JP3361553B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device such as a semiconductor acceleration sensor.

[0002]

2. Description of the Related Art Conventionally, electrochemical etching has been performed for the purpose of accurately forming a thin portion (diaphragm) of a semiconductor pressure sensor or an acceleration sensor. In this method, a scribe is used as a current supply path in order to accurately etch the entire surface of the processed wafer. In JP-A-61-30039, an N-type high-concentration diffusion layer is formed as the current supply path, but it is more effective to use a metal thin film having a lower resistance than the diffusion layer.

[0003]

However, when a metal thin film is formed on a scribe, which is an area for dicing cut originally, and the dicing cut is performed, chips of the metal thin film are generated and adhere to the chip to cause characteristics. It will cause a defect.

Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of avoiding the problems associated with the dicing cut of a metal thin film for electrochemical etching.

[0005]

SUMMARY OF THE INVENTION This invention includes a first step of preparing a semiconductor wafer having a second conductivity type monocrystalline semiconductor film of the thin film to the first conductivity type monocrystalline semiconductor substrate is formed,
Each chip arranged in the chip formation area of the semiconductor wafer.
Scribe area to scribe area
Extend along the in and along the scribe line
A second step of forming a metal thin film having a lack passage for cutting blade of the dicing cut to the scribing area
Predetermined regions of the single crystal semiconductor substrate is removed by electrochemical etching through the metal thin film which is disposed in a third step to leave a predetermined region of the second conductivity type monocrystalline semiconductor film, the scribe line A gist is a method of manufacturing a semiconductor device, which comprises a fourth step of cutting along with cutting into chips.

[0006] The second step is said after forming the high concentration diffusion layer of the second conductivity type in the scribe area in the second conductivity type monocrystalline semiconductor film is for forming the metal thin film Is desirable. Furthermore, the chip type
Of the second-conductivity-type single-crystal semiconductor film located in the formation region.
Before being located in the central region and the outer periphery of the chip formation region
Between the outer peripheral region of the second conductivity type single crystal semiconductor film,
From the surface of the second conductivity type single crystal semiconductor film, the first conductive film is formed.
Prevention of leakage of the first conductivity type reaching the electric type single crystal semiconductor substrate
The method may further include the step of forming a region.

[0007]

[Action] In the present invention, a semiconductor wafer in which the second conductivity type monocrystalline semiconductor film formed in the first step by the first conductivity type monocrystalline semiconductor substrate a thin film is prepared, the semiconductor by a second step Each placed in the chip formation area of the wafer
Scribe to scribe areas between chip areas
Along the line and along the scribe line.
As described above , a metal thin film having a notch for passage of a dicing cut blade is formed. Then, in the third step, a predetermined region of the single crystal semiconductor substrate is removed by electrochemical etching through the metal thin film arranged in the scribe area, leaving a predetermined region of the second conductivity type single crystal semiconductor film.

Furthermore, the chips are cut along the scribe line by a fourth step. At this time, since the dicing cut blade passes through the cutout portion of the metal thin film, no chips are generated.

[0009]

【Example】

(First Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a perspective view of a semiconductor acceleration sensor. 2 is a plan view of the semiconductor acceleration sensor,
FIG. 3 shows an AA cross section of FIG. This sensor is used in the ABS system of an automobile.

As shown in FIG. 1, a square plate-shaped silicon chip 2 is arranged on a square plate-shaped base 1 made of Pyrex glass. As shown in FIG. 2, the silicon chip 2 has a rectangular frame-shaped first surface whose rear surface is joined to the pedestal 1.
The support part 3 is provided, and the first support part 3 is formed by using the four sides of the silicon chip 2. Four through holes 4a, 4b, 4c, 4d are formed in the first support portion 3 of the silicon chip 2 so as to vertically penetrate therethrough, and the four thin movable portions 5, 6, 7, 8 are thick. It has a structure in which the quadrangular weight parts 9 are connected. Further, in the first support portion 3 of the silicon chip 2, the through hole 1 that penetrates vertically is formed.
0 is formed so as to surround the through holes 4a, 4b, 4c, 4d. The through-hole 10 defines a thick U-shaped second support portion 11 and a thick connecting portion 12.

That is, the second support portion 11 is extended with respect to the thick first support portion 3 joined to the pedestal 1, and the second support portion 11 is provided.
Has a structure in which thin movable parts 5 to 8 are extended. In addition, the through hole 10 allows the first support portion 3 and the second support portion 1 to be formed.
1 has a structure in which it is connected by a connecting portion 12. Further, the second support portion 11 and the weight portion 9 are connected by the movable portions 5 to 8 as described above. The thickness of each of the movable parts 5 to 8 is about 5 μm, and two piezoresistive layers 13a, 13b, 14a, 14b, 15a, 15b, 1 are provided in pairs.
6a and 16b are formed. Further, as shown in FIG. 3, a recess 17 is formed in the center of the upper surface of the pedestal 1 so as not to come into contact when the weight 9 is displaced due to acceleration.

FIG. 4 shows a wiring pattern made of aluminum on the surface of the silicon chip 2. In this embodiment, a wiring 18 for grounding, a wiring 19 for applying a power supply voltage, and an output wiring 20 for extracting a potential difference according to acceleration,
And 21 are formed. Also, one more for these wiring
A set of four wires is prepared. That is, the wiring 22 for grounding, the wiring 23 for applying the power supply voltage, and the wirings 24, 25 for outputting for extracting the potential difference according to the acceleration are formed. The impurity diffusion layer 26 of the silicon chip 2 is interposed in the middle of the wiring 19 for applying the power supply voltage, and the wiring 18 for grounding is arranged on the impurity diffusion layer 26 via the silicon oxide film in a crossing state. . Similarly,
The wiring 23 for applying the power supply voltage is connected to the wiring 19 for applying the power supply voltage via the impurity diffusion layer 27, the wiring 22 for grounding is connected to the wiring 18 for grounding via the impurity diffusion layer 28, and The wiring 24 for output is the impurity diffusion layer 2
It is connected to the output wiring 20 via 9. The output wirings 21 and 25 are connected via an impurity diffusion layer 30 for resistance adjustment. In this embodiment, the wiring 1
Wiring using 8 to 21 is performed.

Then, as shown in FIG. 5, each piezoresistive layer 13a, 13b, 14a, 14b, 15a, 15b, 1
The 6a and 16b are electrically connected so as to form a Wheatstone bridge circuit. Here, the terminal 31 is a grounding terminal, the terminal 32 is a power supply voltage applying terminal, and the terminals 33 and 34 are output terminals for extracting a potential difference according to acceleration.

Next, a method of manufacturing the sensor will be described. Figure 6
26A to 26C show the manufacturing process of the sensor. First, as shown in FIG. 6, a p-type single crystal silicon wafer 35 is prepared,
An n-type epitaxial layer 36 is formed on the surface. Then, as shown in FIG. 7, the p ⁺ diffusion layer 37 is formed in the piezoresistive layer forming region of the epitaxial layer 36, and the n ⁺ diffusion layer 38 is formed on the scribe line. Further, the through holes 4a, 4b, 4c, 4 shown in FIG.
An n ⁺ diffusion layer 39 is formed in the formation region of d and 10. Then, the aluminum 40 is arranged on the n ⁺ diffusion layer 38, and the pad is extended from a part of the aluminum 40. Furthermore, n
⁺ Aluminum 41 as a metal thin film is arranged on the diffusion layer 39.

Here, details of the wiring structure of the aluminum 40 will be described. FIG. 8 shows the plane of the intersection of the aluminum 40 on the substrate. Further, FIG. 9 shows a DD cross section of FIG. As shown in FIG. 9, the aluminum 40 is arranged in the scribe area, and a notch 65 for passage of the dicing cut blade 66 is formed in the center thereof. That is, the width W1 of the notch 65 is equal to the width of the dicing blade 66.
The width is slightly wider than W2. That is, when the dicing cut blade 66 passes through the notch 65 of the aluminum 40, the dicing cut blade 66 and the aluminum 40 do not come into contact with each other.

Further, as shown in FIG. 8, the passage notch 65 of the dicing cutting blade 66 is not formed at the intersection of the aluminum 40. This is to reduce the resistance of the current supply line for performing the electrochemical etching described later.

In FIG. 9, 67 is a silicon oxide film, 68 is an aluminum wiring, and 69 is a passivation film. Subsequently, as shown in FIG. 10, a plasma nitride film (P-SiN) 52 is formed on the back surface of the single crystal silicon wafer 35, and a predetermined patterning is performed by photoetching. Then, a current is supplied to the pad of aluminum 40 to perform electrochemical etching using the n ⁺ diffusion layer 38 as an electrode.

Here, the electrochemical etching will be described in detail. As shown in FIG. 11, KOH aqueous solution (33 wt
%, 82 ° C.) 76 and the Pt (platinum) electrode plate 7 in a KOH aqueous solution.
0 is arranged to face the single crystal silicon wafer 35. Then, a constant voltage power source (2 volts) 71, an ammeter 72, and a contact 73 are connected in series between the aluminum 40 of the single crystal silicon wafer 35 and the Pt electrode plate 70. Also, the controller 7
A start switch 75, an ammeter 72 and a contact 73 are connected to the switch 4. The controller 74 detects the start of etching by the signal from the start switch 75 and detects the energizing current by the signal from the ammeter 72. Further, the controller 74 is adapted to open and close the contact 73. The controller 74 is mainly composed of a microcomputer.

The controller 74 executes the processing shown in FIGS. This processing will be described based on the time chart of FIG. The vertical axis of FIG. 14 represents the value of the energizing current. First, when the etching start signal is input from the start switch 75, the controller 74 starts the process of FIG. The controller 74 contacts 73 at step 101.
Is closed and the flag F is set to "0" in step 102. Further, the controller 74, in step 103, outputs the ammeter
The current value I _i obtained by 2 is read, and step 104
Then, the difference ΔI _i (= I _i −I) between the current value I _i and the previous value I _i-1
i-1 ) is calculated.

The controller 74 then proceeds to step 1
At 05, it is determined whether the rate of change ΔI _i of the energizing current is inverted from positive to negative. That is, it is determined whether or not the energizing current value reaches a peak in FIG. 14 (timing tp in FIG. 14). Controller 74, when the change rate [Delta] I _i of the electric current is not inverted from positive to negative the process returns to step 103, the flag F at step 106 if the rate of change [Delta] I _i of the electric current is inverted from positive to negative to "1" Set.

Further, the controller 74 executes the interrupt processing of FIG. 13 every predetermined time. The controller 74 determines in step 201 whether the flag F is "1", and F = 0
If so, return. On the other hand, the controller 74 uses F = 1
When the change rate [Delta] I _i of the electric current is determined whether it is "0" at step 202, the process returns so [Delta] I _i ≠ 0 becomes [Delta] I _i is negative, during a period tp -t2 in Fig. Then, the controller 74 controls the change rate ΔI
_{When i} becomes "0" (timing t2 in FIG. 14), the contact 73 of FIG. 11 is opened in step 203 to end the energization. Immediately after this energization, the single crystal silicon wafer 35 is taken out from the KOH aqueous solution 76 and the single crystal silicon wafer 35 is washed with water. This completes the electrochemical etching.

The behavior of the energizing current value shown in FIG. 14 will be described. In the first region after the energization is started, the etching of the single crystal silicon wafer 35 proceeds due to the chemical reaction between KOH and silicon. This is because the voltage is supplied to the aluminum 40, but no current is supplied to the single crystal silicon wafer 35 due to the PN junction formed by the single crystal silicon wafer 35 and the epitaxial layer 36. In the second region, which has a peak current, anodization proceeds in the same region due to an electrochemical reaction of the single crystal silicon wafer. This is because the single crystal silicon wafer 35 is etched, the PN junction disappears, and the epitaxial layer 36 to which a voltage is supplied comes into contact with the KOH aqueous solution, so that a current flows and the silicon on the surface of the epitaxial layer 36 is oxidized. Is. Further, the gentle peak in the second region is due to the surface distribution of the thickness of the single crystal silicon wafer 35 (thickness variation).

In the next third region, the current value decreases again, but becomes larger than the current value in the first region. This is because silicon oxide is also etched even though the etching rate is slow, so that the etching of oxide and the oxidation of silicon maintain an equilibrium state. More specifically, the etching rate of silicon oxide with a KOH aqueous solution is about 100 times lower than that of silicon, so that etching of silicon is almost completed.

In this way, the inflection point of the silicon oxide film to the equilibrium current after the peak of the energization current value in the second region is the etching end time. In addition, in FIG. 11, the diameter of the single crystal silicon wafer 35 is 10 cm, and the total value of the etching locations (locations indicated by L in FIG. 11) is 17.4 cm ² .

When performing this electrochemical etching, FIG.
As shown by 0, since the n ⁺ diffusion layer 39 exists in a predetermined region of the epitaxial layer 36 in the chip, the electric current supplied from the n ⁺ diffusion layer 38 is not impaired by the lateral resistance and is sufficiently electric. The chemical etching surface can be supplied. That is, the lateral resistance of the epitaxial layer 36 becomes low, sufficient current is supplied to the portion distant from the voltage supply portion, the anodic oxide film is formed, and the etching easily stops.

Here, as shown in FIGS. 15 and 16, when the p ⁺ diffusion layer 54 reaching the single crystal silicon wafer 35 is formed in the outer peripheral portion of the chip formation region in the epitaxial layer 36, the electrical conductivity shown in FIG. 17 is obtained. Leak generation part of the PN junction at the outermost periphery of the wafer during chemical etching (see B in FIG. 17).
Is electrically isolated from the portion to be etched, and the occurrence of leakage can be prevented, and a uniform thin portion can be formed with high accuracy. That is, when the p ⁺ diffusion layer 54 is not formed, the potential of the outermost peripheral portion of the epitaxial layer 36 is the same as that of the central portion of the epitaxial layer 36, so that a leak occurs at the portion B of FIG. On the other hand, by forming the p ⁺ diffusion layer 54, the outermost peripheral portion of the epitaxial layer 36 has the same potential as the silicon wafer 35, and no leak occurs.

The high-concentration diffusion layer for leak prevention may be formed as follows. First, as shown in FIG. 18, a p ⁺ buried layer 55 is formed on the surface of a p-type single crystal silicon wafer 35, and then an n-type epitaxial layer 3 is formed on the surface of the wafer.
6 is formed. Then, as shown in FIG. 19, ap ⁺ diffusion layer 56 is formed in the epitaxial layer 36 by heat treatment in an oxygen atmosphere, and both 55 and 56 are superposed on each other. After that, electrochemical etching is performed as shown in FIG. This method is advantageous in that the time for deeply diffusing the p ⁺ diffusion layer to the silicon wafer can be shortened, especially when the epitaxial layer is thick.

Further, during the electrochemical etching, as shown in FIG.
As shown in FIG. 22, a platinum ribbon 59 is sandwiched between an alumina support substrate 57 and a silicon wafer 58, and the silicon wafer 58 and the support substrate 57 are fixed with a resin (for example, heat resistant wax) 60. The resin 60 allows the silicon wafer 58 and the platinum ribbon 59 to be etched with an etching solution (for example,
33 wt% KOH solution, 82 ° C) 61 protected. As shown in FIGS. 22 and 23, the platinum ribbon 59 is in the form of a strip plate, and the tip side thereof is wavy. In the platinum ribbon 59, the thickness of this corrugated portion is W in a state where no external force is applied, but the support substrate 5 shown in FIG.
In the state where it is fixed between 7 and the silicon wafer 58, the thickness of the corrugated portion of the platinum ribbon 59 is compressed to W or less, and the force for spreading the silicon wafer 58 and the support substrate 57 acts. Therefore, in this state, the platinum ribbon 5
Electrical contact between 9 and the silicon wafer 58 is reliably ensured. After the electrochemical etching, as shown in FIG. 24, the silicon wafer 58 or the like is dipped in a solvent (for example, trichloroethane) 62 to dissolve the resin 60 and the silicon wafer 58 is taken out. During the immersion of the silicon wafer 58, the corrugated portion of the platinum ribbon 59 exerts a force to push the silicon wafer 58 and the supporting substrate 57 apart, so that the gap between the silicon wafer 58 and the supporting substrate 57 is widened. Therefore, the circulation speed of the solvent 62 by the stirrer 64 is increased in this portion, and the fresh solvent 62 is supplied to the peeling portion, and the peeling time can be shortened.
That is, if the platinum ribbon 59 is not formed into a wavy and compressed state but a flat platinum ribbon is used, the gap between the support substrate 57 and the silicon wafer 58 is narrowed due to the weight of the silicon wafer 58 during the peeling process of the resin 60. However, the peeling time can be shortened by arranging the platinum ribbon 59 in a wavy shape and arranging it in a compressed state.

By such an electrochemical etching, as shown in FIG. 10, a predetermined region of the single crystal silicon wafer 35 is removed to form a groove 42 and a predetermined region of the epitaxial layer 36 remains, so that a thin movable layer is formed. Parts 5, 6,
7, 8 (see FIG. 2) are formed.

Then, as shown in FIG. 25, a predetermined region of the epitaxial layer 36 (a region including the n ⁺ diffusion layer 39) is removed to communicate with the groove 42. As a result, the through holes 4a,
4b, 4c, 4d, 10 (see FIG. 2) are formed. After that, the silicon wafer 35 is anodically bonded onto the pedestal 1 made of Pyrex glass.

Finally, as shown in FIG. 26, the scribe line is diced and cut, and the silicon wafer 35 and the pedestal 1 are cut into a predetermined size as shown in FIG. At this time, as shown in FIG.
When the dicing-cut blade 66 passes through the notch 65, the dicing-cut blade 66 and the aluminum 40 do not come into contact with each other. That is, since the dicing cutting blade 66 passes through the cutout portion of the aluminum 40, no chips are generated.

As described above, in this embodiment, the thin n-type epitaxial layer 36 (second conductivity type single crystal semiconductor) is formed on the p type single crystal silicon wafer 35 (first conductivity type single crystal semiconductor substrate). A film 40 is formed (first step), and aluminum 40 having notches 65 for passage of dicing cutting blades 66 is provided on the scribe lines in the epitaxial layer 36.
(Metal thin film) is formed (second step), and a predetermined area of the single crystal silicon wafer 35 is removed by electrochemical etching through the aluminum 40 on the scribe line, leaving a predetermined area of the epitaxial layer 36 (third step). ), The scribe line was cut into chips (fourth step).

In the fourth step, since the dicing cutting blade 66 passes through the cutout portion of the aluminum 40, no chips are generated and it is possible to avoid a characteristic defect due to the adhesion of the chips to the chip. Further, when there is no cutout 65 for passage of the dicing cutting blade 66 on the scribe line, the work is difficult because it is not possible to know where to cut because the aluminum 40 is formed on the scribe area. However, in this embodiment, by using the cutout 65 for passage of the dicing cut blade 66 as a cutting mark, a predetermined scribe line can be reliably cut and the workability is improved.

The aluminum 40 was formed after the n ⁺ diffusion layer 38 (second conductivity type high-concentration diffusion layer) was formed on the scribe line in the epitaxial layer 36. Therefore, the n ⁺ diffusion layer 38 on the scribe line can be used as an electrode, and the electrical connection can be made more reliably.

[0036] Also, with the aluminum 40 and the n ⁺ diffusion layer 38 is disposed in a region to be a scribe cutting portion, since the n ⁺ diffusion layer 39 is disposed in the through hole forming area, aluminum 40, n ⁺ diffusion layer Due to the arrangement of 38 and 39, the area inside the chip does not increase.

As an application example of this embodiment, in FIG. 8, the notch 65 for passing the dicing cut blade 66 is not provided at the intersection of the aluminum 40, but the dicing cut is also made at the intersection of the aluminum 40. A notch 65 for passage of the blade 66 may be provided. In this way, the resistance is increased as compared with the above-mentioned embodiment, but even at the intersection of the aluminum 40, the dicing-cut blade 66 and the aluminum 40 do not come into contact with each other, and the generation of chips can be completely prevented.

Further, in step 105 in FIG.
It may be possible to determine whether or not a predetermined time T (shown in FIG. 14) has elapsed. That is, the time T that becomes an inflection point to a constant current after the energization current peak is experimentally obtained in advance, and the electrochemical etching is terminated when the time T (for example, 5 minutes) has elapsed after the peak. Good.

Further, as shown in FIG. 27, the piezoresistive layers 13a and 1a of FIG.
3b, 14a, 14b, 15a, 15b, 16a, 16
The n ⁺ diffusion layer 43 may be formed in a region other than the region where the b is formed to electrically connect the n ⁺ diffusion layer 39 and the aluminum 40. Further, as shown in FIG. 28, the epitaxial layer 3
6, the piezoresistive layers 13a, 13 of FIG.
b, 14a, 14b, 15a, 15b, 16a, 16b
The aluminum 44 may be arranged in the region other than the region where the wirings 18 to 30 are formed, and the aluminum 41 and the aluminum 40 may be electrically connected to each other. (Second Embodiment) Next, the second embodiment will be described focusing on the differences from the first embodiment.

29 to 35 show the manufacturing process of the sensor. First, as shown in FIG. 29, an n ⁺ diffusion layer 46 is formed on a p-type single crystal silicon wafer 45 by a thermal diffusion method or an ion implantation method. After that, the n-type epitaxial layer 47 is formed on the single crystal silicon wafer 45.

Then, as shown in FIG. 30, the p ⁺ diffusion layer 48 is formed in the piezoresistive layer forming region of the epitaxial layer 47, and the n ⁺ diffusion layer 49 is formed on the scribe line. Further, aluminum 50 is arranged on n ⁺ diffusion layer 49. At this time, in the first embodiment shown in FIG.
As shown in FIG. 9, the aluminum 50 (metal thin film) having the cutout 65 for passage of the dicing cut blade 66 is formed on the scribe line in the epitaxial layer 47.

Then, as shown in FIG. 31, a plasma nitride film (P-SiN) is formed on the back surface of the single crystal silicon wafer 45.
53 is formed and a predetermined patterning is performed by photoetching. And n on the scribe line
^{Using the +} diffusion layer 49 as an electrode, a predetermined area of the single crystal silicon wafer 45 is removed by electrochemical etching to form a groove 51.
Is formed and a predetermined region of the epitaxial layer 47 and the n ⁺ diffusion layer 46 is left.

The electrochemical etching at this time is also performed as shown in FIGS. 11, 12, 13, and 14 in the first embodiment. That is, electrochemical etching is performed through the aluminum 50 in a state where the single crystal silicon wafer 45 is immersed in a KOH aqueous solution, and the electrochemical etching is terminated at the inflection point to a constant current after the peak of the energizing current. A predetermined region of the crystalline silicon wafer 45 is removed, leaving a predetermined region of the epitaxial layer 47.

Further, during this electrochemical etching,
As shown in FIG. 31, since the n ⁺ diffusion layer 46 exists between the single crystal silicon wafer 45 and the epitaxial layer 47, the current supplied from the n ⁺ diffusion layer 49 is not impaired by the lateral resistance. It is sufficient to supply the electrochemically etched surface. That is, the lateral resistance of the epitaxial layer 47 becomes low, and a sufficient current is supplied to a portion distant from the voltage supply portion to form an anodized film,
Etching is likely to stop.

Here, as shown in FIG. 32, when p ⁺ diffusion layer 63 reaching single crystal silicon wafer 45 is formed in the outer peripheral portion of the chip formation region in epitaxial layer 47, electrochemical etching shown in FIG. 33 is performed. At some time, the leak generating portion (indicated by B in FIG. 33) of the PN junction at the outermost peripheral portion of the wafer and the etched portion are electrically insulated from each other to prevent the leak from occurring and to form a highly accurate and uniform thin portion.

The high-concentration diffusion layer for preventing leakage is formed after the p ⁺ buried layer is formed on the p-type single crystal silicon wafer 45, as described with reference to FIGS. 18 to 20 in the first embodiment. In, the p ⁺ diffusion layer may be formed in the n-type epitaxial layer 47, and both may be overlapped with each other.

Thereafter, as shown in FIG. 34, predetermined regions of the epitaxial layer 47 and the n ⁺ diffusion layer 46 are removed to communicate with the groove 51. Then, as shown in FIG. 35, the silicon wafer 4 is placed on the base 1 made of Pyrex glass.
5 is anodically bonded. Finally, the scribe line is cut to form the silicon wafer 45 and the pedestal 1 into chips.

At this time, as shown in FIG. 9 in the first embodiment, when the dicing cut blade 66 passes through the notch 65 of the aluminum 50, the dicing cut blade 66 is used.
Does not come into contact with aluminum 50.

As an application of this embodiment, the n ⁺ diffusion layer 4 is used.
6 is not formed on the single crystal silicon wafer 45, but
The epitaxial layer may have a two-layer structure, an n ⁺ layer may be formed as a lower layer, and the upper layer may be an n-type layer.

[0050]

As described above in detail, according to the present invention,
It has an excellent effect of avoiding the problems caused by the dicing cut of the metal thin film for electrochemical etching.

[Brief description of drawings]

FIG. 1 is a perspective view of a semiconductor acceleration sensor according to an embodiment.

FIG. 2 is a plane surface of a semiconductor acceleration sensor.

3 is a cross-sectional view taken along the line AA of FIG.

FIG. 4 is a plan view of a silicon chip showing a wiring pattern.

FIG. 5 is an electrical connection diagram showing connection of resistance layers.

FIG. 6 is a cross-sectional view showing the manufacturing process of the sensor according to the first embodiment.

FIG. 7 is a cross-sectional view showing the manufacturing process of the sensor.

FIG. 8 is a plan view of an intersection of aluminum.

9 is a cross-sectional view taken along the line DD of FIG.

FIG. 10 is a cross-sectional view showing the manufacturing process of the sensor.

FIG. 11 is a schematic view showing an electrochemical etching apparatus.

FIG. 12 is a flowchart for explaining an electrochemical etching operation.

FIG. 13 is a flowchart for explaining an electrochemical etching operation.

FIG. 14 is a time chart for explaining an electrochemical etching operation.

FIG. 15 is a plan view of a silicon wafer.

FIG. 16 is a cross-sectional view showing the manufacturing process of the sensor.

FIG. 17 is a cross-sectional view showing the manufacturing process of the sensor.

FIG. 18 is a cross-sectional view showing the manufacturing process of the sensor.

FIG. 19 is a cross-sectional view showing the manufacturing process of the sensor.

FIG. 20 is a cross-sectional view showing the manufacturing process of the sensor.

FIG. 21 is a cross-sectional view for explaining electrochemical etching.

22 is a view on arrow C in FIG. 21. FIG.

FIG. 23 is a side view of a platinum ribbon.

FIG. 24 is a cross-sectional view showing the manufacturing process of the sensor.

FIG. 25 is a cross-sectional view showing the manufacturing process of the sensor.

FIG. 26 is a cross-sectional view showing the manufacturing process of the sensor.

FIG. 27 is a cross-sectional view showing an application example of the first embodiment.

FIG. 28 is a cross-sectional view showing an application example of the first embodiment.

FIG. 29 is a cross-sectional view showing the manufacturing process of the sensor according to the second embodiment.

FIG. 30 is a cross-sectional view showing the manufacturing process of the sensor.

FIG. 31 is a cross-sectional view showing the manufacturing process of the sensor.

FIG. 32 is a cross-sectional view showing the manufacturing process of the sensor.

FIG. 33 is a cross-sectional view showing the manufacturing process of the sensor.

FIG. 34 is a cross-sectional view showing the manufacturing process of the sensor.

FIG. 35 is a cross-sectional view showing the manufacturing process of the sensor.

[Explanation of symbols]

35 p-type single crystal silicon wafer as a first conductivity type single crystal semiconductor substrate 36 n type epitaxial layer as a second conductivity type single crystal semiconductor film 38 n ⁺ as a second conductivity type high concentration diffusion layer Diffusion layer 40 Aluminum as metal thin film 54 P ⁺ diffusion layer 65 constituting a leak prevention region Cutout 66 for passing Dicing cutting blade

Claims (3)

(57) [Claims] 1. A semiconductor web of second conductivity type monocrystalline semiconductor film of a first conductivity type monocrystalline semiconductor substrate a thin film is formed
The first step of preparing the c and each chip arranged in the chip formation area of the semiconductor wafer.
Scribe area to scribe area
Extend along the in and along the scribe line
Removing a predetermined region of the monocrystalline semiconductor substrate and a second step of forming a metal thin film having a lack passage for cutting blade of dicing, by electrochemical etching through the metal thin film disposed on the scribe area as and manufacturing a semiconductor device characterized by comprising a third step of leaving a predetermined region of the second conductivity type monocrystalline semiconductor film, and a fourth step of chips by cutting along said scribing line Method. Wherein said second step, after forming the high concentration diffusion layer of the second conductivity type in the scribe area in said second conductivity type monocrystalline semiconductor film is for forming the metal thin film according Item 2. A method of manufacturing a semiconductor device according to item 1. 3. The first member located in the chip formation region
The central region of the two-conductivity type single crystal semiconductor film and the chip type
The second-conductivity-type single crystal semiconductor located on the outer periphery of the formation region
The second conductivity type single crystal half is formed between the outer peripheral region of the body film and
From the surface of the conductive film to the first conductivity type single crystal semiconductor substrate
To form a first conductivity type leak prevention region.
The method according to claim 1 or 2, characterized in that
Method for manufacturing mounted semiconductor device.