JPH01233724A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01233724A JPH01233724A JP6086088A JP6086088A JPH01233724A JP H01233724 A JPH01233724 A JP H01233724A JP 6086088 A JP6086088 A JP 6086088A JP 6086088 A JP6086088 A JP 6086088A JP H01233724 A JPH01233724 A JP H01233724A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- opening
- opening part
- diffusion region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000009792 diffusion process Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 238000009499 grossing Methods 0.000 claims description 2
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 239000012530 fluid Substances 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
従来の半導体装置は、第３図に示すように、ｐ型シリコ
ン基板１０表面に不純物を導入してｎ型゛拡散領域２を
形成し、ｎ型拡散領域２の上に硼素及び燐を含有する酸
化シリコン膜（以下ＢＰＳＧ膜と記す）３を形成する。As shown in FIG. 3, in a conventional semiconductor device, an impurity is introduced into the surface of a p-type silicon substrate 10 to form an n-type diffusion region 2, and boron and phosphorus are contained on the n-type diffusion region 2. A silicon oxide film (hereinafter referred to as BPSG film) 3 is formed.
次に、ＢＰＳＧ膜３を選択的にエツチングしてコンタク
ト用開口部６を設けた後、熱処理によ、ｊ９８ＰＳＧ膜
３を流動化させ開口部６の上端を滑らかにする。こ＼で
、開口部６を等方性エツチングと異方性エツチングの組
合せによ多形成して開口部６の上端にテーパーを付ける
こともできる。次に、開口部６を含む表面にアルミニウ
ム膜を堆積し、これを選択的にエツチングしてｎ型拡散
領域２とコンタクトする電極配線８を形成する。Next, the BPSG film 3 is selectively etched to form a contact opening 6, and then the j98PSG film 3 is fluidized and the upper end of the opening 6 is smoothed by heat treatment. Here, the opening 6 can be formed by a combination of isotropic etching and anisotropic etching, and the upper end of the opening 6 can be tapered. Next, an aluminum film is deposited on the surface including the opening 6 and selectively etched to form an electrode wiring 8 in contact with the n-type diffusion region 2.
上述した従来の半導体装置は、絶縁膜の熱処理による流
動性が少なかったシ、絶縁膜の等方性エツチング速度が
小さいか又はホトレジスト膜が長時間のウェットエツチ
ングに耐えられない等によりコンタクト用開口部のテー
パーが充分形成できず、コンタクト開口部に設けた電極
配線のステップカバレージが不充分で断線等の事故を生
ずるという問題点があった。In the conventional semiconductor devices described above, contact openings are difficult to form because the insulating film has low fluidity due to heat treatment, the isotropic etching rate of the insulating film is low, or the photoresist film cannot withstand long-term wet etching. There was a problem in that a sufficient taper could not be formed, and the step coverage of the electrode wiring provided in the contact opening was insufficient, resulting in accidents such as disconnection.
本発明の目的はコンタクト用開口部における電極配線の
ステップカバレージを改善して信頼性を向上させた半導
体装置の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that improves reliability by improving step coverage of electrode wiring in a contact opening.
本発明の半導体装置の製造方法は、−導電型半導体基板
の一主面に逆導電型の拡散領域を設け前記拡散領域を含
む表面に熱処理による流動性を有する第１の絶縁膜及び
前記第１の絶縁膜よりエッチング速度の大きい第２の絶
縁膜を順次積層して設ける工程と、前記第２の絶縁膜上
にバター二／グされたホトレジスト膜を設ける工程と、
前記ホトレジスト膜をマスクとして前記第２の絶縁膜を
等方性エツチングし、再度前記ホトレジスト膜をマスク
として前記第１の絶縁膜を異方性エツチングして盃状の
開口部を設ける工程と、前記ホトレジスト膜を除去した
後熱処理により前記開口部内壁を滑らかにする工程と、
前記開口部を含む表面に金属膜を堆積しこれを選択的に
エツチングして前記拡散領域とコンタクトし前記第２の
絶縁膜上に延在する電極配線を設ける工程とを含んで構
成される。The method for manufacturing a semiconductor device of the present invention includes: - providing a diffusion region of an opposite conductivity type on one main surface of a conductivity type semiconductor substrate; a first insulating film having fluidity by heat treatment on the surface including the diffusion region; a step of sequentially laminating and providing a second insulating film having a higher etching rate than the insulating film; a step of providing a butter-printed photoresist film on the second insulating film;
isotropically etching the second insulating film using the photoresist film as a mask, and anisotropically etching the first insulating film again using the photoresist film as a mask to provide a cup-shaped opening; Smoothing the inner wall of the opening by heat treatment after removing the photoresist film;
The method includes the step of depositing a metal film on the surface including the opening and selectively etching the metal film to provide an electrode wiring that contacts the diffusion region and extends on the second insulating film.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｅ）は本発明の第１の実施例を説明す
るための工程順に示した半導体チップの断面図でおる。FIGS. 1A to 1E are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.
第１図（ａ）に示すように、ｐ型シリコン基板１の一主
面に不純物を導入してｎ型拡散領域２を形成し、ＣＶＤ
法等によｌ）ｎ型拡散領域２の上に厚さ０．５μｍのＢ
ＰＳＧ膜３と厚さ０．５μｍの酸化シリコン膜４とを順
次堆積して設けてブレベークする。次に、酸化シリコン
膜４の上にコンタクト開口部形成用パターンを有するホ
トレジスト膜５を選択的に設ける。As shown in FIG. 1(a), impurities are introduced into one main surface of a p-type silicon substrate 1 to form an n-type diffusion region 2, and CVD
l) B layer with a thickness of 0.5 μm on the n-type diffusion region 2
A PSG film 3 and a silicon oxide film 4 having a thickness of 0.5 .mu.m are sequentially deposited and then bre-baked. Next, a photoresist film 5 having a pattern for forming a contact opening is selectively provided on the silicon oxide film 4.
次に、第１図（ｂ）に示すように、ホトレジスト膜５を
マスクとしてバッフアート弗酸による等方性エツチング
法により＆化シリコン膜４をエツチングしてホトレジス
ト膜５のパターンの垂直投影面積より僅かに広い面積に
ＢＰＳＧ膜３の表面を露出させる。このとき、酸化シリ
コン膜４のエツチング速度はＢＰＳＧ膜３に対して３〜
１０倍大きいため、ＢＰＳＧ膜３をエツチングストッパ
としてすシ鉢状の開口部が形成できる。Next, as shown in FIG. 1(b), using the photoresist film 5 as a mask, the & silicon oxide film 4 is etched by an isotropic etching method using buffered hydrofluoric acid, and the vertical projected area of the pattern of the photoresist film 5 is etched. The surface of the BPSG film 3 is exposed over a slightly wider area. At this time, the etching rate of the silicon oxide film 4 is 3 to 3 with respect to the BPSG film 3.
Since it is 10 times larger, a bowl-shaped opening can be formed using the BPSG film 3 as an etching stopper.
次に、第１図（Ｃ）に示すように、再度ホトレジスト膜
５をマスクとして異方性のプラズマエツチング法によｆ
ｉ ＢＰＳＧ膜３をエツチングし、ｎ型拡散領域２の表
面を露出させ、盃状のコンタクト用開口部６を形成する
。Next, as shown in FIG. 1C, an anisotropic plasma etching process is performed again using the photoresist film 5 as a mask.
i The BPSG film 3 is etched to expose the surface of the n-type diffusion region 2, and a cup-shaped contact opening 6 is formed.
次に、第１図（ｄ）に示すように、ホトレジスト膜５を
除去し、不活性雰囲気中で熱処理を行いＢＰ８Ｇ膜３の
肩部７を流動化させて表面張力により開口部を滑らかに
する。Next, as shown in FIG. 1(d), the photoresist film 5 is removed and heat treatment is performed in an inert atmosphere to fluidize the shoulder portion 7 of the BP8G film 3 and smooth the opening due to surface tension. .
この時、酸化シリコン膜４はほとんど流動しないので、
ＢＰＳＧ膜３は上下を固定された形となシ、酸化シリコ
ン膜４の上面から、ｎ型拡散領域２の表面まで連続的に
つながる滑らかな開口部が形成できる。At this time, the silicon oxide film 4 hardly flows, so
Since the BPSG film 3 has a fixed top and bottom shape, a smooth opening can be formed continuously from the top surface of the silicon oxide film 4 to the surface of the n-type diffusion region 2.
次に、第１図（ｅ）に示すように、開口部６を含む表面
にアルミニウム層を堆積し、これを選択的にエツチング
して、開口部６のｎ型拡散領域２と接続し酸化シリコン
膜４の上に延在する電極配線８を形成する。このように
開口部６が滑らかなテーパーを有するため、電極配線８
のステップカバレージが良好となる効果がある。Next, as shown in FIG. 1(e), an aluminum layer is deposited on the surface including the opening 6, and this is selectively etched to connect the n-type diffusion region 2 of the opening 6 to the silicon oxide layer. Electrode wiring 8 is formed extending over the film 4. Since the opening 6 has a smooth taper in this way, the electrode wiring 8
This has the effect of improving step coverage.
第２図は本発明の第２の実施例を説明するための半導体
テップの断面図でおる。FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.
図に示すように、第１の実施例と同じ工程でＢｌ’ Ｓ
Ｇ膜３を形成した後、ＢＰＳＧ膜３の上に多結晶シリコ
ン膜９を堆積して、これを選択的にエツチングし配線を
形成する。次に、多結晶シリコン膜９を含む表面に厚さ
０．２μｍのＢＰＳＧ膜１０膜厚００．５μｍｏＰｓＧ
膜１１を順次横１１て設ける。As shown in the figure, in the same process as in the first example, Bl' S
After forming the G film 3, a polycrystalline silicon film 9 is deposited on the BPSG film 3 and is selectively etched to form wiring. Next, on the surface including the polycrystalline silicon film 9, a 0.2 μm thick BPSG film 10 with a thickness of 00.5 μmoPsG
The membranes 11 are sequentially provided horizontally.
次に、ＰＳＧ膜１１を等方性エツチングにより選択的に
エツチングしてｎ型拡散領域２及び多結晶シリコン層９
のコンタクト用のすシ鉢状の開口部をそれぞれ設け、更
に前記開口部の底部のＢＰＳＧ膜１０膜厚０を異方性エ
ツチングして盃状のコンタクト用開口部６及び１２を設
ける。次に、開口部６，１２を含む表面にアルミニウム
層を堆積し、選択的にエツチングしてｎ型拡散領域２と
コンタクトする電極配線８及び多結晶シリコン層９と接
続する配線１３をそれぞれ形成する。Next, the PSG film 11 is selectively etched by isotropic etching to form the n-type diffusion region 2 and the polycrystalline silicon layer 9.
A bowl-shaped contact opening is provided respectively, and the BPSG film 10 at the bottom of the opening is anisotropically etched to form cup-shaped contact openings 6 and 12. Next, an aluminum layer is deposited on the surface including the openings 6 and 12 and selectively etched to form an electrode wiring 8 in contact with the n-type diffusion region 2 and a wiring 13 in contact with the polycrystalline silicon layer 9, respectively. .
以上説明したように本発明は、コンタクト用開口部の第
２の絶縁膜に等方性エツチングによるテーパーを設け、
さらに、第１の絶縁膜を異方性プラズマエツチングして
生じ比肩部を熱処理によって滑らかにすることができる
丸め、電極配線の良好なステップカバレージが得られ、
半導体装置の信頼性を向上させるという効果がある。As explained above, the present invention provides a taper by isotropic etching in the second insulating film of the contact opening,
Furthermore, the first insulating film is rounded by anisotropic plasma etching and the comparable portions can be smoothed by heat treatment, resulting in good step coverage of the electrode wiring.
This has the effect of improving the reliability of the semiconductor device.
第１図（ａ）〜（ｅ）は本発明の第１の実施例を説明す
るための工程順に示した半導体装置の断面図、第２図は
本発明の第２の実施例を説明するための半導体チップの
断面図、第３図は従来の半導体装置の一例を示す半導体
チップの断面図である。
１・・・ｐ型シリコン基板、２・・・ｎ型拡散領域、３
・・・ＢＰＳＧ膜、４・・・酸化シリコン膜、５・・・
ホトレジスト膜％ ６・・・開口部、７・・・肩部、訃
・・電極配線、９・・・多結晶シリコン膜、１０・・・
ＢＩ）ＳＧ膜、１１・・・ＰＳＧ膜、１２・・・開口部
、１３・・・配線。
代理人 弁理士 内 原 音
６閘Ｕ部
／
箒 ｌ 図
Ｉ Ｐ型シソコシ署引ｈ（
第２図
／
第３ 図FIGS. 1(a) to (e) are cross-sectional views of a semiconductor device shown in order of steps for explaining a first embodiment of the present invention, and FIG. 2 is a cross-sectional view for explaining a second embodiment of the present invention. FIG. 3 is a cross-sectional view of a semiconductor chip showing an example of a conventional semiconductor device. 1...p-type silicon substrate, 2...n-type diffusion region, 3
...BPSG film, 4... Silicon oxide film, 5...
Photoresist film% 6...Opening, 7...Shoulder, butt...Electrode wiring, 9...Polycrystalline silicon film, 10...
BI) SG film, 11...PSG film, 12...opening, 13...wiring. Agent Patent Attorney Uchihara Oto 6 Lock U Department / Houki l Figure I P-type Shisokoshi Signature H (Figure 2 / Figure 3
Claims (1)
設け前記拡散領域を含む表面に熱処理による流動性を有
する第１の絶縁膜及び前記第１の絶縁膜よりエッチング
速度の大きい第２の絶縁膜を順次積層して設ける工程と
、前記第２の絶縁膜上にパターニングされたホトレジス
ト膜を設ける工程と、前記ホトレジスト膜をマスクとし
て前記第２の絶縁膜を等方性エッチングし、再度前記ホ
トレジスト膜をマスクとして前記第１の絶縁膜を異方性
エッチングして盃状の開口部を設ける工程と、前記ホト
レジスト膜を除去した後熱処理により前記開口部内壁を
滑らかにする工程と、前記開口部を含む表面に金属膜を
堆積しこれを選択的にエッチングして前記拡散領域とコ
ンタクトし前記第２の絶縁膜上に延在する電極配線を設
ける工程とを含む半導体装置の製造方法。A diffusion region of an opposite conductivity type is provided on one main surface of a semiconductor substrate of one conductivity type; a first insulating film having fluidity due to heat treatment on the surface including the diffusion region; and a second insulating film having a higher etching rate than the first insulating film. a step of providing a patterned photoresist film on the second insulating film, isotropically etching the second insulating film using the photoresist film as a mask, and etching the second insulating film again. a step of anisotropically etching the first insulating film using the photoresist film as a mask to provide a cup-shaped opening; a step of smoothing the inner wall of the opening by heat treatment after removing the photoresist film; A method for manufacturing a semiconductor device, comprising the steps of depositing a metal film on a surface including an opening and selectively etching the metal film to provide an electrode wiring that contacts the diffusion region and extends on the second insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6086088A JPH01233724A (en) | 1988-03-14 | 1988-03-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6086088A JPH01233724A (en) | 1988-03-14 | 1988-03-14 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01233724A true JPH01233724A (en) | 1989-09-19 |
Family
ID=13154561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6086088A Pending JPH01233724A (en) | 1988-03-14 | 1988-03-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01233724A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5246883A (en) * | 1992-02-06 | 1993-09-21 | Sgs-Thomson Microelectronics, Inc. | Semiconductor contact via structure and method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6068613A (en) * | 1983-09-26 | 1985-04-19 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS60227443A (en) * | 1984-04-26 | 1985-11-12 | Nec Corp | Manufacture of semiconductor device |
-
1988
- 1988-03-14 JP JP6086088A patent/JPH01233724A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6068613A (en) * | 1983-09-26 | 1985-04-19 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS60227443A (en) * | 1984-04-26 | 1985-11-12 | Nec Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5246883A (en) * | 1992-02-06 | 1993-09-21 | Sgs-Thomson Microelectronics, Inc. | Semiconductor contact via structure and method |
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