JPS6254427A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6254427A JPS6254427A JP16887485A JP16887485A JPS6254427A JP S6254427 A JPS6254427 A JP S6254427A JP 16887485 A JP16887485 A JP 16887485A JP 16887485 A JP16887485 A JP 16887485A JP S6254427 A JPS6254427 A JP S6254427A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- opening
- mask
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、 IrflC
。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device,
.
絶縁膜に設は次間口部における断線のない配線を有する
半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device having wiring in an insulating film that does not cause disconnection in the opening.
従来、素子が形成された半導体基板上の絶縁膜に電極取
り出し用の開口埋金形成する方法、さらに配線が多層と
なる場合、金属配線間に設は几絶縁膜に層間接続用の開
口部を形成する方法は、絶縁膜上に所定の開口部を有す
るレジスト膜を形成し、この開口部に露出している絶縁
膜を一度にエツチングした後、レジスト膜を除去して、
第2図(alに示すように、半導体基板1の上の絶縁膜
2に所定の開口部3t−設けていた。つぎに同図(b)
に示すように、配線金属5例えばアルミニウムをスパッ
タリング法により被着し、パターンニングで配線6t−
形成していた。Conventionally, there has been a method of filling an opening for electrode extraction in an insulating film on a semiconductor substrate on which an element is formed, and in addition, when the wiring is multilayered, openings for interlayer connections are formed in the insulating film between the metal wirings. The formation method is to form a resist film having a predetermined opening on the insulating film, to etch the insulating film exposed in the opening at once, and then to remove the resist film.
As shown in FIG. 2 (al), a predetermined opening 3t was provided in the insulating film 2 on the semiconductor substrate 1. Next, as shown in FIG.
As shown in FIG.
was forming.
上述した従来の半導体基板上の絶縁膜に開口部を設け、
配線を形成するには、開口部の絶縁膜を−iにエツチン
グ処理により除去してしまうため、開口部の断面が急峻
な形状となり1次に被着したアルミ配線は、開口部段部
での膜厚が薄くなり。An opening is provided in the insulating film on the conventional semiconductor substrate described above,
To form the wiring, the insulating film at the opening is removed by -i etching, resulting in a steep cross-section of the opening and the aluminum wiring deposited on the first layer is difficult to form at the step of the opening. The film thickness becomes thinner.
ついには配線の断線の原因となり、半導体装置の信頼性
を低下させる。Eventually, this will cause disconnection of the wiring, reducing the reliability of the semiconductor device.
また、断線を防止する方法としては、絶縁膜の開口部の
段部の傾斜をゆるやかにする方法があるが、傾斜をゆる
やかにするtめに加工精度が落ち、また、傾斜部の占有
面積が大きくなり、集積度を低下させる。断線を防止す
る他の方法としては、配線金属の膜厚を厚くする方法も
あるが、この方法もま九微細化が困難となり集積$t−
低下させるという欠点がある。In addition, one way to prevent wire breakage is to make the slope of the stepped part of the opening in the insulating film gentler, but as the slope becomes gentler, the processing accuracy decreases, and the area occupied by the slope part increases. becomes larger and reduces the degree of integration. Another method to prevent wire breakage is to increase the thickness of the wiring metal, but this method also makes it difficult to miniaturize and increases the cost of integration.
It has the disadvantage of lowering
本発明の半導体装置の製造方法における絶縁膜の開口部
の形成方法は、第1の絶縁膜に写真食刻技術により所定
の開口部を設けた後、第2の絶縁膜をスパッタリング法
により形成するが、このスパッタリング時、半導体基板
にバイアスを印加することにより1段部が所望の傾斜を
持つようになる。さらに、再び写真食刻技術により開口
部のエツチングを行ない所定の開口部を形成し、この開
口部を通して下層の導体ま几は基板に接続した配線を形
成する。The method for forming an opening in an insulating film in the method for manufacturing a semiconductor device of the present invention includes forming a predetermined opening in a first insulating film by photolithography, and then forming a second insulating film by a sputtering method. However, during this sputtering, by applying a bias to the semiconductor substrate, the first step part can have a desired slope. Further, the openings are etched again by photolithography to form predetermined openings, and through these openings the underlying conductor is connected to the substrate to form wiring.
つぎに本発明を実施例によシ説明する。 Next, the present invention will be explained using examples.
第1図(a)ないしくflは本発明の一実施例に係るア
ルミ配線の形成方法を工程順に説明するtめの断面図で
ある。まず、第1図(alのように、シリコン基板1の
上を500〜8000人1例えば5ooo人の第1の絶
縁膜1例えばシリコン酸化膜2で被った後、その上にフ
ォトレジスト膜3を形成し、写真蝕刻技術により、開孔
3a fあける。つぎに反応性イオンエツチングにより
、フォトレジスト膜3をマスクとしてシリコン酸化膜2
をエツチング除去した後、フォトレジスト膜3t−除去
し、第1図の)の状態にする。次にシリコン基板1];
負のバイアスを印加して、スパッタリング法により、第
2の絶縁膜1例えばシリコン酸化膜4t−1000〜1
0000に1例えば6000人の厚さに形成して。FIGS. 1A to 1F are t-th cross-sectional views illustrating a method for forming an aluminum wiring according to an embodiment of the present invention in the order of steps. First of all, as shown in FIG. The silicon oxide film 2 is then formed by reactive ion etching using the photoresist film 3 as a mask.
After removing the photoresist film 3t by etching, the photoresist film 3t is removed, resulting in the state shown in FIG. Next, silicon substrate 1];
Applying a negative bias, the second insulating film 1, for example, a silicon oxide film 4t-1000 to 1, is formed by sputtering.
Formed to a thickness of 1 in 0,000, for example 6,000 people.
第1図fc)に示すようにする。この時、シリコン基板
に印加するバイアスの大きさにより段部での傾斜角αを
自由に変えることができる。つぎに第1図(d)のよう
に、再びフォトレジスト膜5t−形成し。As shown in Fig. 1 fc). At this time, the inclination angle α at the step portion can be freely changed by changing the magnitude of the bias applied to the silicon substrate. Next, as shown in FIG. 1(d), a photoresist film 5t is formed again.
写真食刻技術によりバターニングしエツチングマスク用
の開口部5aを形成する。次に前述と同様にスパッタリ
ング法により形成し九シリコン酸化膜4を反応性イオン
エツチング法によシエッチング除去した後、フォトレジ
スト膜5を除去し、第1図te+の状態にする。次に配
線金属として例えばアルミニウム膜6をスパッタリング
法により形成し友状態金第1図(flに示す。この図か
られかるように、開口部側面でも平坦部と同じ厚さにア
ルミニウム膜6が被着している。The opening 5a for an etching mask is formed by buttering by photolithography. Next, the silicon oxide film 4 formed by the sputtering method as described above is etched away by the reactive ion etching method, and then the photoresist film 5 is removed to form the state shown in FIG. Next, as a wiring metal, for example, an aluminum film 6 is formed by sputtering, and the aluminum film 6 is coated on the side surface of the opening to the same thickness as the flat part. I'm wearing it.
なお、スパッタリング法により形成され九シリコン酸化
膜をエツチング除去する場合に使用するマスクは、第1
回目のエツチングに使用し友マスクと同一でも異なって
いてもよく、必ずしも開口部の大きさが同じ必要はない
。ま几、前記第2の絶縁膜は、シリコン酸化膜の他に、
シリコン窒化膜、または酸化アルミニウム膜を用いるこ
ともできる。Note that the mask used when etching away the silicon oxide film formed by the sputtering method is the first one.
The mask used for the second etching may be the same as or different from the companion mask, and the openings do not necessarily have to be the same size. In addition to the silicon oxide film, the second insulating film is made of
A silicon nitride film or an aluminum oxide film can also be used.
ま几、本実施例は半導体基板と配線金属の接続の場合に
ついて説明し九が、半導体基板と多結晶シリコン、配線
金属と配線金属の接続のための開口部を形成する場合等
についても同様である。Although this embodiment describes the case of connecting a semiconductor substrate and a wiring metal, the same applies to the case of forming an opening for connecting a semiconductor substrate and polycrystalline silicon, or wiring metal to wiring metal. be.
以上説明し几ように本発明に係る絶縁膜の開口部の形成
方法では、開口部の断面の形状が側面の上部で一定の傾
斜を持って広がっているため、次に配線金属として、た
とえばアルミニウムを被着した時に、開口部の側面にも
平坦部と同じ厚さにアルミニウム膜が形成され、配線の
断線は生じず信頼性が向上する。さらに、開口部側面の
下部の断面形状は半導体基板に対してほぼ垂直となり微
細化にも適しているため集積度を低下させることもない
。As explained above, in the method for forming an opening in an insulating film according to the present invention, the cross-sectional shape of the opening widens at a certain slope at the upper part of the side surface. When deposited, an aluminum film is formed on the side surfaces of the opening to the same thickness as the flat portion, preventing wiring breakage and improving reliability. Furthermore, since the cross-sectional shape of the lower part of the side surface of the opening is substantially perpendicular to the semiconductor substrate and is suitable for miniaturization, there is no reduction in the degree of integration.
第1図(alないしくf)は本発明の一実施例に係るア
ルミ配線形成工程を説明するための工程順の断面図、第
2図fat 、 (b)は従来のアルミ配線形成工程を
説明するための断面図である。
1・・・・・・シリコン基板、2・・・・・・第1の絶
縁膜、3゜5・・・・・・フォトレジスト膜、4・・・
・・・第2の絶縁膜。
6・・・・・・アルミニウム膜。
代理人 弁理士 内 原 晋
(b) (e)0
゛′ 豪1ヅ °f)
(i 、2図 cb)Figure 1 (al to f) is a cross-sectional view of the process order for explaining the aluminum wiring forming process according to an embodiment of the present invention, and Figure 2 (fat) and (b) are illustrating the conventional aluminum wiring forming process. FIG. DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2...First insulating film, 3°5...Photoresist film, 4...
...Second insulating film. 6...Aluminum film. Agent Patent Attorney Susumu Uchihara (b) (e) 0
゛′ Australia 1ヅ °f) (i, Figure 2 cb)
Claims (4)
む半導体装置の製造方法において、素子が形成された半
導体基板上又は、素子に所望の配線が形成された半導体
基板上に第1の絶縁膜を形成し、この第1の絶縁膜にマ
スクを用いたエッチング処理により所定の開口を設け、
つぎに、前記半導体基板にバイアスを印加して第2の絶
縁膜をスパッタリング法により形成した後、マスクを用
いて前記所定の開口部の前記第2の絶縁膜をエッチング
処理により除去する工程を含むことを特徴とする半導体
装置の製造方法。(1) In a method of manufacturing a semiconductor device that includes forming an opening in an insulating film on a semiconductor substrate, a first forming an insulating film, and providing a predetermined opening in this first insulating film by etching using a mask;
Next, the step includes applying a bias to the semiconductor substrate to form a second insulating film by a sputtering method, and then removing the second insulating film in the predetermined opening by etching using a mask. A method for manufacturing a semiconductor device, characterized in that:
ン窒化膜又は酸化アルミニウムを用いることを特徴とす
る特許請求の範囲第1項に記載の半導体装置の製造方法
。(2) The method for manufacturing a semiconductor device according to claim 1, wherein a silicon oxide film, a silicon nitride film, or an aluminum oxide film is used as the second insulating film.
第2の絶縁膜の膜厚を1000〜10000Åとするこ
とを特徴とする特許請求の範囲第1項に記載の半導体装
置の製造方法。(3) The thickness of the first insulating film is 500 to 8000 Å,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film has a thickness of 1,000 to 10,000 Å.
して、異方性エッチを用いることを特徴とする特許請求
の範囲第1項に記載の半導体装置の製造方法。(4) The method for manufacturing a semiconductor device according to claim 1, wherein anisotropic etching is used as a method for etching away the insulating film in the opening.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16887485A JPS6254427A (en) | 1985-07-31 | 1985-07-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16887485A JPS6254427A (en) | 1985-07-31 | 1985-07-31 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6254427A true JPS6254427A (en) | 1987-03-10 |
Family
ID=15876161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16887485A Pending JPS6254427A (en) | 1985-07-31 | 1985-07-31 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6254427A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5951286A (en) * | 1982-09-10 | 1984-03-24 | Sankyo Co Ltd | Preparation of carbapenem derivative |
EP0516486A2 (en) | 1991-05-31 | 1992-12-02 | Sankyo Company Limited | Azetidinone derivatives useful in the preparation of carbapenem antibiotics |
US5260438A (en) * | 1992-04-28 | 1993-11-09 | Tanabe Seiyaku Co., Ltd. | Method for removing the protecting group for hydroxy group |
KR100414949B1 (en) * | 1996-12-28 | 2004-03-31 | 주식회사 하이닉스반도체 | Method for forming contact hole of semiconductor device |
-
1985
- 1985-07-31 JP JP16887485A patent/JPS6254427A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5951286A (en) * | 1982-09-10 | 1984-03-24 | Sankyo Co Ltd | Preparation of carbapenem derivative |
JPS6254427B2 (en) * | 1982-09-10 | 1987-11-14 | Sankyo Kk | |
EP0516486A2 (en) | 1991-05-31 | 1992-12-02 | Sankyo Company Limited | Azetidinone derivatives useful in the preparation of carbapenem antibiotics |
US5260438A (en) * | 1992-04-28 | 1993-11-09 | Tanabe Seiyaku Co., Ltd. | Method for removing the protecting group for hydroxy group |
KR100414949B1 (en) * | 1996-12-28 | 2004-03-31 | 주식회사 하이닉스반도체 | Method for forming contact hole of semiconductor device |
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