JPH0974106A - Epitaxial substrate for field effect transistor - Google Patents

Abstract

(57) [Summary] (Modified) [PROBLEMS] To provide an epitaxial substrate for a high withstand voltage and high quality FET by suppressing the influence of the interface between the substrate and the buffer layer, which is closely related to the field effect transistor (FET) characteristics. . SOLUTION: The semi-insulating G produced by a pyrolysis vapor phase growth method using an organic metal and / or a hydride as a raw material.
An aAs substrate 6, a buffer layer 4, an electron transit layer 3, and a contact layer 1 are laminated in this order to form a field effect transistor epitaxial substrate. The buffer layer 4 is a high resistance layer having a residual carrier concentration of 1 × 10 ¹⁶ cm ⁻³ or less, has an acceptor concentration of 5 × 10 ¹¹ cm ⁻² or less between the substrate 6 and the buffer layer, and is depleted. P-type Al _x Ga
_1-x As It has a layer 5. Further, it is a substrate having an electron supply layer 2 between the electron transit layer 3 and the contact layer 1, and an FET epitaxial substrate in which the layer 5 is doped with carbon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an epitaxial substrate for a field effect transistor (hereinafter sometimes referred to as FET).

[0002]

2. Description of the Related Art When an epitaxial substrate for an FET is grown on a substrate by a thermal decomposition vapor phase epitaxy method, if an electron transit layer is directly grown on the substrate, a deep surface defect due to defects, surface states and impurities on the substrate surface is generated. As a result, the electron mobility is lowered and carriers are compensated, so that a high-quality FET epitaxial substrate cannot be obtained. In order to prevent the influence of the substrate, it is known to grow a high resistance buffer layer between the substrate and the electron transit layer. Also, especially Ga
It is known that the influence of the substrate can be solved by using a Cr-doped GaAs substrate in the As-based FET epitaxial substrate.

However, when a higher quality epitaxial substrate for FETs is required, the influence of the substrate on the buffer layer cannot be ignored, and a new problem occurs at the interface between the substrate and the buffer layer. Came. That is, when the temperature of the substrate is increased by heating, the surface of the substrate is directly exposed to a high temperature, so that the substrate is thermally damaged and the purity of the interface between the substrate and the buffer layer is lowered and the number of defects on the substrate surface is increased. Further, generally, the surface of the substrate is easily polluted, and such contamination cannot be sufficiently removed during the epitaxial growth process, which is also a cause of interface deterioration.

As the interface purity between the substrate and the buffer layer decreases, the resistance of this interface decreases, a leak current flows in this part, the pinch-off characteristic deteriorates, and the drain conductance (g _d ) increases, and The decrease in transconductance (g _m ) at low drain current is large, resulting in deterioration of noise figure.

Further, in the Cr-doped GaAs substrate used as the GaAs-based FET epitaxial substrate, Cr forms a deep level, and a shallow donor or acceptor can be compensated to suppress the above-mentioned influence. Cr diffuses not only into the buffer layer but also into the electron transit layer when the temperature of the substrate is increased by heating,
It has the drawback of compensating for the carrier.

The conventional buffer layer suppresses carrier traps at the interface between the substrate and the electron transit layer and a decrease in electron mobility. However, if the impurity concentration and the number of defects at the interface become too large, this effect cannot be suppressed even if the buffer layer is grown, and there arises a problem that carrier compensation of the electron transit layer and reduction of electron mobility occur.

[0007]

SUMMARY OF THE INVENTION The object of the present invention is to provide FE
It is an object of the present invention to provide an FET epitaxial substrate that suppresses the influence of the interface between the substrate and the buffer layer, which is closely related to T characteristics, and has a high withstand voltage and that can manufacture a high-quality FET.

[0008]

DISCLOSURE OF THE INVENTION The inventors of the present invention have made intensive studies in view of these problems, and as a result, form a specific layer between a buffer layer and a substrate to manufacture a high quality FET. The inventors have found that this can be done and have reached the present invention. That is, the present invention is produced by a thermal decomposition vapor deposition method using an organic metal and / or a hydride as a raw material, and includes a substrate, a buffer layer, an electron transit layer, a contact layer or a substrate, a buffer layer, an electron transit layer, and an electron. In an epitaxial substrate for a field effect transistor, in which a supply layer and a contact layer are laminated in this order, the substrate is a semi-insulating GaAs substrate,
The buffer layer has a residual carrier concentration of 1 × 10 ¹⁶ cm
^-3 or less high-resistance buffer layer and a depleted p-type Al _x Ga ₁ having a sheet acceptor concentration of 5 × 10 ¹¹ cm ^-2 or less between the substrate and the buffer layer. _-x A
The present invention relates to an epitaxial substrate for a field effect transistor, which has an s (0 <x ≦ 1) layer.
Hereinafter, the present invention will be described in detail.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION An epitaxial substrate for a field effect transistor according to the present invention is produced by a thermal decomposition vapor deposition method using an organic metal and / or a hydride as a raw material, and contacts the substrate, a buffer layer, an electron transit layer and a contact. A layer or a substrate, a buffer layer, an electron transit layer, an electron supply layer, and a contact layer are laminated in this order, the substrate is a semi-insulating GaAs substrate, and the buffer layer has a residual carrier concentration of 1 × of 10 ¹⁶ cm ^-3 or less is a high-resistance buffer layer. A feature of the present invention is that between the substrate and the buffer layer,
Has a sheet acceptor concentration of 5 × 10 ¹¹ cm ^-2 or less,
It has a depleted p-type Al _x Ga _1-x As (0 <x ≦ 1) layer.

In the present invention, the buffer layer is a high resistance layer having a residual carrier concentration of 1 × 10 ¹⁶ cm ^-3 or less,
It may be a homobuffer layer, a superlattice buffer layer or the like, and the structure thereof does not matter. Further, the potential of the buffer layer is preferably p-type in order to suppress the short channel effect of the FET.

Further, in the present invention, p-type Al _x Ga _1-x As (0 <x ≦ 1) sandwiched between the substrate and the buffer layer.
The layer avoids excessive reduction of the two-dimensional electron density (Ns) and does not generate p-type neutral regions causing buffer leakage and increased stray capacitance, and in the absence of Ns the substrate interface donor and It is necessary to deplete the anti-insulating GaAs substrate by a deep level (indicating the center of EL2). Here, the depletion means the carrier profile of the buffer layer obtained by the measurement method of obtaining the carrier profile by performing CV measurement while chemically etching the epitaxial substrate for FET.
It means that no profile showing the existence of the p-type layer, which means the generation of the neutral region, is observed. As a commercially available device that can perform the measurement, for example, SPP (Semiconductor Prof) under the trade name of Polaron is used.
ile Plotter). A p-type Al _x Ga _1-x As (0 <x ≦ which is sandwiched between the substrate and the buffer layer.
1) The sheet acceptor concentration of the layer is 5 × 10 ¹¹ c
It is less than m ^-2 .

In the present invention, the p-type Al _x Ga _1-x
The thickness of the As (0 <x ≦ 1) layer is preferably in the range of 50 to 1000Å. In addition, the substrate and p-type Al _x Ga _1-x As (0
G with a thickness of about 50 to 1000Å between the <x ≦ 1) layers
It is preferable to further grow the aAs layer.

Further, the p-type Al _x Ga _1-x As (0 <
The Al composition of the x ≦ 1) layer is preferably 0.2 ≦ x ≦ 0.8. More preferably, 0.4 ≦ x ≦ 0.8. x>
A value of 0.8 is not preferable because it causes instability of the epitaxial growth layer. When x <1, a sufficient acceptor concentration may not be obtained, so it is not so preferable, but it can be used by intentionally adjusting the acceptor concentration by using a dopant as described above.

Further, in the present invention, p-type Al _x Ga
Carbon is preferred as the p-type dopant for the _1-x As (0 <x ≦ 1) layer. Carbon is preferable because it has a small diffusion and a stable epitaxial growth layer can be obtained. Further, it is known that carbon naturally enters the epitaxial growth layer grown by the pyrolysis vapor deposition method using an organic metal or hydride as a raw material by increasing the Al composition.
When the Al composition of the type Al _x Ga _1-x As (0 <x ≦ 1) layer is large, a required acceptor can be introduced without requiring a special dopant. On the other hand, when a sufficient acceptor concentration cannot be obtained when the Al composition is small, it is possible to introduce the required acceptor by intentionally adding impurities that form the acceptor level. Also in this case, carbon is preferable as the dopant.

The epitaxial substrate for a field effect transistor of the present invention is manufactured by a thermal decomposition vapor deposition (hereinafter sometimes referred to as MOVPE) method using an organic metal and / or a hydride as a raw material. In the MOVPE method, the following raw materials can be used. Trimethylgallium [(CH ₃ ) ₃ G as a raw material of Group 3 element
a, hereinafter may be referred to as TMG. ], Triethylgallium [(C ₂ H ₅ ) ₃ Ga, hereinafter may be referred to as TEG. ] R ₁ R ₂ R ₃ Ga (where R ₁ , R
₂ , R ₃ represents a lower alkyl group. ) Trialkylgallium represented by the formula; trimethylaluminum [(CH ₃ ).
₃ Al, hereinafter sometimes referred to as TMA. ], Triethylaluminum [(C ₂ H ₅ ) ₃ Al, hereinafter sometimes referred to as TEA. ] R ₁ R ₂ R ₃ Al (where
R ₁ , R ₂ and R ₃ have the same definition as above. ) Trialkylaluminum represented by); trimethylindium [(CH ₃ ) ₃ In, hereinafter may be referred to as TMI. ], Triethylindium [(C ₂ H ₅ ) ₃ In]
And the general formula R ₁ R ₂ R ₃ In (where R ₁ , R ₂ , R
₃ has the same definition as above. And the like. These are used alone or in combination. Next, among the Group 5 raw materials, as arsenic raw materials,
Generally, arsenic trihydride (arsine) is used, but monoalkylarsine in which one hydrogen of arsine is replaced with an alkyl group having 1 to 4 carbon atoms can also be used. In the present invention, Al _x Ga _1-x A is formed by MOVPE method.
When the s (0 <x ≦ 1) layer is grown, the crystallinity is lowered when the temperature is too low or too high, so that p-type Al _x
The growth temperature of the Ga _1-x As (0 <x ≦ 1) layer is 600 ° C.
It is preferably 750 ° C. or lower.

[0016]

EXAMPLES Examples of the present invention will be shown below, but the present invention is not limited thereto. Example 1 FIG. 1 shows a sectional view of an example (hereinafter referred to as A) of an epitaxial substrate for FET of the present invention. The substrate is semi-insulating GaAs manufactured by the liquid sealing pulling method (LEC).
A substrate was used. On this substrate, an FET epitaxial substrate composed of a buffer layer, an electron transit layer, an electron supply layer, and a contact layer shown in FIG. 1 was formed by a pyrolysis vapor deposition method using organic metal and hydride as raw materials. grown. To alleviate the effect of the substrate surface, grow a 500 Å GaAs layer directly on the substrate and then p-type Al _x Ga _1-x As (x = 0.7)
After the layer was grown to 100Å, a buffer layer, an electron transit layer and an electron supply layer were sequentially grown. Furthermore, a contact layer was grown for the purpose of reducing the contact resistance during electrode formation.

In order to examine the buffer breakdown voltage of this epitaxial substrate, the current-voltage characteristics of the buffer layer were measured.
First, the upper layer is etched and removed from the electron transit layer, and a pattern of an ohmic electrode 5 μm apart is formed on the upper layer by a resist, and AuGe (Ge 12 wt%), N
After depositing i and Au and removing unnecessary portions of the resist and the deposited metal by lift-off, the measurement sample was processed by annealing at 380 ° C. for 90 seconds in a hydrogen atmosphere. In Table 1,
The voltage value (breakdown voltage) at a leak current of 1 × 10 ⁻⁵ A is shown.

Comparative Example 1 FIG. 2 shows that p-type Al _x Ga _1-x is provided between the substrate and the buffer layer.
A cross-sectional view of an FET epitaxial substrate (hereinafter referred to as B) having the same structure as that of Example 1 except that an As (x = 0.7) layer is not grown is shown. Similarly to the sample A, the buffer breakdown voltage of the sample B was examined. The sample processing was performed in the same process as in Example 1. Table 1 shows the voltage value (withstand voltage) at a leak current of 1 × 10 ⁻⁵ A.

[Table 1]

In Comparative Example 1, the leak current between the substrate and the buffer layer is large and the buffer withstand voltage is not sufficient, but in Example 1 of the present invention, the withstand voltage can be significantly improved.

[0020]

The FET epitaxial substrate of the present invention is a high-quality FET epitaxial substrate in which the influence of the interface between the substrate and the buffer layer is suppressed and the withstand voltage is high.

[Brief description of drawings]

FIG. 1 is a sectional view of an example (Example 1) of an FET epitaxial substrate of the present invention.

FIG. 2 is a cross-sectional view of one example (Comparative Example 1) of an FET epitaxial substrate having only a homobuffer layer.

[Explanation of symbols]

1 ... contact layer 2 ... electron supply layer 3 ... electron transit layer 4 ... buffer layer 5 ... p-type _{Al x Ga 1-x As (} 0 <x ≦ 1) 6 ... semi-insulating GaAs substrate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiko Hata 6 Kitahara, Tsukuba-shi, Ibaraki Sumitomo Chemical Co., Ltd.

Claims (3)

[Claims] 1. An organic metal and / or a hydride as a raw material
The substrate and the buffer were prepared by the pyrolysis vapor deposition method used.
Layer, the electron transit layer, and the contact layer are laminated in this order.
Epitaxial substrate for field effect transistor
The substrate is a semi-insulating GaAs substrate and the buffer is
The layer has a residual carrier concentration of 1 × 10 ¹⁶cm^-3Higher than
A resistor buffer layer, and the substrate and the buffer layer
Between 5 × 10¹¹cm^-2The following sheet acceptor concentrations
And depleted p-type Al _xGa_1-xAs (0 <x
≦ 1) field-effect transistor having a layer
Epitaxial substrate. 2. The epitaxial substrate for a field effect transistor according to claim 1, further comprising an electron supply layer between the electron transit layer and the contact layer. 3. A p-type Al _x Ga _{1 -x} As (0 <x ≦ 1)
2. The layer dopant is carbon.
Or the epitaxial substrate for a field effect transistor according to 2.