JP2009302191A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To fully enhance gain and efficiency and fully widen a band by not increasing parasitic capacitance, while keeping cost low, for example, when a high-frequency device is realized using a high resistance semiconductor substrate. <P>SOLUTION: A semiconductor device is provided with: a semiconductor substrate 1; and a compound semiconductor layer 2 which is formed on the semiconductor substrate 1. An impurity, which is not a dopant for the semiconductor substrate 1, exists in a region which includes an interface between the semiconductor substrate 1 and the compound semiconductor layer 2, and its proximity. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device suitable for use in, for example, a high electron mobility transistor (HEMT) using nitride.

In recent years, GaN-HEMTs have been actively developed in which an AlGaN layer or a GaN layer is grown on a substrate and the GaN layer is used as an electron transit layer.
Since GaN-HEMT has a band gap of GaN of 3.4 eV and larger than that of GaAs having a band gap of 1.4 eV, it is expected to operate at a high breakdown voltage.
For example, when a high breakdown voltage GaN-HEMT is used as an amplifier, it is possible to operate on a load line corresponding to a large load impedance on a graph showing current-voltage characteristics. As a result, highly efficient operation is possible.

For example, when a SiC substrate having a high thermal conductivity is used, a high mobility HEMT can be realized, and the thermal resistance of the device can be reduced even when mounted on a package.
JP 2006-165207 A Pradeeo Rajagopal et al., “MOCVD AlGaN / GaN HEMTs on Si: Challenges and Issues”, Material Research Society Symposium Proceedings, vol. 798, pp. 61-66 (2003).

By the way, when GaN-HEMT is used as a high frequency device, for example, a semi-insulating SiC substrate is used, but a semi-insulating SiC substrate (high resistance SiC substrate) is very expensive.
For this reason, it is conceivable to use, for example, a high resistance Si substrate as an alternative substrate.
However, when a high-resistance Si substrate is used, Ga may be mixed at the interface with the crystal layer grown on the Si substrate and in the vicinity thereof to have p-type conductivity.

This is because Ga diffuses from the GaN layer formed on the high-resistance Si substrate to the high-resistance Si substrate, or the Ga adhered to the growth apparatus in the previous crystal growth process is high-resistance Si substrate before crystal growth This is because it reattaches to the surface of the metal and diffuses into the high resistance Si substrate.
As described above, when Ga is mixed into the interface between the high-resistance Si substrate and the crystal layer and in the vicinity thereof and has p-type conductivity, it causes parasitic capacitance, resulting in a decrease in gain and a narrow band. As a result, the efficiency is lowered. The same applies when a high resistance InP substrate or a high resistance GaAs substrate is used.

Further, for example, a high resistance GaN substrate may be used as an alternative substrate.
However, if a high-resistance GaN substrate is used, Si present in the air adheres to the surface, which remains without being removed by the pretreatment for crystal growth, so that the high-resistance GaN substrate and the crystal layer grown thereon The interface with the (growth layer) and the vicinity thereof may have n-type conductivity.

Thus, when Si is mixed at the interface between the high-resistance GaN substrate and the crystal layer and in the vicinity thereof and has n-type conductivity, it causes parasitic capacitance, resulting in a decrease in gain and a narrow band. As a result, the efficiency is lowered. The same applies when a high-resistance sapphire substrate is used.
Therefore, for example, when a high-frequency device is realized using a high-resistance semiconductor substrate, it is desired that the parasitic capacitance is not increased while the cost is kept low, the gain and efficiency are sufficiently increased, and the bandwidth is sufficiently widened.

For this reason, this semiconductor device includes a semiconductor substrate and a compound semiconductor layer formed on the semiconductor substrate, and impurities that are not dopants to the semiconductor substrate are present at and near the interface between the semiconductor substrate and the compound semiconductor layer. It must be present in the containing area.
In this method of manufacturing a semiconductor device, at least one compound semiconductor layer is grown on a semiconductor substrate, and an impurity that is not a dopant is introduced into the semiconductor substrate so as to reach the inside of the semiconductor substrate from the surface side. It is a requirement to grow the remaining compound semiconductor layer on the semiconductor layer.

  Therefore, according to the present semiconductor device and its manufacturing method, for example, when a high-frequency device is realized using a high-resistance semiconductor substrate, the parasitic capacitance is not increased while the cost is kept low, and the gain and efficiency are sufficiently increased. There is an advantage that the bandwidth can be sufficiently widened.

Hereinafter, the semiconductor device and the manufacturing method thereof according to the present embodiment will be described with reference to the drawings.
[First Embodiment]
First, the semiconductor device and the manufacturing method thereof according to the first embodiment will be described with reference to FIGS.

The semiconductor device according to the present embodiment is a high-frequency device (electronic element for high-frequency applications) using a high-resistance semiconductor substrate.
Hereinafter, a case where the present invention is applied to a high electron mobility transistor (HEMT; GaN-HEMT; field effect semiconductor device using a compound semiconductor) using nitride will be described as an example. .

The GaN-HEMT includes a plurality of semiconductor crystal layers containing nitrogen (compound semiconductor layer; group III nitride layer; nitride layer containing Ga or Al here) on a high-resistance Si substrate (high-resistance semiconductor substrate); nitrogen The HEMT structure is formed by laminating a content layer.
Specifically, as shown in FIG. 1, the present GaN-HEMT has an AlN underlayer 2 (for example, a thickness of 0.1 μm) on a high-resistance Si substrate 1 made of (111) -plane single crystal Si (silicon). ), I-GaN buffer layer (non-doped buffer layer) 3, AlGaN / GaN superlattice layer 4, i-GaN electron transit layer 5, i-AlGaN layer (non-doped layer) 6, n-AlGaN electron supply layer 7, n- A GaN protective layer (cap layer) 8 has a semiconductor laminated structure in which these layers are laminated in this order. Here, the AlGaN / GaN superlattice layer 4, the i-GaN electron transit layer 5, the i-AlGaN layer 6, the n-AlGaN electron supply layer 7, and the n-GaN protective layer 8 constitute a GaN-HEMT structure.

  Here, the high resistance Si substrate 1 is a Si substrate having a resistivity of, for example, 100 Ω · cm or more. Note that the resistivity of the high-resistance Si substrate is at least 100 Ω · cm or more in the vicinity of the interface with the crystal layer (here, the AlN underlayer 2) formed thereon (for example, about 10 μm from the interface (surface)). It ’s fine. Thus, the cost can be kept low by using the Si substrate 1.

The non-doped buffer layer 3 is made of non-doped high-resistance GaN and has a thickness of 0.1 μm.
The electron transit layer 5 is made of non-doped high mobility GaN and has a thickness of 2 μm.
The non-doped layer 6 is made of non-doped Al _0.25 Ga _0.75 N and has a thickness of 5 nm.

The electron supply layer 7 is a compound semiconductor material having an electron affinity smaller than that of the electron transit layer 5, specifically, n-type Al _0.25 Ga _0.75 N doped with Si by 4 × 10 ¹⁸ cm ^−3. It is formed and its thickness is 10 nm.
As shown in FIG. 1, the source electrode 9 and the drain electrode 10 are provided apart from each other on a partial region of the electron supply layer 7.

The source electrode 9 and the drain electrode 10 have a layer structure composed of a Ta layer in contact with the electron supply layer 7 and an Al layer disposed thereon, and are ohmicly connected to the electron supply layer 7. Here, a TaAl ₃ layer is formed by mutual diffusion at the interface between the Ta layer and the Al layer.
The surface of the electron supply layer 7 between the source electrode 9 and the drain electrode 10 is covered with a protective layer 8.

The protective layer 8 is made of n-type GaN doped with Si by 5 × 10 ¹⁸ cm ⁻³ and has a thickness of 7 nm.
Further, as shown in FIG. 1, a gate electrode 11 is provided on a partial region of the protective layer 8 so as to be separated from both the source electrode 9 and the drain electrode 10.
The gate electrode 11 has a two-layer structure of a Ni layer in contact with the protective layer 8 and an Au layer disposed thereon. Here, the gate length is 0.5 μm and the unit gate width is 300 μm. The unit gate width is a gate width per one, and is a width of a region in which the concentration of two-dimensional electron gas (2DEG) is controlled by the gate electrode 11.

The gate length and unit gate width are not limited to this.
For example, when used as a high efficiency amplifier, the gate length is preferably in the range of 0.3 μm to 0.7 μm, and more preferably in the range of 0.5 μm to 0.6 μm. When the gate length is increased, the gain is lowered and the distortion characteristics are also deteriorated. When the gate length is shorter than 0.3 μm, the withstand voltage is lowered to, for example, 200 V or less, the efficiency is lowered due to the deterioration of the pinch-off characteristic, and the reliability of the element is lowered. The unit gate width is preferably in the range of 200 μm to 350 μm, and more preferably in the range of 250 μm to 300 μm. Increasing the unit gate width decreases the gain of the Doherty amplifier, and decreasing the unit gate width decreases the maximum output that can be extracted.

In addition, as shown in FIG. 1, the surface of the protective layer 8 between the gate electrode 11 and the source electrode 9 and the surface of the protective layer 8 between the gate electrode 11 and the drain electrode 10 are insulated films (here Then, it is covered with a SiN film) 12.
By the way, when the high resistance Si substrate 1 is used, Ga is mixed into the interface between the high resistance Si substrate 1 and a crystal layer (AlN underlayer 2 in this case) grown thereon and in the vicinity thereof, and has p-type conductivity. Become electrically activated. That is, the resistivity is, for example, 100 Ω · cm or more even though it has a Ga mixed layer, that is, a dopant (Ga) at and near the interface between the high-resistance Si substrate 1 and the crystal layer (here, the AlN underlayer 2). A layer having a high resistance is formed. This causes parasitic capacitance.

Therefore, in this embodiment, as shown in FIG. 1, Ar is introduced into the high-resistance Si substrate 1, the AlN underlayer 2, and the i-GaN buffer layer 3 by ion implantation. As a result, the region including the p-type conductive portion at the interface between the high resistance Si substrate 1 and the crystal layer (here, the AlN underlayer 2) and in the vicinity thereof (the surface of the high resistance Si substrate 1 and the vicinity thereof) is excluded. It is activated.
Here, impurities that do not become dopants to the semiconductor substrate 1 are introduced into the high-resistance Si substrate 1, the AlN underlayer 2 and the i-GaN buffer layer 3, but the present invention is not limited to this. . For example, impurities that are not dopants to the semiconductor substrate 1 may be introduced into the high resistance Si substrate 1 and the AlN underlayer 2.

Thus, in the present embodiment, Ar exists in the region including the interface between the high resistance Si substrate 1 and the crystal layer (here, the AlN underlayer 2) and the vicinity thereof. Note that a region where Ar is implanted is referred to as an inactive region.
In this embodiment, Ar is ion-implanted, but the present invention is not limited to this.
For example, an impurity that does not become a dopant with respect to the semiconductor substrate may be introduced into a region including the interface between the semiconductor substrate and the crystal layer and the vicinity thereof.

  Specifically, at least one of Ar, O, H, He, and B may be introduced as an impurity that does not become a dopant for the high-resistance Si substrate 1. For example, only one of them may be introduced, or two or more may be introduced. Further, the implantation energy at the time of ion implantation may be changed stepwise. The inactive region can be deepened by these methods.

Further, for example, impurities may be introduced by a method such as thermal diffusion or electron beam irradiation.
In this way, impurities (Ar here) that do not become dopants to the high resistance Si substrate 1 are introduced into the region including the interface between the high resistance Si substrate 1 and the crystal layer (here, the AlN underlayer 2) and the vicinity thereof. By doing so, it is possible to prevent the parasitic capacitance, particularly the output capacitance, from increasing. That is, it is possible to keep the high resistance of the high resistance Si substrate 1 and to have no parasitic capacitance component.

Next, a method for manufacturing the semiconductor device (GaN-HEMT) according to the present embodiment will be described with reference to FIG.
First, as shown in FIG. 2A, an AlN underlayer 2 and an i-GaN buffer layer 3 are formed on a high-resistance Si substrate 1 (here, a single crystal Si substrate) by, for example, metal organic vapor phase epitaxy (MOVPE). Growing in order according to the law (first growth). For example, trimethylaluminum may be used as the Al material, trimethylgallium as the Ga material, and ammonia as the N material.

  Here, once taken out from the growth apparatus, as shown in FIG. 2B, impurities that do not become dopants to the high resistance Si substrate 1 are introduced into the high resistance Si substrate 1 from the surface side [at least the high resistance Si substrate. 1 and a region including the vicinity of the interface between the crystal layer 1 and the crystal layer (the AlN underlayer 2 in this case). Here, the ion implantation species is Ar, and the energy is 100 keV.

  In the present embodiment, after the i-GaN buffer layer 3 is grown, the i-GaN buffer layer 3 is taken out from the growth apparatus and impurities that do not become dopants are introduced into the semiconductor substrate. However, the present invention is not limited to this. For example, after the AlN underlayer 2 is grown and before the i-GaN buffer layer 3 is grown, it may be taken out from the growth apparatus and an impurity that does not become a dopant may be introduced into the semiconductor substrate. That is, before introducing an impurity that does not become a dopant into a semiconductor substrate, at least one crystal layer is grown on the semiconductor substrate, and after introducing an impurity that does not become a dopant into the semiconductor substrate, The remaining crystal layer (here, a GaN-HEMT structure, or an i-GaN buffer layer and a GaN-HEMT structure) may be grown.

Here, FIG. 3 shows the relationship between the implantation amount and the distance from the implantation surface when ArN is implanted from the surface of the AlN foundation layer 2 after the AlN foundation layer 2 is grown on the high resistance Si substrate 1. FIG.
As shown in FIG. 3, the peak of the amount of Ar ion-implanted is at the interface between the high-resistance Si substrate 1 and the AlN underlayer 2 and is about 3 × 10 ²⁰ cm ⁻³ . Ar is also implanted into the high resistance Si substrate 1 to a depth of 300 nm from the implantation surface. That is, the profile of the Ar implantation amount is a profile in which the tail is drawn to a depth of 300 nm from the implantation surface (200 nm from the substrate surface). Note that the region into which Ar is implanted in this way becomes an inactive region.

By injecting impurities (Ar here), activation of the interface between the high resistance Si substrate 1 and the crystal layer (AlN underlayer 2 here) and the vicinity thereof can be prevented. Thus, the parasitic capacitance does not increase even after the HEMT (transistor) is manufactured.
After that, returning to the growth apparatus again, as shown in FIG. 2C, on the i-GaN buffer layer 3, an AlGaN / GaN superlattice layer 4, an i-GaN electron transit layer 5, an i-AlGaN layer 6, The n-AlGaN electron supply layer 7 and the n-GaN protective layer 8 are sequentially grown by, for example, a metal organic vapor phase epitaxy (MOVPE) method (second growth). For example, trimethylaluminum may be used as the Al material, trimethylgallium as the Ga material, and ammonia as the N material. Further, for example, silane may be used as the Si dopant raw material.

Next, although not shown, after forming a resist film on the n-GaN protective layer 8, an element isolation pattern is formed, and element isolation is performed by ion implantation of nitrogen, for example. Thereafter, the resist film is removed.
Next, as illustrated in FIG. 2D, the source electrode 9 and the drain electrode 10 are formed on the n-AlGaN electron supply layer 7.

That is, first, a new resist film is formed on the n-GaN protective layer 8, and exposure and development are performed to form openings in regions where the source electrode 9 and the drain electrode 10 are to be formed.
Next, a Ta film having a thickness of 10 nm and an Al film having a thickness of 280 nm, for example, are sequentially deposited on the entire surface by, for example, vapor deposition.
Next, by removing the resist film, the Ta film and the Al film in a region other than the region where the source electrode 9 and the drain electrode 10 are formed are removed.

Subsequently, for example, heat treatment is performed at 550 ° C. for 1 minute under a nitrogen atmosphere using a rapid thermal annealing (RTA) apparatus. By this heat treatment, a TaAl ₃ film is formed at the interface between the Ta film and the Al film.
In this way, the source electrode 9 and the drain electrode 10 are formed on the n-AlGaN electron supply layer 7.

Next, as shown in FIG. 2D, a SiN film (insulating film) 12 is formed on the entire surface by, for example, plasma enhanced chemical vapor deposition (PE-CVD).
Next, as illustrated in FIG. 2D, the gate electrode 11 is formed on the n-GaN protective layer 8.
That is, first, a new resist film is formed on the SiN film 12, and exposure and development are performed to form an opening in a region where the gate electrode 11 is to be formed.

Next, a 10 nm thick Ni film, for example, a 200 nm thick Au film, for example, is sequentially deposited on the entire surface by, for example, vapor deposition.
Next, the resist film is peeled off together with the Ni film and Au film deposited thereon.
Thus, the gate electrode 11 having a two-layer structure of the Ni film and the Au film is formed on the n-GaN protective layer 8.

Thereafter, although not shown, after an SiN film (insulating film) is formed on the entire surface, openings are formed in regions corresponding to the source electrode 9, the drain electrode 10, and the gate electrode 11, and the source electrode 9, the drain electrode 10, and the gate are formed. The upper surface of the electrode 11 is exposed.
Therefore, according to the semiconductor device (GaN-HEMT) and the manufacturing method thereof according to the present embodiment, for example, when realizing a high frequency device using a high resistance semiconductor substrate, the parasitic capacitance does not increase while keeping the cost low. Thus, there are advantages that the gain and efficiency can be sufficiently increased and the bandwidth can be sufficiently widened.

Here, FIG. 4 shows gain (dB), efficiency (%), output (W / mm), band (MHz), output capacitance (fF) in the GaN-HEMT fabricated on the Si substrate 1 as described above. / Mm) in comparison with those using a Si substrate but not ion-implanted, and using a SiC (silicon carbide) substrate.
As shown in FIG. 4, when the Si substrate 1 is used but the ion implantation is not performed, the gain is low and the efficiency and the output are reduced. It can be seen that with the implantation, all of gain, efficiency, and output are improved, and characteristics equivalent to those using the SiC substrate can be obtained. This is because the parasitic capacitance, particularly the output capacitance, has decreased as shown in FIG. In addition, it is possible to achieve wide matching of gain bands due to a decrease in output capacitance. In contrast to the case where the Si substrate 1 is used but the ion implantation is not performed, the case where the ion implantation is performed using the Si substrate 1, as shown in FIG. 4, has a band in which the gain is within a range of ± 0.2 dB. You can see that it is spreading.

In the above-described embodiment, the high-resistance Si substrate 1 is used and Ar is introduced as an impurity that does not become a dopant to the Si substrate 1, but the present invention is not limited to this. For example, a high-resistance InP substrate or a high-resistance GaAs substrate is used as the high-resistance semiconductor substrate, and a crystal layer (including a HEMT structure including a GaN layer) similar to that in the above-described embodiment is formed thereon, At least one of Ar, O, H, He, and B may be introduced as an impurity that does not become a dopant.
[Second Embodiment]
Next, a semiconductor device and a manufacturing method thereof according to the second embodiment will be described with reference to FIG.

The semiconductor device (GaN-HEMT) and the manufacturing method thereof according to the present embodiment are different from those of the first embodiment described above in that a high-resistance Si substrate is used, whereas a high-resistance GaN substrate is used. .
That is, as shown in FIG. 5, the present GaN-HEMT has a plurality of semiconductor crystal layers containing nitrogen (compound semiconductor layer; group III nitride layer; on a high resistance GaN substrate (high resistance semiconductor substrate)) 1A. A HEMT structure in which a nitride layer containing Ga or Al; a nitrogen-containing layer) is stacked is provided.

  Specifically, as shown in FIG. 5, the present GaN-HEMT is formed on a high resistance GaN substrate 1A made of single crystal GaN (gallium nitride), an AlN underlayer 2 (for example, thickness 0.1 μm), i− GaN buffer layer (non-doped buffer layer) 3, AlGaN / GaN superlattice layer 4, i-GaN electron transit layer 5, i-AlGaN layer (non-doped layer) 6, n-AlGaN electron supply layer 7, n-GaN protective layer ( (Cap layer) 8 has a semiconductor laminated structure in which the layers are laminated in this order. In FIG. 5, the same components as those in the first embodiment described above (see FIG. 1) are denoted by the same reference numerals.

  Here, the high-resistance GaN substrate 1A is a GaN substrate having a resistivity of, for example, 100 Ω · cm or more. The high-resistance GaN substrate 1A has at least a resistivity of 100 Ω · cm or more in the vicinity of the interface (for example, about 10 μm from the interface (surface)) with the crystal layer (here, the AlN underlayer) formed thereon. It ’s fine. Thus, the cost can be kept low by using the GaN substrate 1A.

  By the way, when the high-resistance GaN substrate 1A is used, Si (residual Si) is mixed at the interface between the high-resistance GaN substrate 1A and a crystal layer (here, the AlN underlayer 2) grown on the high-resistance GaN substrate 1A, and in the vicinity thereof. It will have conductivity. That is, the resistivity of the layer containing Si (Si-GaN layer), that is, the dopant (Si), at the interface between the high resistance GaN substrate 1A and the crystal layer (here, the AlN underlayer 2) and in the vicinity thereof. However, a layer having a high resistance of, for example, 100 Ω · cm or more is formed. This causes parasitic capacitance.

  Therefore, in this embodiment, as shown in FIG. 5, Ar is introduced into the high resistance GaN substrate 1A, the AlN underlayer 2, and the i-GaN buffer layer 3 by ion implantation. As a result, the region including the n-type conductive portion at the interface between the high resistance GaN substrate 1A and the crystal layer (here, the AlN underlayer 2) and in the vicinity thereof (the surface of the high resistance GaN substrate 1A and the vicinity thereof) is excluded. It is activated.

Here, impurities that are not dopants to the semiconductor substrate 1A are introduced into the high-resistance GaN substrate 1A, the AlN underlayer 2 and the i-GaN buffer layer 3, but this is not restrictive. . For example, impurities that do not become dopants to the semiconductor substrate 1A may be introduced into the high-resistance GaN substrate 1A and the AlN underlayer 2.
Thus, in the present embodiment, Ar exists in the region including the interface between the high resistance GaN substrate 1A and the crystal layer (here, the AlN underlayer 2) and the vicinity thereof. Note that a region where Ar is implanted is referred to as an inactive region.

In this embodiment, Ar is ion-implanted, but the present invention is not limited to this.
For example, an impurity that does not become a dopant with respect to the semiconductor substrate may be introduced into a region including the interface between the semiconductor substrate and the crystal layer and the vicinity thereof.
Specifically, at least one of Ar, N, O, H, P, He, and B may be introduced as an impurity that does not become a dopant for the semiconductor substrate. For example, only one of them may be introduced, or two or more may be introduced. Further, the implantation energy at the time of ion implantation may be changed stepwise. The inactive region can be deepened by these methods.

Further, for example, impurities may be introduced by a method such as thermal diffusion or electron beam irradiation.
As described above, an impurity (here, Ar) that does not serve as a dopant to the high resistance GaN substrate 1A is introduced into the region including the interface between the high resistance GaN substrate 1A and the crystal layer (here, the AlN underlayer 2) and the vicinity thereof. By doing so, the parasitic capacitance can be prevented from increasing. That is, it is possible to prevent the parasitic capacitance component from being maintained while maintaining the high resistance of the high-resistance GaN substrate 1A.

Other details of the configuration are the same as those of the first embodiment described above, and thus the description thereof is omitted here.
Next, a method for manufacturing the semiconductor device (GaN-HEMT) according to the present embodiment will be described.
First, as in the case of the first embodiment described above (see FIG. 2A), the AlN underlayer 2 and the i-GaN buffer layer 3 are formed on the high-resistance GaN substrate 1A by, for example, metal organic vapor phase epitaxy ( MOVPE) method is used for sequential growth (first growth).

Next, in the same manner as in the case of the first embodiment described above (see FIG. 2B), impurities that do not become dopants with respect to the high-resistance GaN substrate 1A are once extracted from the growth apparatus. Ions are implanted so as to reach the inside of the substrate 1A [at least the region including the interface between the high-resistance GaN substrate 1A and the crystal layer (here, the AlN underlayer 2) and its vicinity).
By injecting impurities (here Ar) in this way, activation of the interface between the high resistance GaN substrate 1A and the crystal layer (here AlN underlayer 2) and the vicinity thereof can be prevented. Thus, the parasitic capacitance does not increase even after the HEMT (transistor) is manufactured.

Thereafter, in the same manner as in the case of the first embodiment described above (see FIG. 2C), it is returned to the growth apparatus again, and the AlGaN / GaN superlattice layer 4 and i-GaN electrons are formed on the i-GaN buffer layer 3. The traveling layer 5, the i-AlGaN layer 6, the n-AlGaN electron supply layer 7, and the n-GaN protective layer 8 are sequentially grown by, for example, a metal organic vapor phase epitaxy (MOVPE) method (second growth).
The details of the other manufacturing methods are the same as those of the first embodiment described above, and the description thereof is omitted here.

Therefore, according to the semiconductor device (GaN-HEMT) and the manufacturing method thereof according to the present embodiment, for example, when realizing a high frequency device using a high resistance semiconductor substrate, the parasitic capacitance does not increase while keeping the cost low. Thus, there are advantages that the gain and efficiency can be sufficiently increased and the bandwidth can be sufficiently widened.
In the above-described embodiment, the high-resistance GaN substrate 1A is used, and Ar is introduced as an impurity that does not become a dopant to the GaN substrate 1A. However, the present invention is not limited to this. For example, a high-resistance sapphire substrate is used as a high-resistance semiconductor substrate, and a crystal layer (including a HEMT structure including a GaN layer) similar to that in the above-described embodiment is formed thereon, and impurities that do not serve as dopants to the semiconductor substrate As described above, at least one of Ar, N, O, H, P, He, and B may be introduced.
[Others]
The present invention is not limited to the configurations described in the above-described embodiments and modifications thereof, and various modifications, improvements, combinations, and the like are possible without departing from the spirit of the present invention.

For example, the crystal layer (compound semiconductor layer; semiconductor stacked structure; HEMT structure) formed on the semiconductor substrate is not limited to those of the above-described embodiments.
For example, as shown in FIG. 6, an AlN underlayer 2, an i-GaN electron transit layer 5, an n-AlGaN electron supply layer 7, and an n-GaN protective layer 8 are sequentially laminated on the high resistance semiconductor substrate 1 (1 </ b> A). It is also possible to provide a semiconductor laminated structure. In FIG. 6, the same components as those in the above-described embodiments (see FIGS. 1 and 5) are denoted by the same reference numerals. For example, the electron supply layer may be formed of AlGaInN instead of AlGaN. Further, for example, the HEMT threshold value can be changed by adjusting the band gap of the electron supply layer by controlling the In composition ratio. Further, for example, each layer such as an electron transit layer and an electron supply layer may be formed of other compound semiconductor materials (for example, AlInN, InN, InGaN, etc.).

  Further, for example, in each of the above-described embodiments, the HEMT (high frequency device) using a high-resistance semiconductor substrate is described as an example. However, the present invention is not limited to this, and the present invention uses a semiconductor substrate. It can be widely applied to semiconductor devices.

It is a typical sectional view showing the composition of the semiconductor device (GaN-HEMT) concerning a 1st embodiment of the present invention. (A)-(D) are typical sectional drawings for demonstrating the manufacturing method of the semiconductor device (GaN-HEMT) concerning 1st Embodiment of this invention. It is a figure which shows the relationship between Ar injection amount and the distance from the injection | pouring surface in the semiconductor device (GaN-HEMT) concerning 1st Embodiment of this invention. It is a figure for demonstrating the effect of the semiconductor device (GaN-HEMT) concerning 1st Embodiment of this invention. It is typical sectional drawing which shows the structure of the semiconductor device (GaN-HEMT) concerning 2nd Embodiment of this invention. It is typical sectional drawing which shows the structure of the modification of the semiconductor device (GaN-HEMT) concerning each embodiment of this invention.

Explanation of symbols

1 High resistance Si substrate 1A High resistance GaN substrate 2 AlN underlayer 3 i-GaN buffer layer (non-doped buffer layer)
4 AlGaN / GaN superlattice layer 5 i-GaN electron transit layer 6 i-AlGaN layer (non-doped layer)
7 n-AlGaN electron supply layer 8 n-GaN protective layer 9 source electrode 10 drain electrode 11 gate electrode 12 insulating film (SiN film)

Claims (6)

A semiconductor substrate;
A compound semiconductor layer formed on the semiconductor substrate,
The semiconductor device characterized in that an impurity which does not become a dopant with respect to the semiconductor substrate is present in a region including an interface between the semiconductor substrate and the compound semiconductor layer and the vicinity thereof.   2. The semiconductor device according to claim 1, wherein the impurity which does not become a dopant with respect to the semiconductor substrate is at least one of Ar, N, O, H, P, He, and B.   3. The semiconductor device according to claim 1, wherein the compound semiconductor layer is a nitride layer containing Ga or Al.   The semiconductor device according to claim 1, wherein the semiconductor substrate is a high-resistance Si substrate.   The semiconductor device according to claim 1, wherein the semiconductor substrate is a high-resistance GaN substrate. Growing at least one compound semiconductor layer on the semiconductor substrate;
Impurities that do not become dopants to the semiconductor substrate are introduced so as to reach the inside of the semiconductor substrate from the surface side,
A method of manufacturing a semiconductor device, comprising growing a remaining crystal layer on the compound semiconductor layer.

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