JPH09331023A - Semiconductor integrated circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of interference noise effectively by interrupting the potential fluctuation due to asynchronous operation between circuit blocks operating asynchronously. SOLUTION: In the semiconductor integrated circuit 24, welts W1 -W4 are isolated among circuit blocks M1 -M4 operating asynchronously and power supply lines 28, 30 are wires while being isolated electrically from signal lines 32, 34 and connected, respectively, with the circuit blocks M1 -M4 . Consequently, potential fluctuation is not transmitted between the circuit blocks thus preventing erroneous operation due to interference noise and lowering of operational speed. Furthermore, a semiconductor device 20 incorporating the semiconductor integrated circuit 24 is provided, on the outer circumferential surface, with terminals VDD1 -VDD4 , Vss1-Vss4, Vin1-Vin4 and Vout1-Vout4 internally connected with any one of the power supply lines 28, 30 or the signal lines 32, 34 while keeping the electrically isolated state of each circuit block M1 -M4 .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit called a so-called chip and a semiconductor device after packaging the same. In particular, the present invention relates to a technique for preventing interference noise that is transmitted between circuit blocks that operate asynchronously in the same chip via a power supply line or the like.

[0002]

2. Description of the Related Art Generally, a semiconductor integrated circuit in which electronic circuits are integrated on the same substrate is viewed as an electronic circuit, depending on its function unit or whether or not the same function operates in synchronization. It can be said that it is composed of several divided circuit blocks. Here, “operate in synchronization” means that each circuit block operates in association with another circuit block in terms of time, and “operates asynchronously” means that they operate in relation to each other in terms of time. It means to operate independently. For example, in the case of DRAM, memory cell array, various decoders, input / output circuits, power supply circuits, etc.
It is composed of a plurality of circuit blocks each having a different function. Of these, the memory cell array is composed of a plurality of memory blocks divided in a predetermined unit such as word line sector, and data is written and read in this unit. Then, it can be said that it is composed of several finer circuit blocks.

Power supply lines such as a power supply voltage supply line and a reference voltage supply line are connected to these circuit blocks. An input signal line and an output signal line are connected to each circuit block.

On the other hand, from a structural perspective of this semiconductor integrated circuit, various wells are formed by introducing n-type or p-type impurities into the semiconductor substrate surface side, and each circuit block is
The well is composed of a group of elements formed on the surface side of the semiconductor substrate.

[0005]

In this conventional semiconductor integrated circuit, for example, taking a DRAM as an example, data writing and reading of each memory block are sequentially performed for each memory block, and data erasing is performed for a part of the memory block or Most of the time, it was all done at the same time. Therefore, if the power supply line is shared, the potential fluctuation is transmitted to the circuit blocks. However, as long as the circuit blocks are synchronously operated, even if the potential of the power supply line fluctuates to some extent, it does not hinder the normal operation of the circuit block, and this potential fluctuation is considered a problem. Didn't.

On the other hand, as the operating speed has been shortened in recent years, there is an increasing number of cases where data is asynchronously written and read in different memory blocks. For example, a plurality of memory blocks on one side may start charging / discharging bit lines in synchronization with each other, and a little later than this, the other memory block may raise a word line to read data stored in that memory cell. . In addition, one memory block and the other memory block start charging / discharging the bit lines substantially at the same time, but there is a case where data writing is performed on one side and data reading is performed on the other side.

In these cases, when the potential fluctuation of the power supply line is transmitted from one circuit block to the other circuit block that operates asynchronously, it becomes interference noise and malfunction or operating speed of the other circuit block. A new problem has arisen that the risk of a decrease in

For example, in the former case, the voltage line of the power supply line drops due to the charging / discharging of the bit line of one memory block, and the word line of the other memory block reaches a desired potential within a predetermined time. It could take some time to do. In the latter case, the data read time through the bit line of the other memory block becomes longer due to the potential drop of the power supply voltage supply line due to the charging / discharging of the bit line of one memory block and the increase in the potential of the reference voltage supply. There was an occasion. The delay in these sensing operations is
How to suppress the potential fluctuations that cause this interference noise, as it interferes with high-speed operation and causes malfunctions,
Alternatively, how to reduce the influence has become an important issue for preventing malfunction of the device and maintaining high-speed performance.

The present invention has been made in view of the above situation, and provides a semiconductor integrated circuit and a semiconductor device in which potential fluctuations are cut off between circuit blocks that operate asynchronously, thereby effectively preventing the occurrence of interference noise. The purpose is to provide.

[0010]

In order to solve the above-mentioned problems of the prior art and to achieve the above object, the present invention
As a result of diligent study on interference noise in DRAM, the interference noise between memory blocks operating asynchronously is mainly transmitted as fluctuations of a power supply voltage supply line or a reference voltage supply line, and a transistor via a well of a semiconductor substrate. Some change the threshold voltage of
I got the knowledge.

Based on this knowledge, in the semiconductor integrated circuit of the present invention, the wells are divided between the blocks operating asynchronously, and the power supply lines and the signal lines are electrically separated and connected. . That is, the semiconductor integrated circuit of the present invention has at least 2 layers formed on the surface of the semiconductor substrate.
At least two circuit blocks each including one well and an element group including a transistor formed on the surface side of each well and operating independently of each other (for example, a memory cell array of a semiconductor memory is configured. Memory block), and circuit blocks that operate asynchronously with each other are electrically separated and wired on a semiconductor substrate, and have a power supply line and a signal line connected to each circuit block.

Conventionally, well formation has been mainly determined by the type of transistor and process restrictions.
Further, also in the related art, when it is necessary to supply a plurality of types of power source voltages, the power source lines are electrically separated. On the other hand, according to the present invention, in addition to the power supply line,
Wells and signal lines are separated from each other. Therefore, the potential fluctuations via them are not mutually transmitted between the circuit blocks that operate asynchronously, which prevents malfunction due to interference noise. Also, the interference noise does not hinder the charging / discharging of the bit line or the like, which extends the time and hinders the high speed operation.

On the other hand, the semiconductor device of the present invention has the above-mentioned semiconductor integrated circuit of the present invention built-in, and either the power supply line or the signal line is maintained while the electrically separated state of each circuit block operating asynchronously is maintained. Has a plurality of terminals internally connected to the outer peripheral surface.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION As described above, according to the present invention, wells are divided between blocks that operate asynchronously, and power lines and signal lines are electrically separated and connected. Prior to a detailed description of the present embodiment, first, the inventors of the present invention briefly describe the simulation result of the defective operation, which is the basis for forming the present invention as described above, together with the drawings.

FIG. 5 shows a model of this operation simulation. In this semiconductor device 2, a semiconductor chip 6 is mounted in a package 4. The package 4 is provided with two terminals 4a and 4b. In the semiconductor chip 6, a well 8 is formed on the surface of a semiconductor substrate, and the well 8 has a first memory block M1 and a second memory block M2. Further, a common power supply voltage supply line 10 and a common reference voltage supply line 12 are laid on the surface of the semiconductor substrate, and both memory blocks M1 and M2 are connected via these power supply lines 10 and 12. The power supply voltage supply line 10 and the reference voltage supply line 12 are provided with pads in the middle thereof, and the pads are provided on the terminals 4a and 4 of the package 4, respectively.
Wire-bonded to b.

FIGS. 6 and 7 show the results of operation simulation using the model thus constructed. In FIG. 6, when the first memory block M1 starts charging / discharging the bit line and tries to write or erase the data of the first memory block M1, the second memory block M2 is slightly delayed. This is a case where the word line is activated to read the data stored in the memory cell. In the initial state, as shown in FIG. 6, the bit line is held at the level of half the power supply voltage Vcc (not shown). Further, as shown in the figure, the power supply lines 10 and 12 for charging / discharging the bit lines and driving the sense amplifier are maintained at the constant power supply voltage VDD and the reference voltage Vss.

From this initial state, for example, when the first memory block M1 charges the bit line and writes the data of the memory cell, as shown in FIG. 4A, first, the word line is boosted by the booster circuit. Voltage Vw higher than power supply voltage VDD due to
Then, the bit line is Vcc / by the power supply voltage VDD.
Charge from 2 to VH (BIT) and write data to the memory cell. On the contrary, when erasing data, the bit line should be Vcc / 2.
To VL (BIT) to erase the data.

Along with the charging / discharging of the bit line, potential fluctuations of the power supply voltage VDD and the reference voltage Vss occur. That is, as shown in the figure, the potential of the power supply voltage VDD decreases and the potential of the reference voltage Vss increases as the bit line starts charging and discharging. Then, when the charging / discharging ends, the potential is returned to the original potential.

When the second memory block M2 tries to raise the word line for data reading during the potential fluctuation of the power supply voltage VDD and the reference voltage Vss,
Since the rise of the word line is performed by boosting the power supply voltage VDD, it is interlocked with the power supply voltage VDD, and as shown in FIG.
The rise of the word line is delayed until the power supply voltage VDD returns after the fluctuation. As a result, the output of the sense amplifier of the second memory block M2 is VH (SENSE) or VL (SENS
The timing to become E) is delayed. In the operation simulation, the sensing of the second memory block M2 is simply delayed, but in the actual operation, the data read time is limited within a predetermined time after starting the activation of the word line and the data read time. Then, as a result of the determination that the reading operation is completed during the sensing, this sensing delay may cause a malfunction.

FIG. 7 shows the first memory block M1 and the second memory block M1.
Memory block M2 of the other memory cell rises the word line almost at the same time, and one first memory block M1 starts charging / discharging the bit line to write or erase the data of the memory cell. Second memory block M2
Then, it is the case of reading data.

In the case of FIG. 7, since the word lines are activated almost at the same time, the second memory block M2 as shown in FIG.
There is no delay in the startup of the word line on the side. However, as the bit line is charged / discharged in the first memory block M1, the power supply voltage VDD is changed as in the case of FIG.
And the potential fluctuation of the reference voltage Vss occurs. For this reason,
The sense amplifier of the second memory block M2 cannot perform the sensing smoothly until the potentials of the power supply voltage VDD and the reference voltage Vss are restored, and it takes time to read the data as shown in the figure. The sensing delay in this case also causes a malfunction due to the same reason as above, or impedes the high-speed operation of the semiconductor memory in the case of waiting for the end of sensing and proceeding to the next operation.

The potential fluctuations of the power supply voltage VDD and the reference voltage Vss generated based on the operation of one of the memory blocks cause interference noise to prevent the normal operation of the other memory block. It is because it is working. That is, for example, in the case of FIG. 7, when both memory blocks M1 and M2 are synchronously writing or erasing data, or when both memory blocks are both reading data, If the number of cells is large, some sensing delay may occur, but no operation abnormality causing a malfunction as shown in FIGS. 6 and 7 is found.
In the present invention, "operate in synchronization" means that each circuit block such as a memory block operates while being temporally associated with another circuit block, and "operates asynchronously" means It means that these operate independently of each other in terms of time.

Next, a semiconductor integrated circuit and a semiconductor device according to the present invention devised based on the result of the above-mentioned operation simulation will be described in detail with reference to the drawings. First Embodiment FIG. 1 is a top view showing a schematic configuration of the inside of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a schematic sectional view of a semiconductor integrated circuit taken along line II-II of FIG. is there. As shown in FIG. 1, the semiconductor device 20 includes a package 22 and a semiconductor integrated circuit (semiconductor chip 24) mounted on a lead frame or the like in the package 22.

In the semiconductor chip 24 of the present invention, four n-type wells W1, W2, W3 and W4 are separately formed on the surface of a p-type semiconductor substrate 26 as shown in FIG. There is. Wells W1, W2, W3, W4
On the front side of the circuit block M, which operates asynchronously with each other.
1, M2, M3 and M4 are formed. Each of the circuit blocks M1, M2, M3 and M4 is composed of an element group including a transistor. In the following description, each of the circuit blocks M1, M2, M3 and M4 is assumed to be a memory block formed by dividing the memory cell array of the semiconductor memory into several memory cell aggregates.

For example, in the case of DRAM, each memory cell includes a memory capacitor on a semiconductor substrate and a transfer MO.
It is composed of an S transistor. Each circuit block M1, M2, M3, M4 is composed of, for example, a plurality of memory cells for each word line sector as a unit to which the same excitation voltage is applied at one time when writing data to or reading data from the DRAM. . Each circuit block M1, M2, M
Sense amplifiers are included in 3 and M4, respectively. Further, peripheral circuits of the memory cell array, such as various decoders, input / output circuits, and power supply circuits are not shown.

In the semiconductor chip 24 of the present invention, as shown in FIG. 1, four power supply voltage supply lines 28, a reference voltage supply line 30, an input signal line 32, and an output signal line 34 are electrically separated from each other. Circuit blocks M1, M2, M3, M4 while maintaining this electrically separated state.
It is connected to the.

In the package 22 of the present invention, the number of circuit blocks in which the external terminals of the same type operate asynchronously in the semiconductor chip 24 (four in FIG. 1).
They are provided one by one. That is, the semiconductor device 2 on the illustrated side
0 has power supply voltage supply lines VDD1 to VDD4, reference voltage supply lines VSS1 to VSS4, input signal lines Vin1 to Vin4, output signal lines Vout1 to Vout4, and four external terminals each. Then, to each of these external terminals, the above-mentioned four power supply voltage supply lines 28, reference voltage supply lines 30,
Either the input signal line 32 or the output signal line 34 is connected by wire bonding while maintaining its electrically separated state.

As described above, the semiconductor integrated circuit 24 of the present invention
In this case, the respective circuit blocks M1, M2, M3, M4 that are asynchronous with each other and are formed in separate wells W1, W2, W3, W4. Therefore, even if the potential of the well W1 changes, for example, the threshold voltage of the transistor does not change in other wells.

Further, in the semiconductor device 20 of the present invention, in the semiconductor integrated circuit 24, the power supply lines 28, 30 and the signal lines 32, 34 are electrically separated from each other and wired, and the electrically separated state is set. It is connected to the external terminal while maintaining it. Therefore, each circuit block M1, M2, M3,
Even if the M4s operate asynchronously with each other and the potential fluctuations are generated thereby, the potential fluctuations are not input to other circuit blocks, and therefore, the occurrence of interference noise, which has been a problem in the past, is prevented.

Second Embodiment This embodiment is a case in which a power supply voltage supply line for substrate bias and an external terminal are further added to each circuit block in addition to the above-described first embodiment. FIG. 3 shows a second embodiment of the present invention.
FIG. 4 is a top view showing a schematic configuration of the inside of the semiconductor device according to the embodiment, and FIG. 4 is a schematic cross-sectional view of the semiconductor integrated circuit taken along the line III-III in FIG. As shown by the diagonal lines in FIG. 3, the semiconductor device 20 has wells W1, W2, W3.
, W4 are directly connected to the surface of the well W4 and electrically isolated from each other. Also, four external terminals VBB
1 to VBB4 are provided in a form added in the case of the first embodiment, and the respective power supply voltage supply lines 36 are connected to the external terminals VBB1 to VBB4 by wire bonding.

Correspondingly, in order to improve the electrical connection of each power supply voltage supply line 36 on the surface of each well of the semiconductor chip 24, an impurity diffusion layer 38 having a high concentration of n-type impurities is introduced. Are formed. Thus, the power supply for fixing the potentials of the wells W1, W2, W3, and W4 can be independently performed in each of the circuit blocks M1, M2, M3, and M4, and the variation of the fixed potential due to the substrate bias can be suppressed. It can be further suppressed as compared with the case of the first embodiment.

In the present embodiment, the substrate bias is supplied from the outside. However, when the substrate bias power supply is built in the semiconductor chip 24, each circuit block M1, M2, M3, M4 is By providing a substrate bias power supply in the above and electrically separating each wiring in the same manner as the power supply voltage supply line 36 of FIG. 3, the same effect as described above can be obtained.

[0033]

As described above, according to the semiconductor integrated circuit of the present invention, since the circuit blocks constituting the semiconductor integrated circuit which operate asynchronously with each other are formed in separate wells, it is possible to Even if the well potential changes, the threshold voltage of the transistor does not change in other wells.

Further, in the semiconductor integrated circuit, the power supply line and the signal line are electrically separated from each other and wired, and in the semiconductor device of the present invention having the built-in power supply line and the signal line, the external state is maintained while maintaining the electrically separated state. Since the circuit blocks are connected to the terminals, the circuit blocks operate asynchronously with each other, and even if the potential of each line fluctuates, the potential fluctuation is not input to other circuit blocks.

As a result, it is possible to provide a semiconductor integrated circuit and a semiconductor device that effectively prevent the occurrence of interference noise, which has been a problem in the past. That is, according to the present invention, it becomes possible to operate each circuit block asynchronously without disturbing the normal operation of each other, and as a result, it is expected that the operating speed and efficiency of the semiconductor device will be further improved. It

[Brief description of drawings]

FIG. 1 is a top view showing a schematic configuration inside a semiconductor device according to a first embodiment of the present invention.

2 is a schematic cross-sectional view of the semiconductor integrated circuit taken along the line II-II in FIG.

FIG. 3 is a top view showing a schematic configuration of the inside of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of the semiconductor integrated circuit taken along the line III-III in FIG.

FIG. 5 is a model of an operation simulation of a DRAM memory block having a common power supply line, which has clarified the problems of the conventional example and is the basis of the present invention.

FIG. 6 is a result of an operation simulation performed using the model of FIG. 5, and particularly, after a bit line of the first memory block is raised, the storage data of another second memory block is slightly delayed. This is the case of reading.

FIG. 6 is a result of the same simulation, in which the bit lines of the first and second memory blocks are activated almost at the same time, data is written in the first memory block, and data is stored in the second memory block. This is the case of reading data.

[Explanation of symbols]

20 ... Semiconductor device, 22 ... Package, 24 ... Semiconductor chip (semiconductor integrated circuit), 26 ... Semiconductor substrate, 28 ... Power supply line (power supply line), 30 ... Reference voltage supply line (power supply line), 32 ... Input signal Line (signal line), 34 ... output signal line (signal line), 36 ... substrate bias power supply voltage supply line (power line), 38 ... impurity diffusion layer, M1 to M4 ... memory blocks (circuits that operate asynchronously with each other) Block), W
1 to W4 ... Well, VDD1 to VDD4 ... External terminal (terminal) connected to each power supply voltage supply line, Vss1 to Vss4 ... External terminal (terminal) connected to each reference voltage supply line, Vin1 to
Vin4 ... External terminal (terminal) connected to each input signal line,
Vout1 to Vout4 ... External terminals (terminals) connected to each output signal line, VBB1 to VBB4 ... External terminals connected to each power supply voltage supply line for substrate bias, WORD ... Word line,
BIT ... bit line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ken Matsumoto 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (4)

[Claims] 1. A device comprising at least two wells formed on the surface of a semiconductor substrate and an element group including transistors formed on the well surface side, the wells being arranged separately from each other and operating asynchronously with each other. A semiconductor integrated circuit having two circuit blocks and a power supply line and a signal line electrically connected to each circuit block and electrically separated for each circuit block operating asynchronously with each other. 2. The semiconductor integrated circuit according to claim 1, wherein the circuit block includes each memory block formed by dividing a memory cell array into several memory cell aggregates. 3. The semiconductor integrated circuit according to claim 1 is built-in, and any one of the power supply line and the signal line is internally connected while maintaining an electrically separated state for each of the asynchronously operating circuit blocks. Semiconductor device having a plurality of formed terminals on its outer peripheral surface. 4. The semiconductor integrated circuit according to claim 2 is built in, and any one of the power supply line and the signal line is internally connected while maintaining an electrically separated state for each of the asynchronously operating circuit blocks. Semiconductor device having a plurality of formed terminals on its outer peripheral surface.