JP2001035994A - Semiconductor integrated-circuit device and system substratte - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve integration degree and to reduce size by forming a second well region selectively in an island shape into a first well region, arranging two chips at the second well region, and gluing the rear sides of the chips with a conductive adhesive. SOLUTION: A P-type well 23-2 and an N-type well 24-2 are formed in a large N-type well 22-2. An N-channel-type MOSFET1 is formed in the P-type well 23-2, and a low-potential power supply VSS is supplied. Also, the P-channel- type MOSFET1 is formed at the N-type well 24-2, and a high-potential power supply VCC that is the same as the large N-type well is supplied. Further, a P-type well 25-2 is formed in the large N-type well 22-2. An N-type well 26-2 and a P-type well 27-2 are formed in the P-type well 25-2, and a PMOS2 and an NMOS2 are formed in the N-type well 26-2 and the P-type well 27-2, respectively. The rear sides of the chips are glued and laminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a system board, and more particularly to a semiconductor integrated circuit device having chip back surfaces bonded to each other and a system board having a plurality of the same mounted thereon. It is used to improve the degree of integration and downsizing of the system board of the device incorporating the device.

[0002]

2. Description of the Related Art There is an increasing demand for multifunctional, miniaturized, and low-priced products that use semiconductor devices, particularly in the fields of personal computers, mobile phones, game machines and the like.

[0003] As multi-functionality is promoted, the system becomes complicated, and semiconductor devices having various functions are required.
Requires a huge amount of memory. Therefore, the number of single semiconductor devices required for constructing the system increases.

In a single semiconductor device, many functions, especially a processor, are being integrated into one chip year by year, and the size is reduced. Similarly, the memory device has been increased in the capacity integrated on one chip, and has also been reduced in size.

[0005] At present, the technology of memory cards is being developed for high integration, high reliability and miniaturization in order to replace storage media controlled by mechanical control such as a floppy disk drive and a hard disk drive. In the fields of digital cameras, voice recorders, and the like, memory cards have been gradually adopted as replacements for small-capacity storage media (films, tapes, and the like).

However, at present, memory cards are expensive, and in order to replace large-capacity storage media (floppy disk, hard disk, etc.), further higher integration and lower cost are desired. At the present time, advanced processes and circuit technologies are employed to achieve high integration and low cost, but the manufacturing cost is high and the expansion of the memory card market is limited. Further, as the capacity of the memory increases, the chip size increases, making it difficult to improve the yield, leading to an increase in cost.

[0007] Against this background, the memory capacity is easily increased by the technique of laminating the back surfaces of two memory chips having relatively small capacities by bonding them with an insulating adhesive to easily compare the memory capacities of the memory capacities. A technology for realizing a low cost has been proposed.

However, even if such a chip stacking technique is used, if a miniaturization technique is introduced in order to meet the market demand for a lower price and a smaller size of the chip, the conventional element separation technique and the circuit separation technique will fail. The substrate potential becomes unstable due to noise or the like generated in each circuit. In particular, when the low power supply voltage is advanced, the operation margin of the signal voltage with respect to the power supply voltage is reduced, and the above-described malfunction becomes remarkable.

[0009] These problems will be specifically described below.

FIG. 18A shows a cross-sectional structure of a memory chip having an example of a conventional CMOS structure. A cross-section of a state where two back surfaces of this chip are laminated by bonding with an insulating adhesive. The structure is shown in FIG.

That is, in the CMOS structure using the triple well structure as shown in FIG. 18A, the first P well 182 and the first N well 18 are selectively provided on the surface layer of the N type substrate 181.
3. A second P well 184 and a substrate electrode region 185 are formed. The second P-well 182 has a second layer selectively on the surface layer thereof.
The N well 186, the source / drain region 187 of the NMOSFET and the P well electrode region 188 are formed. The first N well 183 and the second N well 186 have a source / drain region 18 of a PMOSFET.
9 and an N-well electrode region 190 are formed. In the second P well 184, a source / drain region 191 of an NMOSFET and a P well electrode region 192 are formed.

Such a triple well structure is used when the circuit operates by changing the external power supply voltage and the power supply voltage of the internal circuit. In this case, generally the first
The second N well 186 in the P well 182 has an N-type substrate.
A potential VCC2 lower than the potential 181 (power supply voltage VCC1) is applied.

As shown in FIG. 18B, two memory chips 193 having the structure shown in FIG.
When the back surfaces are laminated by bonding with the adhesive 194,
If the power supply voltage VCC1 is lower than, for example, 2.5 V, the data content of the memory cell of one of the memory chips may be destroyed due to the ripple of the power supply voltage. However, unevenness in the insulation distance between chips causes a problem due to unevenness of the wrap surface on the back surface of the chip.

On the other hand, a technique (so-called system-on-silicon technique) for mounting a plurality of functional circuits having different functions on a single semiconductor chip has been sought.

It is possible to apply the conventional lamination technique as it is to a chip in which a plurality of functional circuits are mixedly mounted, but it is effective to use the technique in combination with a technique of separating each functional circuit from each other by an isolation region. It is desired to devise a method of applying a simple chip bonding and lamination technique.

[0016]

As described above, the conventional chip laminating technique using an insulating adhesive has a problem that an operation margin is reduced when a low-voltage operation is advanced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and even when at least two back surfaces of a semiconductor integrated circuit chip on which a plurality of functional circuits are mounted are bonded together, heat dissipation characteristics are improved and electrical characteristics are improved. It is an object of the present invention to provide a semiconductor integrated circuit device capable of reducing an adverse effect on a semiconductor device and stabilizing an operation particularly under a low-voltage operation.

Another object of the present invention is to provide a semiconductor integrated circuit device capable of easily increasing the memory capacity at relatively low cost when applied to a chip having a memory function.

Another object of the present invention is to improve the degree of integration and reduce the size by mounting a plurality of semiconductor integrated circuit devices of the multi-chip bonding type according to the present invention, and have a memory function. It is an object of the present invention to provide a system board that can realize a medium capacity and a large capacity at a relatively low cost when a chip is used.

[0020]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device in which a plurality of islands are selectively formed in an island shape on a surface layer of a semiconductor substrate of the first conductivity type. A first well region of a second conductivity type which is a conductivity type; a second well of a first conductivity type selectively formed in the first well region in an island shape;
And two chips including a functional circuit formed in at least the second well region and a conductive adhesive in which the back surfaces of the two chips are bonded to each other. I do.

A second semiconductor integrated circuit device according to the present invention is characterized by further comprising a printed wiring member in which at least one first semiconductor integrated circuit device according to the present invention is assembled.

According to a third semiconductor integrated circuit device of the present invention, two chips each having a plurality of chip regions adjacent to each other with an inter-chip separation region as a unit, and the back surfaces of the two chips are bonded to each other. Wherein each chip region has a first well region of a second conductivity type, which is a conductivity type opposite to the first conductivity type, on a surface layer portion of a semiconductor substrate of the first conductivity type. A plurality of islands are selectively formed in an island shape, a second well region of a first conductivity type is selectively formed in an island shape in the first well region, and a functional circuit is formed at least in the second well region. It is characterized by having been done.

A fourth semiconductor integrated circuit device according to the present invention is characterized by further comprising a printed wiring member in which at least one third semiconductor integrated circuit device according to the present invention is assembled.

According to a fifth semiconductor integrated circuit device of the present invention, a second conductive type is formed on the surface layer portion of the semiconductor substrate of the first conductive type, which is selectively formed in a plurality of islands and has a conductive type opposite to the first conductive type. A first well region of a conductivity type, a second well region of a first conductivity type selectively formed in an island shape in the first well region, and a functional circuit formed in at least the second well region First and second having at least one chip region including
And a third chip, a conductive adhesive bonding the back surfaces of the first and second chips to each other, one side of the first chip and one side of the third chip laminated by the bonding Flip-chip connection part whose sides are fixed by a flip-chip method, a printed wiring member in which the other side of the third chip is assembled, a chip having a three-layer laminated structure assembled on the printed wiring member and the printed wiring member And a package having a plurality of external terminals that are selectively and electrically connected to the other surface side of the second chip and the connection terminals on the printed wiring member.

A system board according to the present invention is characterized in that a plurality of the semiconductor integrated circuit devices according to the present invention are mounted on one or both sides of a printed wiring board.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment of Semiconductor Integrated Circuit Device>
FIG. 1 schematically shows a cross-sectional structure according to a first embodiment of the semiconductor integrated circuit device of the present invention.

The first chip 11 and the second chip 12
Conductive adhesive 13 with good thermal conductivity on each back
And laminated. Each of these chips
This is a semiconductor integrated circuit chip on which a plurality of functional circuits are mixed, and will be described in detail later. As an example, a plurality of semiconductor layers (well regions) selectively formed in an island shape on a surface layer portion of a semiconductor substrate are described. , SRAM,
A chip region in which functional circuits such as a DRAM and a Flash-EEPROM are formed and each functional circuit is insulated from each other by an isolation region is divided from a wafer.

Each of the chips 11 and 12 is not limited to a chip in which a plurality of types of functional circuits are formed corresponding to a plurality of well regions (for example, a memory-embedded chip). Is a chip formed with a plurality of well regions corresponding to a plurality of well regions (for example, a memory chip in which a memory cell array of a semiconductor memory, a peripheral circuit, an input / output circuit, etc. are formed corresponding to a plurality of well regions). Good.

The two chips having such an adhesive laminated structure are assembled on a printed wiring member (for example, a printed wiring board) 14 slightly larger than the chip size and sealed with, for example, an insulating resin 15 to form a resin-sealed mold. The semiconductor integrated circuit device having the chip size package of FIG.

In this case, the element / connection terminal forming surface of the first chip 11 is fixedly connected to the printed wiring board 14 by a flip chip method, and the connection terminal of the element / connection terminal forming surface of the second chip 12 is For example, it is connected to a connection terminal on the printed wiring member by a bonding wire 16. The bonding wire and the two chips of the adhesive laminated structure are sealed with the resin 15.

On the back surface (the surface on which the chip is not mounted) of the printed wiring member 14, a group of external connection terminals 17 of, for example, a ball grid array type is formed. The connection terminals on the element / connection terminal formation surface of the second chip 12 may be connected to the outside via bump electrodes (not shown).

According to the first embodiment of such a semiconductor integrated circuit device, the back surfaces of the two chips are laminated by bonding with an adhesive having good thermal conductivity, so that one of the chips is Even if heat is generated in the operating state, if at least a part of the other chip (for example, the memory unit) generates little heat in the standby state, for example, the heat generated from the one chip can be radiated from the other chip. So
Heat dissipation characteristics are improved.

Further, since the back surfaces of the chips are laminated by bonding with a conductive adhesive, the substrate potential of each chip is stabilized by equipotential, so that when the low power supply voltage is advanced, The adverse effect on the electrical characteristics due to the reduction of the operation margin is reduced. In particular, each chip is a chip in which a plurality of function circuits are mixedly mounted, and the plurality of function circuits are insulated and separated from each other by a well region, and have little influence on each other. Has little adverse effect on electrical characteristics.

Further, since the back surfaces of the respective chips are laminated by being adhered to each other with a conductive adhesive, the problem of variation in the insulation distance between chips does not occur even if there is unevenness on the wrap surface of the back surface of each chip. .

Therefore, when the semiconductor integrated circuit device according to the first embodiment is applied to a chip having a memory function, the memory capacity can be easily increased at relatively low cost.

The above-mentioned case is also applicable to a case where two or more sets are assembled on a printed wiring member and a resin-sealed semiconductor integrated circuit device, for example, is formed by using the chips stacked by bonding as one set as described above. Such effects can be similarly obtained.

Further, also in the case where a semiconductor integrated circuit device in a state where the back surfaces of the two chips are adhered to each other with a conductive adhesive and stacked (a state in which the two chips are not assembled on a printed wiring member) is formed, The same effects as in the first embodiment can be obtained.

FIG. 2 is a sectional view showing a modification of the semiconductor integrated circuit device shown in FIG.

This semiconductor integrated circuit device is different from the semiconductor integrated circuit device shown in FIG. 1 in that the capacitor, inductance, resistance,
In this modification, an electronic component 21 such as an oscillation circuit and a decoder circuit is mounted and an electronic component externally connected to a conventional semiconductor integrated circuit device is incorporated.

In this case, a semiconductor integrated circuit device requiring high-speed operation generally requires a large number of power supply capacitors. However, since the power supply capacitors are changed to include these capacitors, a smaller memory card or the like can be realized. it can.

Next, an example of an embodiment of a chip area on a wafer before dividing each chip from the wafer according to the first embodiment will be described.

FIG. 13 is a sectional view schematically showing an example of a chip area on a wafer.

As shown in FIG. 13, in the chip area 1,
A plurality of semiconductor layers (N-well regions) of a conductivity type opposite to that of the P-type substrate are selectively formed in an island shape on the surface layer of the P-type silicon substrate (P-SUB) 10. A plurality of functional circuits are formed in each of the N-well regions, and the functional circuits are insulated from each other by the isolation regions. This isolation region is formed over the entire periphery of the side surface of the chip region 1, and in this example, a P-type silicon substrate 10 is used.

In the chip area 1 shown in FIG. 13, for example, a plurality of functional circuits having different functions are mixedly mounted, and among the plurality of functional circuits, a functional circuit for fluctuating the potential of the chip is separated by another area into another functional circuit. Separated from the circuit, the isolation region is formed over the entire periphery of the side surface of the chip.

According to such a chip area 1, in particular, a functional circuit (including at least one of a nonvolatile memory circuit and an analog circuit) for fluctuating the potential of the chip is separated into other functional circuits (digital circuit, digital / digital (Including at least one of an analog conversion circuit, a static memory circuit, and a dynamic memory circuit), so that a functional circuit that swings the potential of the chip does not affect other functional circuits.

In this embodiment, the plurality of functional circuits include a processor 2, an SRAM 3, a DRAM 4, a Flash-EEPR
OM5 and the like are formed.

The processor 2 includes a microprocessor (CPU), a central processing unit (DS),
It includes a circuit basically configured by a logic circuit, such as a control circuit such as a P (Digital Signal Processor) or an arithmetic circuit. The SRAM 3 includes a memory circuit basically including a logic circuit, such as a cross-coupled latch circuit, in addition to the SRAM. The DRAM 4 includes a DRAM of a synchronous control in addition to a DRAM of an asynchronous control. The Flash-EEPROM 5 has a NOR type and a NA type.
Also includes ND type.

That is, in FIG. 13, a plurality of large N-type wells (N-WEL) are provided in the P-type silicon substrate 10.
L) 22-2 to 22-5 are provided, and the processor 2, the SRAM 3, the DRAM 4, and the Flash-
An EEPROM 5 is formed.

The large wells 22-2 to 22-5 are supplied with an optimum power supply potential for each functional circuit. High potential power supply VCC is applied to well 22-2, and well 2
The high-potential power supply VDD3 is supplied to the well 22-4, the high-potential power supply VDD4 is supplied to the well 22-4, and the high-potential power supply VDD5 is supplied to the well 22-5.

The high-potential power supply VCC is an external power supply supplied from outside the chip 1 together with a low-potential power supply VSS (not shown). The high-potential power supplies VDD3 to VDD5 are respectively
This is an internal power supply generated by converting a voltage of the external power supply VCC in the chip 1. The voltage conversion includes step-down for lowering the level of the external power supply and step-up for raising the level. The P-type silicon substrate 10 is grounded during actual use and during testing.

The chip as shown in FIG. 13 as described above includes a processor 2, an SRAM 3, a DRAM 4, and a flash memory.
Functional circuits such as the EEPROM 5 are formed in N-type wells 22-2 to 22-5, respectively, and the respective functional circuits are mutually connected by a PN junction between the N-type wells 22-2 to 22-5 and the P-type silicon substrate 10. Are separated. Therefore, each of the functional circuits can be tested without being affected by other functional circuits. This makes it possible to accurately measure the characteristics of each of a plurality of functional circuits having different functions, which are mounted on one chip 1.

Further, since the P-type silicon substrate 10 is the wafer itself, the respective functional circuits are separated from each other even between the respective chips. Therefore, a plurality of chips 1 can be tested at the same time without affecting each of the functional circuits included in the chip 1 by the functional circuits included in other chips. Thus, the characteristics of each of a plurality of functional circuits having different functions mixedly mounted on one chip 1 can be simultaneously and accurately measured by the plurality of chips 1.

Since different potentials are supplied to the wells 22-2 to 22-5, it is necessary to supply a power supply potential to each function circuit so as to maximize the characteristics of each function circuit. Can be.

Hereinafter, each well 22-2 to 22-5 in FIG.
Will be described in detail.

FIG. 14 is a sectional view showing the well 22-2 shown in FIG.

As shown in FIG. 14, a large N-type well 2
2-2 includes a P-type well 23-2 and an N-type well 24-2.
Are formed respectively. A low potential power supply VSS (ground potential) is supplied to the P-type well 23-2. An N-channel MOSFET (hereinafter referred to as NM) is provided in the P-type well 23-2.
OS) 1 is formed. Also, N-type well 2
4-2 is supplied with the same high potential power supply VCC as the large N-type well 22-2. A P-channel MOSFET (hereinafter referred to as PMOS) 1 is formed in the N-type well 24-2. The N-type well 24-2 is a large N-type well 2
It has an impurity concentration higher than 2-2. This allows
The PMOS 1 can be miniaturized, but the N-type well 24-2 is
You don't have to.

In the large N-type well 22-2, a P-type well 25-2 is formed. In the P-type well 25-2,
A low potential power supply VSS (ground potential) is supplied. An N-type well 26-2 and a P-type well 27-2 are formed in the P-type well 25-2. N-type well 26
-2 is supplied with the high potential power supply VDD2. Power supply VD
D2 is different from the power supply VCC, and is an internal power supply generated by performing voltage conversion of the external power supply potential in the chip 1. The PMOS 2 is formed in the N-type well 26-2. The P-well 27-2 is supplied with a low potential power VSS. The NMOS 2 is formed in the P-type well 27-2. The P-well 27-2 is a P-well 25-2.
It has a higher impurity concentration. P-type well 27-2
Need not be provided like the N-type well 24-2.

The processor 2 basically includes the NMOS 1,
2, PMOS 1 and 2
Are NMOS2, P2 driven by the internal power supply VDD2.
You may make it comprise only MOS2. In this case, the NMOS1, PM2 driven by the external power supply VCC
OS1 is, for example, from the external power supply VCC to the internal power supply VDD2.
It may be used for a voltage generating circuit or the like for generating the voltage. The large N-type well 22-2 includes a P-type well 25.
A plurality of P-type wells similar to -2 may be formed.

Note that in FIG.
The gate of the OSFET is shown.

FIG. 15 is a sectional view showing the well 22-3 shown in FIG.

As shown in FIG. 15, a large N-type well 2
2-3 include a P-type well 23-3 and an N-type well 24-3.
Are formed respectively. A low potential power supply VSS (ground potential) is supplied to the P-type well 23-3. The NMOS 3 is formed in the P-type well 23-3. Also, N
In the mold well 24-3, the same as the large N-type well 22-3,
The high potential internal power supply VDD3 is supplied. The PMOS 3 is formed in the N-type well 24-3. N-type well 2
4-3 has a higher impurity concentration than the large N-type well 22-3. The N-type well 24-3 may not be provided.

In the large N-type well 22-3, a P-type well 25-3 is formed. In the P-type well 25-3,
A low potential power supply VSS (ground potential) is supplied. An N-type well 26-3 and a P-type well 27-3 are formed in the P-type well 25-3. N-type well 26
-3 is supplied with a high potential internal power supply VDD3 '. The internal power supply VDD3 'is generated by converting the voltage of the internal power supply VDD3 in the chip 1. The PMOS 4 is formed in the N-type well 26-3. Also, the P-type well 27-3
Is supplied with a low-potential power supply VSS. The NMOS 4 is formed in the P-type well 27-3. P-type well 2
7-3 has a higher impurity concentration than the P-type well 25-3. The P-type well 27-3 may not be provided like the N-type well 24-3.

The SRAM 3 basically includes an NMOS 3,
4, PMOS3, 4, SRAM3
Are NMOS4 driven by the internal power supply VDD3 ',
You may make it comprise only PMOS4. In this case, the NMOS3 driven by the internal power supply VDD3,
The PMOS3 is, for example, from the internal power supply VDD3 to the internal power supply V
It may be used for a voltage generating circuit that generates DD3 '. Further, a plurality of P-type wells similar to the P-type well 25-3 may be formed in the large N-type well 22-3.

In FIG. 15, reference numeral G denotes M
The gate of the OSFET is shown.

FIGS. 16A and 16B are sectional views showing the well 22-4 in FIG.

As shown in FIGS. 16A and 16B,
A large N-type well 22-4 has a P-type well 23-4.
And an N-type well 24-4 are formed. P
The mold well 23-4 is supplied with a low potential power supply VSS (ground potential). The NMOS 5 is formed in the P-type well 23-4. The N-well 24-4 is supplied with the same high-potential internal power supply VDD4 as the large N-well 22-4. The PMOS 5 is formed in the N-type well 24-4. The N-type well 24-4 is a large N-type well 22-4.
It has a higher impurity concentration. N-type well 24-4
May not be required.

Further, in the large N-type well 22-4, three P-type wells 25A-4, 25B-4 and 25C-4 are formed.

The first P-type well 25A-4 is supplied with a negative potential power supply VBB (about -2 to -3 V). The negative potential power supply VBB is generated by converting the voltage of the internal power supply VDD4 in the chip 1. A dynamic memory cell transistor is formed in the P-type well 25A-4.

The low potential power supply VSS (ground potential) is supplied to the second P-type well 25B-4. P-type well 2
5B-4 includes an N-type well 26B-4 and a P-type well 2
7B-4 are formed. N-type well 26B
-4 is supplied with a high potential internal power supply VDD4 '. The internal power supply VDD4 'is generated by converting the voltage of the internal power supply VDD4 in the chip 1. The PMOS 6 is formed in the N-type well 26B-4. Also, the P-type well 27
B-4 is supplied with a low potential power supply VSS. The NMOS 6 is formed in the P-type well 27B-4. P-type well 27B-4 has a higher impurity concentration than P-type well 25B-4. The P-well 27B-4 may not be provided like the N-well 24-4.

The third P-type well 25C-4 is supplied with a negative potential power supply VBB (about -2 to -3 V). An N-type well 26C-4 and a P-type well 27C-4 are formed in the P-type well 25C-4. The high potential internal power supply VDD4 '' is supplied to the N-type well 26C-4. The internal power supply VDD4 ″ is generated by converting the voltage of the internal power supply VDD4 in the chip 1. The PMOS 7 is formed in the N-type well 26C-4. Also, P
A negative potential power supply VBB is supplied to the mold well 27C-4. The NMOS 7 is formed in the P-type well 27C-4. P-type well 27C-4 has a higher impurity concentration than P-type well 25C-4. The P-type well 27C-4
Like the N-type well 24-4, it may not be provided.

The memory cell array of the DRAM 4 is composed of dynamic memory cell transistors,
Peripheral circuits of AM4 are NMOS5,6, PMOS5,6
It consists of. The peripheral circuit of the DRAM 4 may be constituted by only the NMOS 6 and the PMOS 6 driven by the internal power supply VDD 4 ′. In this case, the NMOS 5 and the PMOS 5 driven by the internal power supply VDD4
Are, for example, from the internal power supply VDD4 to the internal power supply VDD4 ′,
It may be used for a voltage generation circuit that generates VDD4 ″ and VBB.

The peripheral circuit of the DRAM 4 includes a circuit using the boosted potential VPP, for example, a word line driver and the like. To construct such a circuit, P
An N-type well to which the boosted potential VPP is supplied may be formed in the type well 25B-4 or the like.

The NMOS 7 and the PMOS 7 formed in the P-type well 25C-4 supplied with the negative potential power supply VBB
Reference numeral 7 denotes, for example, an input / output circuit for exchanging signals with the outside of the chip 1 and a processor 2 formed in another well.
For example, it may be used to form an internal interface circuit which is formed on the chip 1 and exchanges signals with other functional circuits driven by different power supplies. A surge may be input to the input / output circuit or the internal interface circuit. In order to clamp this surge, a negative potential VBB is supplied to the P-type well 25C-4.
The P-type wells to which such a negative potential is supplied include not only the N-type well 22-4 but also the N-type wells 22-2, 22-3, 2-3.
2-5 may be provided for each. In the P-type well to which a negative potential is supplied, an input / output circuit for exchanging signals with the outside of the chip 1 and an internal interface circuit for exchanging signals with other functional circuits may be formed.

In FIGS. 16A and 16B, reference numeral G indicates the gate of the MOSFET, and reference numeral B
L denotes a bit line, WL denotes a word line, PL denotes a plate electrode of a memory capacitor, and S denotes
N indicates a storage electrode of the memory capacitor.

FIGS. 17A and 17B respectively show FIGS.
3 is a sectional view showing a well 22-5 in FIG.

As shown in FIGS. 17A and 17B,
In the large N-type well 22-5, there is a P-type well 23-5.
And an N-type well 24-5 are formed. P
A low potential power VSS (ground potential) is supplied to the mold well 23-5. The NMOS 9 is formed in the P-type well 23-5. The N-well 24-5 is supplied with the same high-potential internal power supply VDD5 as the large N-well 22-5. The PMOS 9 is formed in the N-type well 24-5. The N-well 24-5 is a large N-well 22-5.
It has a higher impurity concentration. N-type well 24-5
May be omitted. Furthermore, a large N-type well 22-5
Are formed with two P-type wells 25A-5 and 25B-5.

The first P-type well 25A-5 is supplied with a low potential power supply VSS (ground potential). P-type well 2
5A-5 includes an N-type well 26A-5 and a P-type well 2
7A-5 are formed. N-type well 26A
-5 is supplied with a high-potential internal power supply VDD5 ''.
The internal power supply VDD5 ″ is connected to the chip 1 by the internal power supply VDD5.
It is generated by voltage conversion inside. N-type well 26A
At -5, a PMOS 8 is formed. The P-well 27A-5 is supplied with a low potential power VSS. P
The NMOS 8 is formed in the mold well 27A-5. P
The mold well 27A-5 has a higher impurity concentration than the P-well 25A-5. The P-well 27A-5 may not be provided like the N-well 24-5.

In the first P-type well 25A-5, an N-type well 26A0-5 is further formed.
The N-well 26A0-5 has a high potential internal power supply VDD5 '.
And the boosted potential VEE are switched and supplied to each other. The internal power supply VDD5 'and the boosted potential VEE are generated by converting the voltage of the internal power supply VDD5 in the chip 1. A P-type well 28-5 is formed in the N-type well 26A0-5. P-type well 2
8-5, a low-potential power supply VSS, a boosted potential VEE, and a step-down potential VBB are switched and supplied to each other. The step-down potential VBB is generated by converting the voltage of the internal power supply VDD5 in the chip 1. In the P-type well 28-5, a NAND-type memory cell transistor is formed. When erasing data from the NAND type memory cell transistor, the control gate CG is grounded,
The boosted potential VEE is supplied to each of the N-well 26A0-5 and the P-well 28-5. This allows the electrons to
The data is erased from the floating gate FG to the P-type well 28-5, and the data is erased. On the other hand, when writing data to the NAND-type memory cell transistor, the control gate CG is set to the program voltage, and the potential VD is applied to the N-type well 26A0-5.
D5 'is supplied, and the reduced potential VBB is supplied to the P-type well 28-5. Thus, electrons are injected into the floating gate FG from the channel below the floating gate FG, and data is written. When reading data stored in the NAND type memory cell transistor, the control gate C
G is a read voltage, and the potential V is applied to the N-type well 26A0-5.
DD5 'is supplied and the low potential VSS is supplied to the P-type well 28-5. Thereby, data of “0, 1”, which is represented by whether or not a current flows through the channel, is determined according to the charging state of the floating gate FG, and the data is read out to the bit line BL.

The low potential power VSS (ground potential) is supplied to the second P-type well 25B-5. P-type well 2
5B-5 includes an N-type well 26B-5 and a P-type well 2
7B-5 are formed respectively. N-type well 26B
-5 is supplied with a high-potential internal power supply VDD5 "". The internal power supply VDD5 ″ ″ is generated by converting the voltage of the internal power supply VDD5 in the chip 1. The PMOS 10 is formed in the N-type well 26B-5. Also, P
The low potential power VSS is supplied to the mold well 27B-5. The NMOS 10 is formed in the P-type well 27B-5. P-type well 27B-5 has a higher impurity concentration than P-type well 25B-5. P-type well 27B-5
Need not be provided like the N-type well 24-5.

The memory cell array of the Flash-EEPROM 5 is composed of NAND-type memory cell transistors.
9, 10, and PMOSs 8, 9, and 10. Fl
The peripheral circuit of the ash-EEPROM 5 is composed of an internal power supply VDD5 '.
, NMOS 8 driven by VDD 5 ′ ″
0, PMOS 8 and 10 only. In this case, the NMOS 9 and the PMOS 9 driven by the internal power supply VDD5 are, for example, changed from the internal power supply VDD5 to the internal power supply VDD5 ′, VDD5 ″, VDD5 ″.
', VBB, VEE.

In FIGS. 17A and 17B, reference numeral G indicates a gate of the MOSFET.

In the above embodiment, the external potential power supply VCC
Was given to the well in which the processor 2 was formed,
It may be provided to a well in which another functional circuit is formed. Further, a well to which the external potential power supply VCC is applied may be further formed, and a circuit for generating a potential to be applied to another well may be formed in this well.

<Second Embodiment of Semiconductor Integrated Circuit Device>
In the first embodiment, the chip (region) back surfaces are bonded and laminated in units of one chip (region), but the second embodiment in which the chip back surfaces are bonded and laminated in units of a plurality of chip regions An embodiment will be described below.

FIGS. 3A and 3B each schematically show a cross-sectional structure according to a second embodiment of the semiconductor integrated circuit device of the present invention.

The first set of chips and the second set of chips are:
It is divided into a plurality of adjacent chip areas (two chip areas in this example) 30 determined as non-defective products by inspection in a state where elements are formed on a wafer. In this case, FIG. 3A shows an example in which two chip areas adjacent to each other in the X direction of the XY coordinate axis of the wafer surface are divided as a unit, and two chip areas adjacent to each other in the Y direction of the XY coordinate axis of the wafer surface are used as a unit. FIG. 3B shows an example of the division.

Each of the chip areas 30 is a chip on which a plurality of types of functional circuits are mounted or a chip on which a single type of functional circuit is formed (for example, a memory chip), similarly to the respective chips in the first embodiment. is there. In this case, since the inter-chip region (dicing line portion) is a separation region by the wafer itself, each set of chips is insulated and separated.

The back surfaces of two sets of chip regions each having two chip regions as a unit are laminated by bonding with a conductive adhesive having good thermal conductivity. Then, four chips of such an adhesive laminated structure are assembled on a printed wiring member and sealed with, for example, an insulating resin (not shown) to obtain a semiconductor integrated circuit device. In this case, the element / connection terminal formation surface of the first set of chip areas is 2 mm in chip size.
It is connected and fixed by a flip chip method on a printed wiring member 31a or 31b slightly larger than twice, and the connection terminals on the element / connection terminal formation surface of the second set of chip areas are connected to the printed wiring board by, for example, bonding wires 32. Connected to the connection terminal. The bonding wire and the two chips of the adhesive laminated structure are sealed with resin.

Note that, for example, a ball grid array type external connection terminal group is formed on the back surface (non-chip mounting surface) of the printed wiring member. The connection terminals on the element / connection terminal formation surface of the second set of chip regions may be connected to the outside via bump electrodes (not shown).

In the semiconductor integrated circuit device according to the second embodiment, an adhesive having good heat conductivity is formed on the back surfaces of two sets of chip regions (for a total of four chips) in units of two chip regions. And the semiconductor integrated circuit device according to the first embodiment, the plane size is almost twice as large as that of the semiconductor integrated circuit device according to the first embodiment. The other effects are basically the same as those of the first embodiment.

Note that, as a plurality of adjacent chip areas,
In this example, the case where the unit is a two-chip area is shown. However, the present invention is not limited to this, and the unit can be expanded to three chip areas, four chip areas, and so on.

The above-described case is also applicable to a case where a semiconductor integrated circuit device in which two or more sets are assembled on a printed wiring member to form, for example, a resin-encapsulated semiconductor chip as a set of chips stacked by bonding as described above. Such effects can be similarly obtained.

Also, a semiconductor integrated circuit device in a state where the back surfaces of the two sets of chip regions are laminated by bonding with a conductive adhesive (a state where they are not assembled on a printed wiring member) may be used. The above-described effects can be similarly obtained.

<Third Embodiment of Semiconductor Integrated Circuit Device>
In the first embodiment and the second embodiment, the two-stage adhesive laminated structure in which the back surfaces of the chips (regions) are bonded to each other is shown, but the element / connection terminal formation surface of the chip (region) on one side is shown. Element of the third chip (area) different from the connection terminal of
Regarding a third embodiment in which a connection terminal on a connection terminal formation surface is connected via a bump electrode to realize a three-layered structure,
This will be described below.

FIG. 4 schematically shows a sectional structure according to a third embodiment of the semiconductor integrated circuit device of the present invention.

In FIG. 4, reference numeral 40 denotes FIG.
As described above with reference to (a) and (b), the semiconductor integrated circuit device in a state before packaging of a two-stage adhesive laminated structure, and 41 is a third chip (or third set) separately prepared Chip area).

The element / connection terminal forming surface on one side of the third chip (or the third set of chip areas) is connected and fixed on the printed wiring member 42 by a flip chip method, and the element / connection on the other side. An element / connection terminal formation surface on one side of the first chip (or a first set of chip regions) is connected and fixed to the terminal formation surface by a flip chip method.

The printed wiring member 42 is housed in the case 431, 432 of the package, and is connected to the connection terminal of the element / connection terminal forming surface on one side of the second chip (or the second set of chip areas). The element / connection terminal formation surface on one side of the third chip (or third chip area) is connected to a relay connection node in the case by, for example, a bonding wire 44, and the relay connection node The external terminals 45 projecting from the bottom surface of the package, for example, in the form of pins, are electrically connected.

Although an example is shown in which a pin-shaped external terminal group is formed on the bottom surface of the package, the type of this package is not particularly limited.
(Ball grid array), CSP (chip size package), or the like. FIG. 5 is a sectional view showing a modification of the semiconductor integrated circuit device shown in FIG.

This semiconductor integrated circuit device is different from the semiconductor integrated circuit device shown in FIG. 4 in that the capacitor, inductance, resistance,
An electronic component 51 such as an oscillation circuit and a decoder circuit is mounted, and the electronic component which is externally connected to the conventional semiconductor integrated circuit device is changed to be built-in.
Is used.

In this case, the connection terminals on the element / connection terminal formation surface of the second set of chip regions may be connected to electronic components via bump electrodes (not shown).

FIG. 6 schematically shows a cross-sectional structure according to a fourth embodiment of the semiconductor integrated circuit device of the present invention.

In FIG. 6, reference numerals 61 and 62 denote two semiconductors in a state before packaging of a two-stage adhesive laminated structure as described above with reference to FIG. 1 or FIGS. 3A and 3B, respectively. These are integrated circuit devices, which are connected and fixed on a printed wiring member (for example, a printed wiring board) 63 slightly larger than twice the chip size by, for example, a flip chip method.

The printed wiring member is housed in the case 641, 642 of the package, and the connection terminals and the connection terminals of the element / connection terminal formation surface on one side of the second chip (or the second set of chip areas) are provided. The connection terminal on the printed wiring member is connected to a relay connection node in the case by, for example, a bonding wire 65, and the relay connection node is electrically connected to, for example, a BGA-shaped external terminal formed on the bottom surface of the package. It is connected to the.

<Plural Embodiments of System Board> The above-described semiconductor integrated circuit is used as a system board of a device (for example, a computer and a temporary data storage device therearound) incorporating the semiconductor integrated circuit device according to any of the above embodiments. If a system board on which a plurality of circuit devices are mounted is used, when a memory is formed as a functional circuit, a medium capacity and a large capacity can be realized at relatively low cost, and the integration degree and the size of the system board can be improved. Can be realized.

A plurality of embodiments of such a system board will be described below.

FIG. 7 is a perspective view schematically showing a first embodiment of the system board of the present invention.

In this system board, the semiconductor integrated circuit device 71 of the first embodiment is provided on a printed wiring board 70 in two rows and two rows.
The so-called multi-chip module is mounted in a state where a total of four are arranged in a row. In this case, when a memory is formed as a functional circuit in each chip area, a medium capacity can be realized at relatively low cost, and the degree of integration and miniaturization of the system substrate can be realized.

FIG. 8 is a plan view schematically showing a second embodiment of the system board of the present invention.

In this system board, the semiconductor integrated circuit device 81 of the first embodiment is provided on a printed wiring board 80 in two rows and two rows.
A total of four are mounted in a row, and a logic-type semiconductor integrated circuit device 82 and a plurality of capacitors 83 are mounted on the same substrate 80. in this case,
When a memory is formed as a functional circuit in each chip area, a medium capacity can be realized at relatively low cost, and the degree of integration and miniaturization of a system substrate can be realized.

FIG. 9 is a plan view schematically showing a third embodiment of the system board of the present invention.

This system board is mounted on a printed wiring board 90 in a state where a total of four semiconductor integrated circuit devices 91 according to the second or third embodiment are arranged in two rows and two columns. Further, a logic type semiconductor integrated circuit device 92 and a plurality of capacitors 93 are mounted on the same printed wiring board 90. In this case, when a memory is formed as a functional circuit in each chip area, a medium capacity to a large capacity can be realized relatively inexpensively, and an improvement in the degree of integration of the system substrate and a reduction in size can be realized relatively easily. be able to.

FIG. 10 is a sectional view schematically showing a fourth embodiment of the system board of the present invention.

This system board is mounted in a state where a plurality of semiconductor integrated circuit devices 101 according to any of the above embodiments are arranged on both sides of a printed wiring board 100, respectively.
Further, a logic type semiconductor integrated circuit device 102 is mounted on one surface of the same printed wiring board 100. In this case, when a memory is formed as a functional circuit in each chip area, a large-capacity memory card can be realized relatively inexpensively, and further improvement and miniaturization of the integration degree of the system board can be realized. it can.

FIG. 11 is a perspective view schematically showing a fifth embodiment of the system board of the present invention.

This system board is mounted on a printed wiring board 110 in a state where a plurality of semiconductor integrated circuit devices 111 according to the first embodiment or its modified example are arranged. A logic type semiconductor integrated circuit device 112, a CPU 113 and a plurality of capacitors 114 are mounted thereon. In this case, when a memory is formed as a functional circuit in each chip area, a large-capacity memory card can be realized relatively inexpensively, and further improvement and miniaturization of the integration degree of the system board can be realized. it can.

FIG. 12 is a perspective view schematically showing a sixth embodiment of the system board of the present invention.

This system board is mounted on a printed wiring board 120 by the semiconductor integrated circuit device 121 according to the second embodiment.
Are mounted in a state where a plurality of are arranged, and a logic type semiconductor integrated circuit device 122 is mounted on one surface of the same printed wiring board 120. In this case, when a memory is formed as a functional circuit in each chip area, a large-capacity memory card can be realized relatively inexpensively, and further improvement and miniaturization of the integration degree of the system board can be realized. it can.

[0119]

As described above, according to the semiconductor integrated circuit device of the present invention, even when at least two back surfaces of a semiconductor integrated circuit chip on which a plurality of functional circuits are mixed are bonded, heat radiation characteristics can be improved. It is possible to reduce adverse effects on electrical characteristics and to stabilize operation particularly at low voltage operation.

Further, according to the semiconductor integrated circuit device of the present invention, when applied to a chip having a memory function,
The memory capacity can be easily increased relatively inexpensively.

Further, according to the system substrate of the present invention, it is possible to improve the degree of integration and reduce the size, and when a chip having a memory function is used, a medium capacity and a large capacity can be manufactured at a relatively low cost. Can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing a first embodiment of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a sectional view showing a modification of the semiconductor integrated circuit device shown in FIG. 1;

FIG. 3 is a sectional view schematically showing a second embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 4 is a sectional view schematically showing a third embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 5 is a sectional view showing a modification of the semiconductor integrated circuit device shown in FIG. 4;

FIG. 6 is a sectional view schematically showing a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 7 is a perspective view schematically showing a first embodiment of the system board of the present invention.

FIG. 8 is a plan view schematically showing a second embodiment of the system board of the present invention.

FIG. 9 is a plan view schematically showing a third embodiment of the system board of the present invention.

FIG. 10 is a sectional view schematically showing a fourth embodiment of the system board of the present invention.

FIG. 11 is a perspective view schematically showing a fifth embodiment of the system board of the present invention.

FIG. 12 is a perspective view schematically showing a sixth embodiment of the system board of the present invention.

FIG. 13 is a sectional view schematically showing an example of a chip area on a wafer before dividing each chip from the wafer according to the first embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 14 is a sectional view showing a well 22-2 in FIG. 13 taken out therefrom;

FIG. 15 is a sectional view showing the well 22-3 in FIG. 13 taken out therefrom;

FIG. 16 is a sectional view showing the well 22-4 in FIG. 13 taken out therefrom;

FIG. 17 is a sectional view showing the well 22-5 in FIG. 13 taken out therefrom;

FIG. 18 is a sectional view showing an example of a conventional CMOS structure.

[Explanation of symbols]

 11: first chip, 12: second chip, 13: conductive adhesive, 14: printed wiring member, 15: sealing resin, 16: bonding wire.

Claims (13)

[Claims] A first well region of a second conductivity type having a conductivity type opposite to the first conductivity type, which is selectively formed in an island shape on a surface layer portion of a semiconductor substrate of the first conductivity type; A second of the first conductivity type selectively formed in an island shape in the first well region.
And two chips including a functional circuit formed in at least the second well region and a conductive adhesive in which the back surfaces of the two chips are bonded to each other. Semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, further comprising a printed wiring member on which the chips stacked by bonding are assembled. 3. A semiconductor device comprising: two chips each having a plurality of chip regions adjacent to each other via an inter-chip separation region; and a conductive adhesive bonding the back surfaces of the two chips to each other, In each of the chip regions, a plurality of first well regions of a second conductivity type, which is a conductivity type opposite to the first conductivity type, are selectively formed in an island shape on a surface layer portion of a semiconductor substrate of the first conductivity type, A semiconductor integrated circuit, wherein a second well region of a first conductivity type is selectively formed in an island shape in the first well region, and at least a functional circuit is formed in the second well region. Circuit device. 4. The semiconductor integrated circuit device according to claim 3, further comprising a printed wiring member on which the chips stacked by bonding are assembled. 5. The chip laminated by bonding has a connection terminal on one side connected and fixed on the printed wiring member by a flip chip method, and a connection terminal on the other side connected to the printed wiring by a bonding wire. The printed wiring member is connected to a connection terminal on the member, the printed wiring member is provided with an external terminal on a surface opposite to a surface on which the chip is assembled, and the chip, printed wiring member, 5. The semiconductor integrated circuit device according to claim 2, wherein the bonding wire is sealed with an insulating resin. 6. The printed wiring member is mounted with one chip laminated by the bonding, the size of the printed wiring member is slightly larger than the size of the chip, and has a chip size package. Claim 2,
6. The semiconductor integrated circuit device according to any one of items 4 and 5. 7. The semiconductor integrated circuit device according to claim 2, wherein the printed wiring member has a plurality of chips stacked by the bonding. 8. A first well region of a second conductivity type having a conductivity type opposite to the first conductivity type, which is selectively formed in an island shape on a surface layer portion of a semiconductor substrate of the first conductivity type, A second of the first conductivity type selectively formed in an island shape in the first well region.
First, second, and third chips each having at least one chip region including a functional circuit formed in the well region and at least the second well region, and back surfaces of the first and second chips, respectively. A conductive adhesive adhesively bonded to each other, a flip chip connecting portion that connects and fixes one side of the first chip and one side of the third chip laminated by the bonding by a flip chip method, A printed wiring member on which the other surface side of the chip is assembled, and the printed wiring member and a chip having a three-layer laminated structure assembled thereon are housed, and the other surface side of the second chip and on the printed wiring member A package having a plurality of external terminals that are selectively and electrically connected to the connection terminals of the semiconductor integrated circuit device. 9. The functional circuit formed in each of the plurality of first well regions is a functional circuit having a different function from each other, and includes a functional circuit that fluctuates a potential of a semiconductor chip. Item 9. The semiconductor integrated circuit device according to any one of Items 1 to 8. 10. The functional circuit formed in each of the plurality of first well regions includes a nonvolatile memory circuit, an analog circuit, a digital circuit, a digital / analog conversion circuit, a static memory circuit, and a dynamic memory circuit. The semiconductor integrated circuit device according to claim 1, wherein at least two are included. 11. The device according to claim 1, wherein the functional circuits formed in the plurality of first well regions respectively constitute a memory circuit as a whole. Semiconductor integrated circuit device. 12. A semiconductor device comprising: a plurality of semiconductor integrated circuit devices according to claim 1; and a printed wiring board on which the plurality of semiconductor integrated circuit devices are mounted on one side. A system board characterized by the above-mentioned. 13. A semiconductor device comprising: the plurality of semiconductor integrated circuit devices according to claim 1; and a printed wiring board having the plurality of semiconductor integrated circuit devices mounted on both surfaces. Characteristic system board.