JPH09245442A - Method and device for recording digital signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a recording capacity and to improve reliability by using a plurality of error correction codes at the time of recording/reproduction of a digital signal and digital data. SOLUTION: A part of input packet data is supplied to a control circuit 104 at the time of recording. In the control circuit 104, the kind of the packet data, the maximum transmission rate, etc., are detected, a recording mode is judged from the results of detection and an operation mode of a recording/ reproduction signal processing circuit 102 and a servo circuit 106 is set. In the case of an ordinary digital signal such as a digital compressed video signal, according to this constitution, a double error correction code of C1 and C2 is used and, in the case of digital data, a triple error correction code of C1, C2 and C3 is used. In accordance with the recording mode, the number of packets to be recorded on one track is judged and recording signals are generated and recorded on a tape 111 by a rotary head 100.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording method and apparatus for recording and reproducing digital signals,
In particular, the present invention relates to a recording method and apparatus for recording / reproducing a digital signal on a magnetic tape by using a rotary head.

[0002]

2. Description of the Related Art A digital signal recording apparatus for recording a digital compressed video signal on a magnetic tape using a rotary head is disclosed in Japanese Patent Laid-Open No. 174496/1993.

[0003]

However, no consideration is given to improvement in reliability during recording.

An object of the present invention is to provide a digital signal recording method and apparatus which can also be used for recording and reproducing digital data which requires reliability.

[0005]

The object is to add a synchronizing signal, a control signal and an error detection and correction code to a digital signal to form a block format, and a predetermined number of the blocks form a digital signal recording area of one track. A digital signal recording method and apparatus for recording on a magnetic recording medium by adding a first error detection / correction code in units of n tracks of the digital signal and in units of 1 block of the digital signal and the first error detection / correction code. A first recording mode in which a second error detection / correction code is added and recorded, and a third error detection / correction code is added in units of n tracks of the digital signal, and the digital signal and the third error detection / correction code 1 are added. The fourth error detection and correction code is added in track units, and the digital signal, the third error detection and correction code, and the fourth error detection and correction code Tsu using the clock unit of the second can be achieved by having a second recording mode for recording by adding an error detection correction code.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a digital signal recording / reproducing apparatus of the present invention. FIG. 1 shows an apparatus that is used for both recording and reproduction. Of course, the same applies when recording and reproduction are independent. 100 is a rotary head, 101 is a capstan, 10
Reference numeral 2 is a recording / reproducing signal processing circuit for generating a recording signal for recording and demodulating a reproducing signal for reproducing, 104 is a control circuit for controlling a recording / reproducing mode etc., for example, a control circuit such as a microprocessor, and 105 is a rotary head. A timing generation circuit that generates a timing signal that serves as a reference for rotation of 100,
Reference numeral 106 is a servo circuit for controlling the feeding speed of the rotary head and tape, 107 is an input / output circuit for inputting a recording signal or outputting a reproduction signal, 109 is a timing control circuit for controlling the timing at the time of recording, and 110 is a reference clock. An oscillating circuit for generation, 111 is a tape, and 112 is a recording / reproducing circuit for analog video signals. The rotary head 100 includes a digital signal recording / reproducing head (D +, D-) and an analog signal recording / reproducing head (A +, A-).

At the time of recording, packet-type recording data is input from the input / output terminal 108 at arbitrary time intervals. A part of the packet data input from the input / output terminal 108 is input to the control circuit 104 via the input / output circuit 107. The control circuit 104 detects the type of packet data, the maximum transmission rate, etc. from the information added to the packet data or the information sent separately from the packet data, determines the recording mode based on the detection result, and outputs the recording / reproducing signal. The operation modes of the processing circuit 102 and the servo circuit 106 are set. The input / output circuit 107 detects the packet data to be recorded and outputs it to the recording / reproducing signal processing circuit 102. In the recording / reproducing signal processing circuit 102, the control circuit 1
The number of packets to be recorded on one track is determined according to the recording mode determined in 04, and the error correction code, ID information,
A subcode or the like is generated, and a recording signal is generated and recorded on the tape 111 by the rotary head 100.

At the time of reproduction, first, the reproduction operation is performed in an arbitrary reproduction mode, and the recording / reproduction signal processing circuit 102 detects the ID information. Then, the control circuit 104 determines which mode has been recorded, and the operation mode of the recording / reproduction signal processing circuit 104 and the servo circuit 106 is reset to perform reproduction.
In the recording / reproducing signal processing circuit 104, the synchronizing signal is detected, the error is detected and corrected from the reproducing signal reproduced by the rotary head 100, and the data, subcode, etc. are reproduced and output to the input / output circuit 107. The input / output circuit 107 outputs reproduced data from the input / output terminal 108 based on the timing generated by the timing generation circuit 105.

When recording / reproducing an analog video signal, the analog video signal input from the input terminal 113 is recorded in the tape 111 by the rotary head 100 by the analog recording / reproducing circuit 112 in a predetermined process. At the time of reproduction, the video signal reproduced by the rotary head 100 is output from the output terminal 114 after the analog recording / reproducing circuit 112 performs a predetermined process. In this case, although not shown, the servo circuit 106 is controlled based on the frame period of the analog video signal. Although the analog recording head is provided independently in FIG. 1, it may be combined with the digital recording head.
You may provide independently.

The digital signal recording / reproducing apparatus of this embodiment is capable of recording / reproducing both a digital compressed video signal and digital data such as a computer program.

First, the case of recording and reproducing a digital compressed video signal will be described.

FIG. 2 shows a recording pattern on the tape 111. Reference numeral 10 is a + azimuth track, and 11 is a −azimuth track, which are recorded and reproduced by a + azimuth head (D +) and a −azimuth head (D−), respectively.

FIG. 3 shows a recording pattern of one track. Reference numeral 3 is a subcode recording area for recording subcodes such as time information and program information, 7 is a data recording area for recording a digital compressed video signal, 2 and 6 are preambles of respective recording areas, and 4 and 13 are respective preambles. Postamble of recording area, 5 is a gap between recording areas,
1 and 14 are margins at the track end. By providing a postamble, a preamble, and a gap in each recording area in this way, it is possible to perform dubbing on each area independently. Of course, recording area 7
A digital signal other than the digital compressed video signal and the audio signal may be recorded in. Further, a digital compressed audio signal may be recorded in the area 7 together with the digital compressed video signal.

FIG. 4 shows a block configuration of each area. FIG.
(A) is a block configuration of the data recording area 7. Two
0 is a synchronization signal, 21 is ID information, 22 is data, and 23 is a first error detection and correction parity (C1 parity).
It is. For example, the sync signal 20 has 2 bytes, and the ID information 2
1 is 3 bytes, data 22 is 99 bytes, parity 23
Is composed of 8 bytes, and one block is composed of 112 bytes. FIG. 4B shows the block configuration of the subcode recording area 3. In the block of the subcode recording area, the synchronization signal 20 and the ID information 21 are shown in FIG.
The data 22 is composed of 19 bytes and the parity 23 is composed of 4 bytes, and one block is composed of 28 bytes which is ¼ of the block of FIG. 4A. In this way, the number of bytes in one block is also set to be an integer ratio, and the synchronization signal 11 and the ID information 12 are further used in all areas.
By making the configurations of (1) to be the same, it is possible to perform processing such as generation of blocks at the time of recording and detection of synchronization signals and ID information at the time of recording by the same circuit. The synchronization signal 11
May have a different value in each area so that the area can be identified only by the synchronization signal.

FIG. 5 shows the structure of the ID information 21. 24
Is a sequence number, 25 is a track address, and 26 is 1
Block address in track, 27 is sequence number 24, track address 25 and block address 26
This is a parity for detecting an error of. The block address 26 is an address for identifying a block in each recording area. For example, in the data recording area 7,
335, 0 to 13 in the additional information recording area 3, and 0 to 15 in the subcode recording area 12. Track address 2
Reference numeral 5 is an address for identifying a track. For example, 6 tracks can be identified by changing the address in units of 1 track or 2 tracks and setting it to 0-5 or 0-2. Sequence number 24 is
For example, 72 tracks can be identified by changing them in units of 6 tracks identified by the track address 25 and setting 0 to 11. If the track address is synchronized with the period of a second error correction code described later, and the sequence number is synchronized with the recording period of variable speed reproduction data described later, processing at the time of recording and identification at the time of reproduction can be facilitated. Can be.

FIG. 6 shows the structure of one track of data in the data recording area 7. Note that the synchronization signal 20 and the ID information 21 are omitted. The data recording area 7 is composed of, for example, 336 blocks, and the first 306
Data 41 is recorded in the block, and a second error correction code (C2 parity) 43 is recorded in the next 30 blocks.

The C2 parity 43, for example, divides data of 306 blocks × 6 tracks into 18 in units of 6 tracks, and 10 blocks of C2 in each 102 blocks.
Add parity. For example, a Reed-Solomon code may be used as the error correction code.

The 99-byte data of each block is composed of a 3-byte header 44 and 96-byte data 41. FIG. 7 shows the structure of the header 44 of the data recording area 7. The header 44 is composed of format information 31, additional information 32, and block information 33.

FIG. 8 shows the structure of the format information 31. The format information 31 is information on a recording format, and for example, one information is composed of 12 bytes of 6 bytes. By multiplex-recording this information a plurality of times, the detection capability at the time of reproduction is improved. The data of 6 blocks includes, for example, the size of 1 block, the number of programs to be recorded, the number of rotations of the rotary head, the error correction code system, the recording mode, the format of the data to be recorded, and the like.

The recording mode (ID1) defines, for example, the maximum recording capacity. In this embodiment, when two-channel recording is performed at a rotation speed of 1800 rpm using a four-head rotary head, data of approximately 25 Mbps can be recorded. Here, if recording is performed once every two times, the recording capacity becomes about 12.5 Mbps. If the recording is performed once every four times, the recording capacity becomes about 6.25 Mbps. In this case, the tape feed speed is 1/2 or 1 /
When set to 4, the track patterns on the tape are almost the same. Similarly, the maximum recording capacity is 1/25 of Mbps.
It can be n. At the time of recording, the transmission rate of the recording data is identified, the optimum recording mode is set, and recording is performed. Then, the mode in which the recording is performed is recorded in the format information 31. For example, "1" at 25 Mbps, "2" at 12.5 Mbps, 6.25
For Mbps, it is set to "3" or the like.

The format (ID2) of the data to be recorded defines, for example, the packet length of the packet to be recorded. By controlling the amount of data to be recorded on one track in packet units and recording the recorded number, it is possible to cope with an arbitrary transmission rate. It should be noted that the control may be performed for each track or a plurality of tracks. Also, by recording the packet length, it is possible to correspond to a packet of an arbitrary length.

At the time of reproduction, the format information 31 may be detected to identify the recording mode and the like, and the reproduction processing circuit may be set to that mode for reproduction.

FIG. 9 shows the structure of the additional information 32. The additional information 32 is composed of, for example, six bytes of six bytes, which constitute one piece of information. The first one byte is an item code indicating the type of information, and the remaining five bytes are data. Can be recorded.
For example, information such as the recording time and the type of the recording signal are recorded. Here, detailed information on the variable speed reproduction data may be recorded in association with the format information 31.

FIG. 10 shows a data recording area 4 for a digital compressed video signal transmitted in a packet format of 188 bytes.
1 is an example of the configuration of a block when recording data in No. 1; In this case, 4-byte time information 25 is added to make 192 bytes, and one packet is recorded in two blocks. By recording one packet of data in correspondence with two blocks, that is, one code sequence of C1, when uncorrection in a block unit occurs due to a burst error due to dropout on a tape or the like, the error is transmitted in units of transmission. Does not extend over a plurality of packets.

FIG. 11 shows a block configuration when the length of the packet 71 is 140 bytes. At this time, 2
The packets 71 are recorded in three blocks. When there is only one packet, one packet may be arranged in two blocks as shown in FIG. That is,
One packet may be arranged in 1.5 blocks, and the remaining 0.5 blocks may be dummy data.

FIG. 13 shows another example of the structure of the packet shown in FIG. 10, FIG. 11 or FIG. The packet is, for example, 3
The byte time information 25 and the control information 72 related to the 1-byte packet are constituted by 188-byte or 140-byte packet data 71. If the number of packet data 71 is smaller than this, for example, 130 bytes, dummy data is added or recorded.
Alternatively, the area of the control information may be increased.

The time information 25 is information on the time when the packet was transmitted. That is, the time when a packet (the beginning of) is transmitted or the interval between packets is counted by the reference clock, the count value is recorded together with the packet data, and the interval between packets is reproduced based on that information during reproduction. By setting, it is possible to output data in the same form as when it was transmitted.

Thus, the ratio of the number of bytes in one packet to the number of bytes in the recording area of one block is a simple integer ratio n: m.
If m packets are recorded in n blocks as shown by, it is possible to efficiently record even if the packet length is different from the recording area of one block. Furthermore, when the number of packets is not in units of m, for example, in the case of m ′ (m ′ <m), the m ′ packets are arranged and recorded in m ′ × n / m blocks. By doing so, n and m that can be efficiently recorded are
Each of the values is smaller than the number of bytes of one packet and the number of bytes of the recording area of one block, and if it can be represented by an integer of 10 or less, the processing can be facilitated.
It should be noted that even if the length of one packet is longer than the recording area of one block (n> m), the same recording can be performed.
Further, if the information such as the time information has the same format even for packets of different lengths, the recording / reproducing process becomes easy. The format information 31 may be used for identification when the packet lengths are different.

FIG. 14 shows the structure of the block information 33. The block information 33 is information for identifying data in block units. The data information 74 is information for identifying the type of data recorded in this block. For example, 0 may be set in a block in which normal packet data is recorded, 1 in a block in which valid data is not recorded, and 2 in a block in which variable speed reproduction data is recorded.

Block number 75 stores packet data 2
This is information for identifying the order of blocks when recorded in units of blocks or three blocks. For example, when recording is performed in units of 2 blocks, 0 to 1, and when recording is performed in units of 3 blocks, 0 to 2. Furthermore, if the end of the recording area can be identified by these pieces of information, processing at the time of reproduction becomes easy.

Next, the case of recording and reproducing digital data will be described.

When recording / reproducing digital data, the recording / reproducing apparatus can be shared by using the same format as that for recording the digital compressed video signal. However, in the case of recording digital data,
Data reliability is important.

FIG. 15 shows a data structure of one track in the data recording area 7 when recording digital data. In FIG. 15, the reliability of data is improved by adding the C3 parity 45. The configuration of the parity is, for example, the same for the C1 parity 23 as in FIG. 6, and the C2 parity 43 is 30 for each track unit.
The data of 6 blocks is divided into 3 and 10 blocks of C2 parity are added to each 102 blocks. Also,
The C3 parity 45 divides the data of 276 blocks × 6 tracks into 18 units in units of 6 tracks, and divides each into 92 units.
Add 10 blocks of C3 parity to the block. As described above, the C1 and C2 parity numbers are made the same as in the case of FIG. 6, only the data distribution method of C2 is changed, and the C3 parity number and the C2 parity number are made the same so that the digital compressed video signal is obtained. The error correction circuit can be shared with the case of recording. Further, by setting the C3 parity 45 to be the same 6-track unit as the C2 parity of FIG. 6, the memory capacity used for data distribution can be made the same, and the memory control method can also be made the same. .

Of course, when the problem of reliability is not so important, the same configuration of FIG. 6 as the case of recording a digital compressed video signal may be used.

When recording digital data, 6
Recording and reproduction may be performed with the track as one unit. In the case of digital data, the time information 25
Is unnecessary. Thus, for example, 2 blocks of 19
Two bytes may be recorded as one packet 71.
In this case, a maximum of 828 packets (1589
(76 bytes) can be recorded. If the packet data is recorded sequentially from the beginning of 6 tracks and the information indicating whether or not valid data is recorded in the block information 33, it is possible to cope with the case where the number of recorded data is small. Of course, it is not necessary to record from the beginning.

In the case of recording digital data, if a part of the format information 31, for example, a value different from that at the time of recording the digital compressed video signal is set as the recording mode, it can be identified at the time of reproduction. .

FIG. 16 shows the configuration of the recording / reproducing signal processing circuit 102. A storage circuit 400 stores data,
Reference numeral 401 is an error correction circuit for adding C2 and C3 parities and error correction at the time of reproduction, 411 is a generation circuit for generating C1 parity, 412 is a recording circuit for generating a recording signal, and 413 is a reproduction for detecting a reproduction signal. A circuit, 414 is an error correction circuit that performs C1 error correction during reproduction, 410 is a signal conversion circuit that converts the timing of a recording / reproduction signal, 4
Reference numeral 03 is a control circuit for controlling the operation timing.

FIG. 17 shows the configuration of the input / output circuit 107. Reference numeral 300 is a packet detection circuit, 301 is a time information confirmation circuit, 302 is an output control circuit, 303 and 309 are buffers, and 304 is a time control circuit.

The specific operation during recording / reproduction will be described below with reference to FIGS. 16 and 17.

First, the case of recording and reproducing a digital compressed video signal will be described. When recording / reproducing a digital compressed video signal, only the + azimuth head (D +) and the −azimuth head (D−) arranged adjacent to one of the rotary heads 100 are used.

At the time of recording, the operation timing of the recording / reproducing apparatus is controlled by the timing control circuit 109 based on the rate of the recording data input from the input / output terminal 108, and at the time of reproduction, the clock oscillated by the oscillation circuit 110 is used as the operation reference. To work as. The input / output terminal 10
The transmission rate of packets input / output from 8A is higher than the frequency of the clock generating the time information. For example, the reference clock for time information is 27
MHz, and input / output is performed at 49.152 bps. Further, the same frequency as the reference clock of the recording / reproducing apparatus transmitted by the oscillation circuit 110 is used. As will be described later, this can facilitate the recording / reproducing process.

At the time of recording, data and a synchronous clock are input from the input / output terminals 108A and 108B at the timing shown in FIG. Reference numeral 310 denotes the data of FIG.
If the time information 25 is input without being added, the time information 25 may be added to each packet by the internally generated reference clock.

The input data and synchronous clock are input to the packet detection circuit 300, and the head of the packet is detected by the clock output from the timing generation circuit 105 input from the input terminal 307. The head of the packet may be detected by detecting a blank between the packets and, when data comes after the blank, determining that the data is the head of the packet. Further, by detecting the data number of one packet by the packet detection circuit 300, it is possible to determine the type of packet and whether the packet is normally transmitted. That is, when a packet with a length other than the predetermined packet length (corresponding to the device) is detected, it is determined that the packet is not transmitted normally or data that cannot be recorded is transmitted. The information may be sent to the control circuit 104 to stop the recording.

The packet 71 detected by the packet detection circuit 300 is output via the buffer 309 to the output terminal 305A.
Is output to the input / output terminal 405 of the recording / reproducing signal processing circuit 102. The buffer 309 is for converting the transmission rate of input data. Transmission speed is 50Mbp
In the case of a high speed of about s, the memory circuit 4 remains at the same speed.
Attempting to record 00 requires the use of a very fast storage circuit. On the other hand, as described above, since the average maximum recording rate of the recording / reproducing apparatus is about 25 Mbps,
The storage circuit 400 can be set at a rate corresponding to this maximum recording rate and stored in the storage circuit 400 via a high-speed buffer to reduce the speed of the storage circuit. FIG. 19 shows the input / output timing of the buffer 309. For example, when the storage rate of the storage circuit 400 is 27 Mbps (3.375 bytes / sec), the speed ratio between the input and output of the buffer is about 1:
It becomes 2. In this case, even if the buffer capacity is about 7 packets or more than 7 packets are continuously input at 50 Mbps, it is possible to handle.

In the recording / reproducing signal processing circuit 102, the packet data input from the input / output terminal 405 is stored in the storage circuit 4.
At 00, the packet input during the period corresponding to one track of recording is stored in association with one track. Further, at this time, the block information 33 and the like are added. Storage circuit 400
After adding the C2 parity by the error correction circuit 401, the C1 parity is added by the C1 generation circuit 411, the sync signal 20 and the like are added by the recording / reproducing circuit 412, and the data stored in FIG. Generating and converting the signal 41
Enter 0. FIG. 20 shows the operation of the signal conversion circuit 410 during recording. The signal conversion circuit 410 delays the signal of the + azimuth track by one track among the recording signals input in the order of + azimuth and −azimuth. Then, the + azimuth and −azimuth recording signals are simultaneously output from the input / output terminal 407 to the + azimuth head (D +) and −azimuth head (D−) arranged adjacent to one of the rotary heads 100, and the magnetic tape. Record at 111.
That is, signals of two tracks are recorded once per one rotation of the rotary head.

The control signal or the like sent in addition to the packet is output from the output terminal 306A to the control circuit 104, and the type of the packet is discriminated and the recording mode is determined. In addition, the time information 25 added to each packet
Is output to the time information confirmation circuit 301.

In the time information confirmation circuit 301, the time information 2
5 and the interval between packets counted by the clock input from the input terminal 307 is compared. When there is a difference between the two, the control signal output from the output terminal 308
The timing control circuit 109 controls the recording processing timing and the number of rotations of the rotary head 100 so as to correct the deviation. By recording the recording processing timing and the rotational speed of the rotary head 100 in synchronization with the time information 25,
At the time of reproduction, reproduction and packet output may be controlled by the reference clock of the recording / reproducing apparatus transmitted from the oscillation circuit 110. That is, the number of packets to be reproduced and the number of packets to be output match even if no special synchronization processing is performed during reproduction.

During reproduction, the reproduction signals of the + azimuth head (D +) and −azimuth head (D−) input from the input / output terminal 407 of the recording / reproduction signal processing circuit 102 are input to the signal conversion circuit 410. In the signal conversion circuit 410, as shown in FIG. 21, the reproduction signal of the −azimuth track is delayed by one track to generate a reproduction signal in which the + azimuth signal and the −azimuth signal are arranged in order to generate the reproduction circuit 413.
To enter. The reproduction circuit 413 detects the sync signal and detects the data in the reproduction signal. Then, the error correction circuit 414 performs error correction using the C1 parity and then stores it in the storage circuit 400. After that, the error correction circuit 401 performs error correction using C2 parity, and outputs it to the input / output circuit 107 from the input / output terminal 405.

The output from the input / output terminal 405 identifies the reproduced block information 33, the flag added at the time of error correction, etc., reproduces without error, outputs only valid packets, and becomes uncorrectable. Packets are not output. Thus, output of abnormal data can be prevented.

In the input / output circuit 107, the input terminal 306B
The output control circuit 302 is controlled in the output mode by the control signal from the control circuit 104, which is further input, and the regenerated packet data is output in synchronization with the reference clock transmitted from the oscillation circuit 110. The packet input from the input terminal 305B is stored in the buffer 303, for example, 27 Mbps.
It is stored at (3.375 bytes / sec). By the time information 25 and the clock input from the input terminal 307, the packet from the buffer 303, for example, 49.15.
When read at 2 bps, the timing shown in FIG.
Output at the same timing as when the recording data was input. Thus, in a device for receiving and processing a reproduced packet, such as a digital compressed video signal decoding device or another digital signal recording / reproducing device, recording and reproduction are performed in the same process as when the signal before recording is directly processed. Can be processed.

Next, the case of recording and reproducing digital data will be described. When recording and reproducing digital data, a + azimuth head (D +) and a −azimuth head (D) arranged adjacent to one of the rotary heads 100.
(-) Performs recording / reproduction, and the + azimuth head (D +) and -azimuth head (D-) arranged adjacent to the other perform simultaneous reproduction at the time of recording. That is, the reliability of the recording is ensured by reproducing the recorded data immediately afterward and confirming whether or not the data is correctly recorded.

During recording, for example, data and a synchronous clock are input from the input / output terminals 108A and 108B at the timing shown in FIG. When recording digital data, it is not necessary to manage the time information of the data. Therefore, the packet data 310 may be a packet of only data to which time information is not added, and it is not necessary to manage the input interval. For example, although not shown, a data request signal is exchanged with a digital data output device, and if the data is within the maximum recording capacity, the data output from the digital data output device is sequentially input and exceeds it. In such a case, the output of the digital data from the output device may be made to wait. Of course, the data need not be in packet form.

The input data and the synchronous clock are input to the packet detection circuit 300, and the clock output from the timing generation circuit 105 input from the input terminal 307 is used to detect the start of the packet as in the case of the digital compressed video signal. Detection is done.

The packet 71 detected by the packet detection circuit 300 is output via the buffer 309 to the output terminal 305A.
Is output to the input / output terminal 405 of the recording / reproducing signal processing circuit 102. In the case of digital data, data is often input in bursts. Therefore, for example, the capacity of the buffer 309 is increased to 6 tracks or several times thereof, and after the data is collected for 6 tracks, the data is output to the recording / reproducing signal processing circuit 102 at a constant speed to be recorded, whereby the data is efficiently recorded. Can be recorded.

In the recording / reproducing signal processing circuit 102, the packet data input from the input / output terminal 405 is stored in the storage circuit 4.
At 00, the packet input during the period corresponding to one track of recording is stored in association with one track. Further, at this time, the block information 33 and the like are added. Storage circuit 400
The data stored in C is generated by the error correction circuit 401 after adding C3 and C2 parity, and then C1 is generated by the C1 generation circuit 411.
1 parity is added, and the sync signal 2 is applied to the recording / reproducing circuit 412.
0 is added to generate the recording signal of FIG. 2 and input it to the signal conversion circuit 410. Then, the same signal conversion as in FIG. 20 is performed, and the rotary head 1 is simultaneously input from the input / output terminal 407.
00 + azimuth head (D
+) And -azimuth head (D-) for recording on the magnetic tape 111. That is, signals of two tracks are recorded once per one rotation of the rotary head.

Further, when recording digital data, as shown in FIG. 22, the other + azimuth head (D +) is used.
And-simultaneously reproduce the data recorded by the azimuth head (D-). Then, the reproduced data is converted by the signal conversion circuit 410 in the same manner as in FIG.
After the synchronization signal is detected, the error correction circuit 41
In step 4, error detection is performed using C1 parity. The result of error detection is output from the input / output terminal 409 to the control circuit 104.
To check whether the recording was done correctly.
For example, when the error is equal to or larger than the allowable value, the data may be recorded again at a different position.

In this way, the error correction circuit 41 is also used during recording.
By detecting an error using C1 parity in 4, it is possible to secure the reliability of recording without providing a dedicated circuit.

At the time of reproduction, it is performed in the same manner as the reproduction of the digital compressed video signal. That is, the same + azimuth head (D +) and −azimuth head (D
Reproduction is performed by (-), and the reproduction signals of the + azimuth head (D +) and the-azimuth head (D-) input from the input / output terminal 407 of the recording / reproduction signal processing circuit 102 are
As shown in FIG. 21, the signal conversion circuit 410 delays the reproduction signal of the −azimuth track by one track to generate a reproduction signal in which the + azimuth signal and the −azimuth signal are arranged in order and inputs the reproduction signal to the reproduction circuit 413. . In the reproduction circuit 413,
The sync signal is detected and the data in the reproduced signal is detected. Then, the error correction circuit 414 performs error correction using the C1 parity and then stores it in the storage circuit 400. After that, the error correction circuit 401 performs error correction using the C2 parity and the C3 parity, and outputs from the input / output terminal 405 to the input / output circuit 107.

The output from the input / output terminal 405 identifies the reproduced block information 33 and the flag added at the time of error correction. In the case of digital data reproduction, all data must be reproduced without error. Therefore, when a packet that cannot be corrected occurs, that portion may be reproduced again, for example.

In the input / output circuit 107, the input terminal 306B
The output control circuit 302 is controlled in the output mode by the control signal from the control circuit 104, which is further input, and the reproduced packet data is output. When reproducing digital data, it is not necessary to manage time information. Therefore,
The data in the buffer 303 may be output in a certain unit. For example, the capacity of the buffer may be increased to 6 tracks or several times thereof and output may be performed in units of 6 tracks.

As described above, by using the signal conversion circuit, the recording / reproducing circuit of one system can perform recording / reproducing of two channels and simultaneous reproducing at the time of recording. Note that C
The generation of the 2 parity and the C 3 parity and the error correction are performed in the same circuit, but of course, independent circuits may be performed.

FIG. 23 shows another embodiment of the digital signal recording / reproducing apparatus of the present invention. In FIG. 23, for recording / reproducing a digital signal, + azimuth heads (D +) and −azimuth heads (D−) that are attached to face each other and a second + azimuth head (adjacent to the −azimuth heads ( D +) three azimuth heads are used.

FIG. 24 shows the configuration of the recording / reproducing signal processing circuit 102 of the digital signal recording / reproducing apparatus of FIG.

In this case, the digital compressed video signal and the digital data can be recorded and reproduced without using the signal conversion circuit. Recording and reproduction of the digital compressed video signal are performed using the opposite + azimuth head (D +) and -azimuth head (D-). Recording and reproduction of digital data is performed by only one + azimuth head as shown in FIG. Then, at the time of recording, as shown in FIG. 26, the signal recorded by the other + azimuth head is reproduced to confirm the recording. In this way, by performing recording and reproduction with one head, the maximum recording amount is halved, but the signal conversion circuit can be omitted. In this case, the recording circuit 412 and the reproducing circuit 413 are controlled so that they operate in only one half of one rotation of the rotary head.

FIG. 27 shows an example of the connection between the digital signal recording / reproducing apparatus of FIG. 1 and the digital broadcast receiver. 20
Reference numeral 0 is a digital signal recording device of FIG. 1, 201 is a digital broadcast receiver, 202 is an antenna, and 207 is a monitor. 203 is a tuner, 204 is a selection circuit, 20
5 is a decoding circuit, and 206 is an interface circuit.
After the digital broadcast signal received by the antenna 202 is demodulated by the tuner 203, the selection circuit 204 selects a required digital compressed video signal. The selected digital compressed video signal is decoded into a normal video signal by the decoding circuit 205 and output to the monitor 207. Further, when a process such as scrambling is performed on the received signal, the decoding circuit 205 cancels it and then performs a decoding process.

At the time of normal reception, the digital broadcast receiver 201 demodulates a digital compressed signal from the received signal, decodes this digital compressed signal into a normal video signal and audio signal, and displays it on a monitor such as a television. Output. This digital compressed signal is usually transmitted in packet format. The packet transmission rate changes depending on the content of the broadcast. The packet transmission interval also changes according to the encoding process. The decoder decodes the video signal by reproducing the frame frequency at the time of encoding based on the information contained in the packet format data and the interval at which the packet is sent.

At the time of recording from the digital broadcast receiver 201, the interface circuit 206 adds time information indicating a packet transmission interval to a packet-type digital compressed signal, converts the packet into a format shown in FIG. 16, and outputs the converted signal.
Then, it is input to the digital signal recording device 200 from the input / output terminal 108 and recorded. If the data is transmitted without adding the time information, the recording / reproducing device 108 may add the time information for recording.

Further, the digital signal recording / reproducing apparatus 200
The digital compressed video signal and the like reproduced in step 1 is output from the input / output terminal 108 to the interface circuit 206 at the same intervals as during recording using time information. The interface circuit 206 performs the same processing as the normal reception on the input signal, and outputs it to the decoding circuit 206. Then, the video and audio signals are decoded and the monitor 2
07.

FIG. 28 shows an example of connection between the digital signal recording / reproducing apparatus of FIG. 1 and a computer. In FIG. 28,
The computer 208 corresponds to the digital broadcast receiver 201. That is, the digital compressed video signal received by the digital broadcast receiver 201 is decoded by the decoding circuit 205 built in the computer 208 and output to the monitor 207.

When the digital compressed video signal is recorded in the digital signal recording / reproducing apparatus 200, the digital compressed video signal output from the digital broadcast receiver 201 is recorded in the digital signal recording / reproducing apparatus 200 via the computer 208. . Further, the digital compressed video signal reproduced by the digital signal recording / reproducing apparatus 200 is
The monitor 20 is decoded by the decoding circuit of the computer 208.
7 is output.

Next, when the digital data stored in the disk 209 or the like is recorded, the computer 2
The data to be recorded is output to the digital signal recording / reproducing device from 08. In addition, the digital signal recording / reproducing device 200
The digital data reproduced by
And is stored in the disk 209 or the like.

The input / output circuit of FIG. 17 can be similarly applied to the input / output circuits of other devices such as the digital broadcast receiver 201.

In the embodiment, the input and output terminals are used together, but the input and output terminals may be provided separately.

[0075]

According to the present invention, when a normal digital signal such as a digital compressed video signal is recorded / reproduced, C1 is used.
C1 and C are used when recording and reproducing digital data for which reliability is required by using the double error correction code of C and C2.
By using the triple error correction code of 2 and C3,
The recording capacity can be increased in normal recording / reproducing of digital signals, and the reliability can be improved in recording / reproducing of digital data. Since C2 is added in units of 6 tracks even in normal recording / reproduction of digital signals, sufficient reliability is ensured for dropout on the tape. Further, C3 at the time of recording digital data is also added in units of 6 tracks, and the parity numbers are made the same, so that the error correction circuit and the storage circuit can be shared.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a digital signal recording / reproducing apparatus.

FIG. 2 is a diagram of a recording pattern on a tape.

FIG. 3 is a recording pattern diagram of one track.

FIG. 4 is a block diagram of each area.

FIG. 5 is a configuration diagram of ID information 21.

FIG. 6 is a configuration diagram of data of one track in a data recording area 7.

7 is a configuration diagram of a header 44 of the data recording area 7. FIG.

FIG. 8 is a configuration diagram of format information 31.

FIG. 9 is a configuration diagram of a configuration of additional information 32;

FIG. 10 is a block diagram of a block for recording a digital compressed video signal transmitted in a packet format of 188 bytes in a data recording area 41.

FIG. 11 is a configuration diagram of a block when the length of a packet 71 is 140 bytes.

FIG. 12 is another configuration diagram of a block when the length of the packet 71 is 140 bytes.

FIG. 13 is another configuration diagram of the packet of FIG. 10, FIG. 11, or FIG.

14 is a configuration diagram of block information 33. FIG.

FIG. 15 is a configuration diagram of data of one track in a data recording area 7 when recording digital data.

16 is a configuration diagram of a recording / reproducing signal processing circuit 102. FIG.

FIG. 17 is a configuration diagram of an input / output circuit 107.

FIG. 18 is a timing diagram of input / output signals.

FIG. 19 is a timing chart of input / output of the buffer 309.

FIG. 20 is an operation timing chart of the signal conversion circuit 410 during recording.

FIG. 21 is an operation timing chart of the signal conversion circuit 410 during reproduction.

FIG. 22 is a signal conversion circuit 41 for recording digital data.
FIG. 7 is an operation timing chart of 0.

FIG. 23 is another configuration diagram of the digital signal recording / reproducing apparatus.

24 is a configuration diagram of a recording / reproducing signal processing circuit 102 of the digital signal recording / reproducing apparatus of FIG.

25 is a recording pattern diagram on the tape in the case of the digital signal recording / reproducing apparatus of FIG.

FIG. 26 is a recording / reproducing timing chart in the case of the digital signal recording / reproducing apparatus of FIG.

FIG. 27 is a connection diagram between a digital signal recording / reproducing device and a digital broadcast receiver.

FIG. 28 is a connection diagram between a digital signal recording / reproducing device and a computer.

[Explanation of symbols]

7 ... data recording area, 10 ... + azimuth track, 11
...- azimuth track, 20 ... synchronization signal, 21 ... ID information, 22 ... data, 23 ... C1 parity, 25 ... time information, 31 ... format information, 32 ... additional information, 33 ...
Block information, 41 ... Data, 43 ... C2 parity, 4
4 ... Header, 45 ... C3 parity, 71 ... Packet, 7
2 ... control information, 74 ... data information, 75 ... block information, 100 ... rotary head, 101 ... capstan, 10
2 ... Recording / reproducing signal processing circuit, 104 ... Control circuit, 105
... Timing generation circuit, 106 ... Servo circuit, 107 ...
Input / output circuit, 109 ... Timing control circuit, 110 ... Oscillation circuit, 112 ... Analog signal recording / reproducing circuit, 300 ...
Packet detection circuit, 301 ... Time information confirmation circuit, 302
... Output control circuit, 303 ... Buffer, 304 ... Time control circuit, 309 ... Buffer, 310 ... Packet, 400 ...
Storage circuit, 401 ... Error correction circuit, 402 ... Recording / reproducing circuit, 403 ... Data control circuit, 410 ... Signal conversion circuit,
411 ... C1 parity generation circuit, 412 ... Recording circuit, 4
13 ... Reproduction circuit, 414 ... Error correction circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location H04N 5/94 H04N 5/92 H

Claims (8)

[Claims] 1. A sync signal, a control signal and an error detection / correction code are added to a digital signal to form a block format, and a predetermined number of said blocks form a digital signal recording area of one track for recording on a magnetic recording medium. In the digital signal recording method, a first error detection / correction code is added in track units (n is an integer greater than 1) of the digital signal, and the digital signal and the first error detection / correction code are in block units. In the first recording mode in which the second error detection and correction code is added for recording, and the third error detection and correction code is added in units of n tracks of the digital signal, the digital signal and the third error detection are added. A fourth error detection / correction code is added for each track of the correction code, and the digital signal, the third error detection / correction code, and the fourth error detection / correction code are added. Digital signal recording method and having a second recording mode for recording by adding a second error detection and correction code in one block units of ECC codes. 2. The digital signal recording method according to claim 1, wherein the first error detection and correction code and the fourth error detection and correction code are error detection and correction codes having the same number of parities. 3. The digital signal recording according to claim 1, wherein the third error detection and correction code and the fourth error detection and correction code are error detection and correction codes having the same number of parities. Method. 4. The digital signal recording method according to claim 1, wherein the n tracks are 6 tracks. 5. The digital signal recording according to claim 1, wherein the control signal includes information for identifying which one of the first recording mode and the second recording mode the recording is performed. Method. 6. A sync signal, a control signal and an error detection and correction code are added to a digital signal to form a block format, and a predetermined number of said blocks form a digital signal recording area of one track for recording on a magnetic recording medium. In the digital recording apparatus, the first error detection and correction code is added in units of n (n is an integer larger than 1) tracks of the digital signal in the first recording mode, and the digital signal of the digital signal is added in the second recording mode. Addition of a third error detection and correction code in units of n tracks, and addition of a fourth error detection and correction code in units of one track of the digital signal and the third error detection and correction code Means and a second unit for each block of the digital signal and the first error detection and correction code or the third and fourth error detection and correction codes. Second digital signal recording method characterized by comprising an error detection correction code adding means for adding the detection correction code Ri. 7. The digital signal recording apparatus according to claim 6, wherein the first error detection and correction code and the fourth error detection and correction code are error detection and correction codes having the same number of parities. 8. The digital signal recording according to claim 6, wherein the third error detection and correction code and the fourth error detection and correction code are error detection and correction codes having the same number of parities. apparatus.