JPH0921866A - Multispectrum repeater - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate multiple wave without limiting data for disturbing by arranging a time dividing control circuit, a small capacity memory device, a register, a computing element, and a variable divider and the like. SOLUTION: A variable divider 5 divides a signal of an oscillator 5a of frequency fc by a value outputted from a computing element 4. A pulse signal of the divider 5 is converted into a digital value, and controls a phase shifter 9 with its bit output. As a result, the phase shifter 9 conducts phase modulation (frequency modulation) to a receiving signal inputted from a sending receiving switch 8, and conducts phase modulation corresponding to each functional parameter 2a by time dividing to generate multiple wave. The output of the phase shifter 9 is sent from an antenna 7 through a delay line 10, an amplifier 11, a switch 12, and the sending receiving switch 8. A selecting switch 1a is connected to each functional parameter 2a. Power of corresponding frequency component is controlled every time. The switch 12 is controlled with a time dividing control circuit 1 so as to close by time sending a signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-spectrum repeater which generates a plurality of waves during phase modulation.

A multi-spectrum repeater is applied to technologies such as radio wave interference and others. It is used when interfering with a radar signal or a signal for wireless communication to generate an interfering signal so that the original signal cannot be identified.

In the case of radar, with the recent technological progress,
Specifications that can interfere with radar signals (frequency,
Frequency changes over time, required power, etc.) are limited, and the values of specifications have become different depending on individual radars.

Therefore, there is provided a circuit system in which microwaves are distributed, phase modulation (frequency modulation) is performed using a plurality of phase shifters or mixers, and the microwaves are recombined to generate a plurality of waves. However, the power control for each wave time was not possible.

[0005]

2. Description of the Related Art FIG. 17 is a block diagram of a first conventional example. In the figure, the radar signal input from the antenna 80 is switched between transmission and reception by the transmission / reception switch 81, and the reception signal (microwave) is distributed by the transmission / reception switch 81 for a predetermined time period.
Then, the modulated signal from the switch 88 is transmitted for a certain length of time thereafter, and the operation is repeatedly executed. The distributor 82 distributes the received signal to n as it is,
Each distributed signal is input to each of n phase shifters 83.

On the other hand, each of the phase shifters 83 generates different voltages which can be arbitrarily set from the voltage generator 1 to the voltage generator n (represented by 89), and the respective voltages are provided correspondingly. The V / F converter 90 thus converted converts the voltage into a frequency, and the frequency output from each V / F converter 90 is counted (divided) by the corresponding counter 91 and converted into a digital value. The output of each counter 91 is supplied to the corresponding phase shifter 83 to control the amount of phase shift to perform phase modulation.

Next, the different phase-modulated signals generated from the respective phase shifters 83 are combined again by the combiner 84, and n
A plurality of waves with the converted frequencies are generated. Synthesizer 84
Is delayed by the delay line 85 (delayed until the next transmission cycle), and the output of the delay line 85 is amplified by the amplifier 86,
It is supplied to the switch 88. This switch 88 is output by the pulse oscillator 87 in each transmission cycle, switched to be turned off in the reception cycle, and transmitted from the antenna 80 when the transmission / reception switch 81 is switched to the transmission state at the next transmission timing.

The transmission / reception switch 81 prevents the transmission signal from flowing into the reception side and also prevents the reception signal from flowing into the transmission side. By modulating different frequencies by the plurality of phase shifters 83, it is possible to cause interference by matching any frequency with the frequency of the radio wave (radar signal) to be interfered with.

Next, FIG. 18 is a configuration diagram of the second conventional example. In this configuration as well, a plurality of voltage generators 89 are provided as in the case of the conventional example 1, but the voltage of each voltage generator 89 is input to the corresponding sine wave output V / F converter 93. Each sine wave output V / F converter 93 generates a sine wave having a frequency corresponding to the input voltage, and each output is input to the corresponding mixer 92 provided.
The mixer 92 frequency-modulates the signal distributed from the distributor 82 by the output of the sine wave output V / F converter 93. The output of each mixer 92 is combined by the combiner 84 to generate a plurality of waves, which are input to the delay line 85, and the output thereof is transmitted from the antenna 80 through each circuit similar to the above-mentioned conventional example 1.

[0010]

According to the above-mentioned conventional example 1 and conventional example 2, a plurality of waves having different frequencies are generated at frequencies corresponding to the output of the voltage generator for generating the set voltage, Frequency (phase) depending on the output
The multi-frequency is generated by modulating, and the purpose can be achieved if one of the frequencies is equal to the frequency of the other party to be disturbed.

However, even if there is a frequency that matches the frequency of the other party, if the power of each frequency component is uniform,
There is a problem that the effect of interference cannot be improved.
That is, in the case of a radar signal, if the power of the same frequency component as the reflected signal in the interfering signal is not relatively large with respect to the power of the reflected signal, there is no effect of the interference.

On the other hand, although it is sufficient to increase the power of each frequency signal in the conventional example 1 and the conventional example 2, it is a problem that the scale of the apparatus increases and the cost also increases in order to generate each frequency signal with high power. was there.

As described above, the conventional technique has a problem that it is difficult to control the power for each wave time, and it is difficult to supply the power required for the interference. It is an object of the present invention to provide a multi-spectral repeater which can be generated without limiting the parameters such as frequency, time variation of frequency, required power, etc. for interfering with radar and receiver.

[0014]

FIG. 1 is a block diagram of the first principle of the present invention, FIG. 2 is a block diagram of the second principle of the present invention, and FIG. 3 is a block diagram of the third principle of the present invention. Is a fourth principle configuration diagram of the present invention, FIG. 5 is a fifth principle configuration diagram of the present invention, and FIG. 6 is a sixth principle configuration diagram of the present invention.

In FIG. 1, 1 is a switch 12 and a time division control circuit for switching function parameters (in the small capacity storage device 2) by time division, 1a is a selection switch, 2 is a small capacity storage device, and 2a is a small capacity storage device. Each of the n function parameters 1 to n, 3 stored in 2 is a register, 4 is a calculator, 5 is a variable frequency divider, 5a is an oscillator for generating a pulse of a constant frequency (fc), 6 is a counter, Reference numeral 7 is an antenna (antenna), 8 is a transmission / reception switcher, 9 is a phase shifter, 10 is a delay line for delaying a period from reception to transmission, 11 is an amplifier,
12 is a switch.

In FIG. 2, reference numerals 5 to 12 represent the same circuits as those in FIG. 1, reference numeral 20 represents a time division control circuit,
21 is different digital function data 1 to n
It is a mass storage device storing (21a). In FIG. 3, 6 to 12 represent circuits similar to those in FIGS. 1 and 2, 30 is a time division control circuit, 31 is an analog switch, and 32-1 to 32-n are analog signal function generators 1.
˜n, and 33 is a V / F converter.

In FIG. 4, 1 to 8 and 10 to 12 represent the same circuits as those in FIG. 1, 40 is a sine function generator (indicated by a SIN function generator), and 41 is a mixer.

Further, in FIG. 5, 5-8, 10-12
Represents a circuit similar to the same reference numeral in FIGS.
Reference numerals 0 and 21 represent similar time division control circuits and mass storage devices having the same reference numerals in FIG. 2, and reference numerals 40 and 41 represent sine function generators and mixers having the same reference numerals in FIG.

Further, in FIG. 6, reference numerals 7, 8, 10 to 12 denote the same circuits as those shown in FIGS.
Reference numeral 32-n corresponds to the same symbol in FIG. 3, 30 is a time division control circuit, 31 is an analog switch, and 32-1 to 32.
n is each function generator 1 to n, 41 is a mixer, and 42 is a sine output type V / F converter.

A first principle of the present invention is that a function parameter of a plurality of time functions is selected by time division by a time division control circuit, a frequency of the time function is generated by an arithmetic unit according to the function parameter, and the frequency signal is generated. A plurality of waves are generated by counting and obtaining phase bits and performing frequency modulation on the received signal by time division.

[0021]

In the case of FIG. 1, the signal received from the antenna 7 is input to the phase shifter 9 at the reception timing of the transmission / reception switch 8. On the other hand, the small-capacity storage device 2 stores function parameters (constants used for the function) of the time function ft of a plurality of (n) frequencies. The function parameter is a parameter in a linear function, a quadratic function, etc., and for example, ft = at +
It is the value of a and b when it is set to b. Time division control circuit 1
Controls the selection switch 1a at a programmed time to select one from the n function parameters 2a by time division. The selected function parameter 2a is stored in the register 3. The arithmetic unit 4 generates a function fc / ft using a preset frequency fc for the time function ft corresponding to the function parameter in the register 3. The function value (digital value) generated by the arithmetic unit 4 is set in the variable frequency divider 5.

The variable frequency divider 5 divides the signal of the oscillator 5a having the frequency fc by the value output from the arithmetic unit 4. As a result, the signal of the frequency fc is divided by the value of fc / ft, so that the signal (pulse) of the frequency of the time function ft is generated and the signal output is supplied to the counter 6. The counter 6 converts the frequency signal of the time function ft into a phase bit signal. That is, the number of pulse signals from the variable frequency divider 5 is counted and converted into a digital value, and the bit output is supplied to the phase shifter 9 to control the phase shifter 9.

As a result, the phase shifter 9 performs phase modulation (frequency modulation) on the reception signal input from the transmission / reception switcher 8,
It is possible to generate a plurality of waves by performing phase modulation corresponding to each function parameter 2a by time division. The output of the phase shifter 9 is the delay line 10, the amplifier 11, and the switch 12 as in the conventional case.
And transmitted from the antenna 7 via the transmission / reception switch 8.

Selection switch 1a for each function parameter
The power of the corresponding frequency component is controlled depending on the time when the is connected. The switch 12 is also controlled by the time division control circuit 1 so as to be closed only during the transmission time.

In the case of FIG. 2, function data 1 to function data n are stored in the mass storage device 21. The function data 1 to the function data n store function data (digital value) of fc / ft obtained by dividing the frequency fc by the time function ft of a plurality of (n) frequencies, which corresponds to the passage of time. Since this is data that changes over time, each of the function data 1 to n is composed of a large amount of data. The time division control circuit 20 controls the selection switch 20a at a programmed time to select one from the n pieces of function data 21a by time division. Selected function data 21
When a is sequentially read and supplied to the variable frequency divider 5, the variable frequency divider 5 frequency-divides the frequency signal of the oscillator 5a by the value of the input function data as in FIG. Function f
A signal (pulse) having a frequency of t is generated. This signal is output to the counter 6, and thereafter the same operation as in FIG. 1 is performed.

Next, in the case of FIG. 3, a plurality of function generators 32
-1-32-n generate voltage waveforms corresponding to different time functions ft. The voltage waveforms of the respective function generators may be constant values different from each other, or may be values changing on different straight lines or curves. When the time division control circuit 30 switches the analog switch 31 in a time division manner, the corresponding voltage waveform from the corresponding function generator is V /
It is supplied to the F converter 33. V / F converter 33
Generates a frequency signal of the time function ft corresponding to the input voltage. This frequency signal is counted by the counter 6 and converted into a phase bit signal to control the phase shifter 9.
The phase shifter 9 performs phase modulation (frequency modulation) to generate a plurality of waves.

In the case of FIG. 4, the time division control circuit 1 similar to that of FIG.
a, a plurality of stored data in the small capacity storage device 2 (n
Function parameters 2a of the time function ft of frequency) are selected and sent to the register 3. The arithmetic unit 4 generates a function fc / ft by dividing the frequency fc predetermined by the function parameter 2a in the register 3. The variable frequency divider 5 divides the pulse of the frequency fc of the oscillator 5a by the value output from the arithmetic unit 4 and outputs the signal (pulse) of the time function ft to the counter 6. The counter 6 counts the input signal and converts it into a phase bit signal. When the bit signal (parallel) is supplied to the sine function generator 40, it is converted into a sine waveform corresponding to the phase bit and supplied to the mixer 41. It
The mixer 41 frequency-modulates the received frequency signal with the output of the sine function generator 40 to generate a plurality of waves.

In the case of FIG. 5, the time division control circuit 20 similar to that of FIG. 2 switches the selection switch 20a at programmed time intervals, and the mass storage device 2 similar to that of FIG.
A plurality of (n) function data 21a stored in 1 are sequentially selected and output to the variable frequency divider 5. The variable frequency divider 5 divides the frequency fc of the oscillator 5a by the value of the function fc / ft generated from the variable frequency divider 5 to count the ft by a counter 6
Output to When the phase bit is generated by the counter 6, it is supplied to the sine function generator 40 to generate a sine waveform corresponding to the phase bit, which is supplied to the mixer 41 to perform frequency modulation on the reception frequency signal and generate a plurality of waves. Occur.

In the case of FIG. 6, a time division control circuit 30 similar to that of FIG. 3 switches the analog switch 31 at programmed time intervals, and a function generator 32 similar to that of FIG.
A voltage waveform representing the selected one of the functions -1 to 32-n is output. This voltage waveform is a sine output type V / F
When input to the converter 42, it is converted into a corresponding frequency, and a sine waveform having a frequency representing the time function ft is generated. This is input to the mixer 41 and the received signal is frequency-modulated to generate a plurality of waves.

[0030]

Embodiment FIG. 7 is a block diagram of the first embodiment, and FIG. 8 is a processing flow of the first embodiment. The first embodiment corresponds to the first principle configuration of the present invention shown in FIG.

In FIG. 7, 1 to 12 correspond to respective circuits having the same reference numerals in FIG. 1, 1 is a time division control circuit,
1b is a CPU, 1c is an external register 3, switch (S
W4) Input / output port (I / O port) for outputting data or control signal to 12, 1d timer, 1e program ROM, 1f RAM, 1g external memory interface, 1h bus, 1i external memory A bus between external memory interfaces, 2 is provided as an external memory, and function parameters 1 to 3 (2-1 to 2-
3) A small capacity programmable ROM (Fig. 1)
Corresponding to the small-capacity storage device 2) of the 16-bit serial EEPROM (Electrically
Erasable Programmable ROM) can be used. 3 is a register, 4 is a computing unit, 5 is 1/100 to 1/16
Variable frequency divider that can perform frequency division in the range of 77721, 5
a is a pulse oscillator that generates a pulse of frequency fc, 6 is a binary counting stage composed of 4 stages (1/2, 1/4, 1/8, 1/16 stages), and a 4-bit phase shift The counters 7 to 11 for outputting the bits to the phase shifter 9 have the same names as the same symbols in FIG. The phase shifter 9 uses a 4-bit digital phase shifter. A switch 12 is turned on at the time of transmission and turned off at the time of reception, and is hereinafter referred to as SW4.

In the time division control circuit 1, the selection switch 1a of FIG. 1 selects a function parameter from the programmable ROM 2 by the CPU 1b, and external memory interface 1g, bus 1h, I / O port 1c.
This corresponds to the operation of transferring data to the register 3 via.

In the first embodiment, the program ROM 1e has 3
An example in which three function parameters 1 to 3 are stored is shown, and the program ROM 1e is executed by the CPU 1b of the time division control circuit 1.
Operates according to the program stored in.

The processing flow of the first embodiment shown in FIG. 8 will be described. This processing flow has a main flow from the start to the end, and each branch flow of to is provided in the middle. First, N, T, Tpw, and T1 to T4 representing each variable or constant provided in the RAM 1f are initialized (FIG. 8).
S1). It should be noted that N is a variable that represents the number of multiple waves (N = 1 to 3) and also represents the reception time (N = 4), which is set to 0 at initialization, and T is the time from the start ( ms) and is set to 0 at initialization. Tpw is a variable for counting the time width, T1 is the pulse width of multiple waves 1 (corresponding to function parameter 1), T2 is the pulse width of multiple waves 2 (corresponding to function parameter 2), T3 is multiple waves 3 (function The pulse width (corresponding to parameter 3), T4, is the width of the reception time (the time when transmission is stopped).

In this initialization, the pulse widths of the plural waves 1 to 3 are initially T1 = 30 (m) as shown in the figure.
s), T2 = 20 (ms), T3 = 50 (ms),
The reception time width T4 is set to 100 (ms), and the power of each of the plurality of waves 1 to 3 is variable by changing the values of T1 to T3 as time passes, as described later. The transmission time is T1 + T2 + T3 = 100, and the reception time (T4 = 10
0) and the transmission time alternately occur and are switched by the switch SW4.

Next, T = T + 1 and N = N + 1 are performed, and T =
1, N = 1 (S2 in FIG. 8), and SW4 is turned on (indicating the start of the transmission operation) (S3 of the same). Next, it is determined whether T = 600 (S4 in the same step). If not, it is determined whether T = 1000 (S5 in the same step).
6). In this case, the process shifts to N = 1.

In step S60, the first function parameter 1 is read from the programmable ROM 2 and sent to the register 3 (S60). Next, the variable Tpw representing the time width and the variable T representing the time are incremented by 1 (at step S61).
During this time, the arithmetic unit 4 generates the function 1 using the function parameter 1 as described with reference to FIG.
2), the output is output to the variable frequency divider 5, and the variable frequency divider 5
Then, the pulse of the oscillator 5a is divided by the value set in the arithmetic unit 4, and the output is output to the counter 6.

The counter 6 counts the input pulse and outputs the 4-bit output to the phase shifter 9 as a phase bit. The phase shifter 9 performs phase modulation (frequency modulation) on the signal received from the duplexer according to the phase bit from the counter 6. Function 1 generation time Tpw> T1 (= 3
It is determined whether it has become 0) (S63 in FIG. 8), and when time T1 is exceeded, Tpw is returned to 0 (S64) and the process returns to the main flow and returns to step S2 via S7 to S10.

In this step S2, the variables T and N are updated (+1) so that N = 2. After this, the condition of N = 2 is satisfied in S7, and the process shifts to. In this case, send the second function parameter 2 to register 3 (
S70), and in the following S71 to S73, the function 2 is generated for the period of time T2 (= 20) by the same processing as above, and when it exceeds the time T2, the process returns to the main flow via S74. After that, in the main flow, when N = 3 is updated in step S2, this time, the process shifts to N = 3 in step S8. In this case, the same processing as the above is executed, the third function parameter is sent to the register 3, and the period function 3 of the time T3 (= 50) is generated (S80 to S83). When the generation of the function 3 is completed (when Tpw> 50), Tpw is set to 0.

After this processing, returning to the main flow, T = 101 (updated in the processing of ,, and) and N = 4 in step S2, and thereafter, through steps S3 to S8, to step S9. In the determination as to whether N = 4, the condition is satisfied, and the process proceeds. In this case, switch SW4 (12 in FIG. 7)
Turn off. As a result, transmission of multiple waves is stopped.
Then, it waits until Tpw is sequentially updated and the time (= 100 ms) set in T4 is reached, and when the time comes, the variable N
And Twp are set to 0 and the process returns to the main flow. Then, N is incremented by 1 in step S2. In this case, since the condition of N = 1 is satisfied in step S6, the process is executed in the same manner as described above. After this, N = 2, N
In the same manner as above, the functions 2 and 3 are sequentially generated for the periods of the time width 20 and the time width 50, respectively, corresponding to = 3.

When the functions 1, 2, and 3 are sequentially generated (total of 100 ms) and the operation of stopping for the next 100 ms is repeated three times, the variable T becomes 600. In this case, if it is determined in step S4 whether T = 600, the determination result is YES, and the process proceeds. The process is a process of changing the generation time of each function parameter (representing the power ratio of each function). In this case, T1 = 50, T2
= 30 and T3 = 20 are set.

After that, when returning to the main flow, since N = 1 at this time, the processing through step S6 is executed,
Function 1 occurs during the period T1 (= 50). After this, returning to the main flow, when N = 2, the processing through step S7 is executed, and the function 2 is generated during the period of T2 (= 30). Then, at the next time, N = 3, so the processing through step S8 is executed, and the function 3 becomes T3 (= 2
It occurs during period 0). After this, when N = 4, 100
The period of ms (reception time) is stopped.

The generation time of each function 1 to 3 according to the generation time of each function set by the above processing (100 in total)
When the operation cycle of (ms) and reception time (100 ms) is repeated twice, the variable T becomes 1000. in this case,
In step S5 of the main flow, the process shifts to the process when it is determined that T = 1000. Here again, each function 1
~ 3 occurrence time (power ratio) is changed, in this example T1
= 20, T2 = 10, T3 = 70. After that, returning to the main flow, the function 1 is generated for the time T1 (20) in step S6, and subsequently, when N = 2, the function 2 is changed to T2 (= 1).
0) time, and when N = 3, the function 3 is T3 (= 70)
Occurs for the time. After that, when N = 4, the period of 100 ms is stopped.

When the operation cycle of the generation time and the reception time of the functions 1 to 3 is repeated twice, the variable T becomes 140
Since it exceeds 0, this is detected in step S10 of the main flow and the processing ends.

FIG. 9 is a diagram showing characteristics of a plurality of waves generated by the present invention. Is a diagram showing changes in frequencies (ft) of three plural waves generated with time, B. Represents changes in pulse widths of three plural waves generated corresponding to time, and C.I. Represents the power of each of the multiple waves that changes with time.

FIG. 9A. As shown in, the frequency (ft) of each of the plurality of waves is calculated by using the corresponding function parameters 1 to 3 using the respective function parameters. A. In the above example, the plural waves 1 are functions having a constant frequency, the plural waves 2 are linear linear functions which descend to the lower right, and the plural waves 3 are linear linear functions which rise to the upper right.

These plural waves 1 to 3 are shown in FIG. , Multiple waves 1 are generated for the pulse width of time T1,
A plurality of waves 2 are generated with a pulse width of time T2, a plurality of waves 3 are generated with a pulse width of time T3, and a stop time (reception time) of T4 is provided after that, and the operation is repeated. The plural waves 1 to 3 correspond to the functions 1 to 3 of the first embodiment, and the pulse widths T1 to T3 of the plural waves 1 to 3 are the first three cycles at the time of initial setting in FIG. 8 (processing of S1. ) Each pulse width of 30, 20, 50, the next two cycles are 50, 30,
With each pulse width of 20, the subsequent 2 cycles have each pulse width of 20, 10, 70 set by the processing of FIG. The ratio of the time when these plural waves 1 to 3 exist is the power ratio.

C. of FIG. B of FIG. Represents the electric power divided for each of the plural waves 1 to 3 when the plural waves 1 to 3 occur. In this way, the pulse widths (generation time widths T1 to T3) are made different from each other and changed according to the passage of time, so that it is possible to arbitrarily divide the power for each of the plurality of waves. It can be generated without limiting the power. However, the total of the electric powers of the plural waves 1 to 3 is constant.

FIG. 10 is a block diagram of the second embodiment, and FIG. 11 is a processing flow of the second embodiment. The second embodiment corresponds to the second principle configuration of the present invention shown in FIG. 10, reference numerals 5 to 12, 20, and 21 correspond to the respective circuits having the same reference numerals in FIG. 2, and the variable frequency divider 5 and the counter 6 have the same configuration as in FIG. 7 (embodiment 1). 7 to 12 have the same names and configurations as the circuits with the same reference numerals in FIG.

Reference numeral 20 denotes a time division control circuit, which has an internal 2
0b to 20i correspond to the respective portions of 1b to 1i in FIG. 7,
20b is a CPU, 20c is an input / output port (I / O port), 20d is a timer, 20e is a program ROM,
20f is a RAM, 20g is an external memory interface, 20h is a bus, and 20i is a data bus between the external memory and the external memory interface. Reference numeral 20j, which is not provided in FIG. 7, is a bus (address and control line) for performing control for sequentially reading specified function data (waveform data) from the mass storage device 21 which is an external memory. Reference numeral 21 denotes a mass storage device that stores function data 1 to 3 provided as an external memory,
In the second embodiment, six 1 Mbit EEPROMs are configured.

The mass storage device 21 is a programmable ROM in which the function data 1 to 3 are stored. Specifically, for example, 1 megabit parallel EEPROM (Electrical)
It consists of 6 lyErasable Programmable ROMs. A switch 12 is turned on at the time of transmission and turned off at the time of reception, and is hereinafter referred to as SW4. The selection switch 20a in FIG. 2 selects function data from the mass storage device 21 by the CPU 20b in the time division control circuit 20 and performs read control from the data bus 20j via the external memory interface 20g. This corresponds to the operation of taking out read data from 20i and transferring it to the variable frequency divider 5 via the I / O port 20c.

The second embodiment shows an example in which three pieces of function data 1 to 3 are stored in the mass storage device 21. The CPU 20b of the time division control circuit 20 controls the program ROM 20e.
Operates according to the program stored in.

The processing flow of the second embodiment shown in FIG. 11 is the same as the main flow of the first embodiment (see FIG. 8) and the first embodiment.
And a branch flow indicated by are included.

First, N, T, Tpw, and T1 to T4 representing each variable or constant provided in the RAM 20f are initialized in the same manner as in the first embodiment of FIG. 8 (S1 of FIG. 11). In this case, T1 is the pulse width of multiple waves 1 (corresponding to function data 1), T2 is the pulse width of multiple waves 2 (corresponding to function data 2), and T3 is the pulse width of multiple waves 3 (corresponding to function data 3). , T4 is the width of the reception time (time to suspend the transmission).

Thereafter, the same processing (S1 to S
5) is performed, and when it is determined that N = 1 in step S6, the process proceeds to the process of FIG. Here, first, the variable Tpw representing the time width and the variable T representing the time are respectively incremented by 1 (S60 in FIG. 11), and the mass storage devices 21 to 1
The second function data 1 is sent to the variable frequency divider (5 in FIG. 10) to generate the function 1 (S61 in FIG. 11). Then, it is determined whether the variable Tpw exceeds the set pulse width T1 (S62), and the operations of S60 and S61 are repeated until the variable Tpw exceeds the set pulse width T1. The variable frequency divider 5 divides the pulse from the pulse oscillator 5a according to the function data 1 input from the time division control circuit 20 according to the principle described in FIG. 2 to generate the function 1. Function 1 generation time Tpw> T1
When it becomes, Tpw is returned to 0 (at step S63), and the process returns to the main flow.

After that, the same processing as in FIG.
= 2, when the condition of N = 2 is satisfied in step S7, the processing of FIG. 11 (S70 to S7 of FIG. 11) is performed.
3) is executed. In this case, the second function data 2 is sent to the variable frequency divider 5 for the time width T2 and returns to the main flow. After that, when N = 3 is updated in the main flow, the process proceeds to step S8.
In this case, the same processing as above (S8 in FIG. 11 is performed).
0 to S83) are executed, the third function data 3 is sent to the variable frequency divider 5, and when the period of time T3 has elapsed, Tp
Set w to 0.

After this processing, return to the main flow and N =
When it becomes 4, the process shifts to the process because N = 4 in step S9, and the process similar to that of FIG.
Stop function data generation for the time set in.
After that, the process at time T = 600 is executed, the process at time T = 1000 is executed, and the power ratio is changed by changing the pulse width of each function data in the same manner as described with reference to FIG. Is changed and the process is repeated, and time T = 1
The process ends at 400.

The operation cycle of the generation time and the reception time of each function 1 to 3 generated in the processing flow of the second embodiment of FIG.
This is the same as in FIG. 8 above, and the characteristics of the multiple waves generated in this case are as shown in A. ~ C. Is the same as that shown in FIG.

Next, FIG. 12 is a block diagram of the third embodiment, and FIG. 13 is a processing flow of the third embodiment. The third embodiment is shown in FIG.
This corresponds to the third principle configuration of the present invention shown in FIG. 12, 6 to 12 correspond to respective circuits having the same reference numerals in FIG. 3, the counter 6 has the same configuration as that in FIG. 7 (Embodiment 1), and 7 to 12 have the same reference numerals in FIG. Since each circuit has the same name and configuration, its description is omitted.

Reference numeral 30 denotes a time division control circuit, which has an internal 3
0a to 30g correspond to the respective parts 1b to 1h in FIG. 7,
30a is a CPU, 30b is an input / output port (I / O port) for generating external control signals 31 and 33, 30c is a timer, 30d is a program ROM, 30e is a RAM,
30f is an external memory interface, and 30g is a bus. Reference numeral 31 is an analog switch including switches SW1 to SW3, 32-1 to 32-3 are ramp function generators 1 to 3 and 33 for generating waveforms (analog voltage) of ramp functions having different slopes, respectively, and V / F converters. .

In this third embodiment, three ramp function generators 3 are used.
An example including 2-1 to 32-3 is shown, and the CPU 30a of the time division control circuit 30 operates according to the program stored in the program ROM 30d.

The processing flow of the third embodiment shown in FIG. 13 is shown by a main flow similar to those of the first embodiment (FIG. 8) and the second embodiment (FIG. 11) and contents including the contents specific to the third embodiment. And a branch flow.

First, N, T, Tpw, and T1 to T4, which represent each variable or constant provided in the RAM 30e, are initialized with the same values as in the first embodiment shown in FIG. 8 (S in FIG. 13).
1).

Thereafter, the same processing (S1 to S
5) is performed, and when it is determined that N = 1 in step S6, the process of FIG. 13 is performed. Here, first, the analog switch SW1 is turned on, SW2 and SW3 are turned off (S60 in FIG. 13), and then the variable Tpw representing the time width is set.
And the variable T representing time is set to +1 (S in FIG.
61). As a result, the ramp function generator 32- of FIG.
1 is supplied to the V / F converter 33, and the output of FIG.
A frequency corresponding to the function 1 is generated according to the principle described in 1. and is supplied to the counter 6 (S62 in FIG. 13). When the pulse width becomes Tpw> T1, Tpw is set to 0 (see S6
4) Return to the main flow.

After that, the same processing as in FIG.
= 2, the condition of N = 2 is satisfied in step S7, and the processing of FIG. 13 (S70 to S73 of FIG. 11) is executed. In this case, the analog switch SW2 is turned on, the output of the second ramp function generator 32-2 is output during the pulse width T2, and the function data 2 is generated. This function data 2 is sent to the variable frequency divider 5 for the time width T2 and returns to the main flow.

Next, when N = 3 is updated in the main flow, the process proceeds to step S8.
In this case, the analog switch SW3 is turned on, and 3
The output of the th ramp function generator 32-3 is pulse width T3
And the function 3 is generated. When the period of time T3 has elapsed, Tpw is set to 0. After this process, when the flow returns to the main flow and N = 4, the process shifts to the process because N = 4 in step S9, and is set to T4 by the same processes as those in FIG. 8 and FIG. Generation of function data is stopped for a certain period.

After this, similarly to the description of FIGS. 8 and 11, the process at time T = 600 is executed, the process at time T = 1000 is executed, and the pulse width of each function data is executed. Is changed to change the power ratio and the process is repeated, and ends at time T> 1400.

Although the characteristics of each of the plurality of waves generated in the processing flow of the third embodiment shown in FIG.
The operation cycle of the generation time and the reception time is the same as that of FIG. 9 in the case of FIG. 8 (first embodiment) and FIG. 11 (second embodiment). ~
C. Is the same as the example.

Next, FIG. 14 is a block diagram of the fourth embodiment. The fourth embodiment corresponds to the fourth principle configuration of the present invention shown in FIG. In FIG. 14, 1 to 12, 40 are the same as those in FIG.
1 to 6 and 7 to 12 correspond to the circuits with the same reference numerals, and the description thereof is omitted because they are the same circuits as the reference numerals of the configuration of the first embodiment (FIG. 7). 40 is a sine function generator, RO
It is composed of an M, D / A converter and a differential amplifier circuit (indicated by an OP amplifier), and a sine function is generated according to the values of the four-stage phase bits of the counter 6. Reference numeral 41 is a mixer for mixing the received signal and the frequency signal of the sine function generator 40.

The fourth embodiment shows an example in which three function parameters 1 to 3 stored in the programmable ROM 2 are used, and the CPU 1b of the time division control circuit 1 operates according to the program stored in the program ROM 1e.

The processing flow according to the configuration of FIG. 14 is the same as that of the first embodiment, and operates according to the processing flow shown in FIG. However, in the case of FIG. 14, unlike the configuration of the first embodiment (FIG. 7), by supplying the output of the sine function generator 40 driven by the output of the counter 6 to the mixer 41, the received signal is converted by each function. Modulate. Also in the case of the fourth embodiment, a plurality of waves are generated due to the characteristics similar to those in FIG.

Next, FIG. 15 is a block diagram of the fifth embodiment. The fifth embodiment corresponds to the fifth principle configuration of the present invention shown in FIG. In FIG. 15, 5-8, 10-12, 2
Reference numerals 0, 21, and 41 correspond to the circuits having the same reference numerals in FIG. 5, and reference numerals 5 to 8, 10 to 12, 20, and 21 are circuits similar to the reference numerals in the configuration of the second embodiment (FIG. 10). Description is omitted. Further, 40 and 41 are the sine function generators, and 41 is a mixer for mixing the received signal and the frequency signal of the sine function generator 40, as in the case of the fourth embodiment (FIG. 14).

In the fifth embodiment, three function data 1 to 3 stored in the mass storage device 21 composed of the EEPROM are stored.
3 shows an example using 3 CPU of the time division control circuit 20
20b operates in accordance with the program stored in the program ROM 20e.

The operation according to the configuration of the fifth embodiment of FIG. 15 is the same as that of the second embodiment, and operates according to the processing flow shown in FIG. However, in the case of FIG. 15, unlike the configuration of the second embodiment (FIG. 10), by supplying the output of the sine function generator 40 driven by the output of the counter 6 to the mixer 41, the received signal is converted by each function. Modulate.

Also in the case of the fifth embodiment, a plurality of waves are generated due to the same characteristics as in FIG. Next, FIG. 16 is a configuration diagram of the sixth embodiment. The sixth embodiment corresponds to the sixth principle configuration of the present invention shown in FIG.

In FIG. 16, 7, 8, 10-12, 3
0 to 32, 41 and 42 correspond to the respective circuits having the same reference numerals in FIG. 6, and 7 to 8, 10 to 12 and 30 to 32-2 are the respective reference numerals of the configuration of the third embodiment (FIG. 12). Since the circuit is similar, the description is omitted. Further, 40 and 41 are the mixers, and 42 is a sine (SIN) wave output type V / F converter, as in the case of the fourth embodiment (FIG. 14).

The sixth embodiment is a ramp function generator 32-1.
.. 32-3, the example in which the three function data 1 to 3 generated from .about.32-3 are used, and the CPU 30a of the time division control circuit 30 operates according to the program stored in the program ROM 30d.

The operation according to the configuration of the sixth embodiment of FIG. 16 is the same as that of the third embodiment, and operates according to the processing flow shown in FIG. However, in the case of FIG. 16, unlike the configuration of the third embodiment (FIG. 12), the voltage of the ramp function generators 32-1 to 32-3 output from the analog switch 31 is output by the sine output type V / F converter 42. It is converted into a sine wave frequency signal and input to the mixer 41 for modulation.

In the operations shown in the first to sixth embodiments, three function parameters, function data, function generators, etc. are provided, and three functions are generated. Needless to say, it is possible to provide the same number. Further, the pulse width (T1 to T3) generated by the signal of each function used in the embodiment and the first and second pulse widths
It is clear that the change time and the stop time numerical value and unit can be arbitrarily changed according to the performance of the program or the circuit element and the target signal.

[0080]

According to the present invention, it is possible to realize a multi-spectral repeater that effectively interferes with a radar signal or a signal for wireless communication so that the original signal cannot be discriminated by a radar or a receiver. it can. In particular, since it is possible to generate a plurality of waves without limiting the frequency of the signal, the time change of the frequency, and the specifications of the electric power, it is possible to improve the performance of the device that interferes with the radar or the like.

[Brief description of drawings]

FIG. 1 is a first principle configuration diagram of the present invention.

FIG. 2 is a second principle configuration diagram of the present invention.

FIG. 3 is a third principle configuration diagram of the present invention.

FIG. 4 is a fourth principle configuration diagram of the present invention.

FIG. 5 is a fifth principle configuration diagram of the present invention.

FIG. 6 is a sixth principle configuration diagram of the present invention.

FIG. 7 is a configuration diagram of a first embodiment.

FIG. 8 is a processing flow of the first embodiment.

FIG. 9 is a diagram showing characteristics of a plurality of waves generated by the present invention.

FIG. 10 is a configuration diagram of a second embodiment.

FIG. 11 is a processing flow of the second embodiment.

FIG. 12 is a configuration diagram of a third embodiment.

FIG. 13 is a processing flow of the third embodiment.

FIG. 14 is a configuration diagram of a fourth embodiment.

FIG. 15 is a configuration diagram of a fifth embodiment.

FIG. 16 is a configuration diagram of a sixth embodiment.

FIG. 17 is a configuration diagram of Conventional Example 1.

FIG. 18 is a configuration diagram of Conventional Example 2.

[Explanation of symbols]

 1 time division control circuit 1a selection switch 2 small capacity storage device 2a function parameters 1 to n 3 register 4 arithmetic unit 5 variable frequency divider 5a oscillator 6 counter 7 antenna (antenna) 8 transmission / reception switch 9 phase shifter 10 delay line 11 Amplifier 12 switch

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hideaki Yonekura 1-18-32A Bldg. 1-18-32A Fuchinobe, Sagamihara City, Kanagawa Prefecture 105 (72) Inventor Jun 1-18-32D Fuchinobe Bldg. Sagamihara City, Kanagawa Prefecture 301 (72) Inventor Shigeru Fujisawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Keito Kondo 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (6)

[Claims] 1. A multi-spectrum repeater for modulating a received signal by a plurality of waves and transmitting the modulated signal,
A small-capacity storage device that stores a plurality of function parameters corresponding to a time function (ft) of a plurality of frequencies with a phase shifter that receives a received signal and performs phase modulation, and a time ratio that specifies the plurality of function parameters. The time-division control circuit that selectively switches between and outputs the output function parameter, and the output function parameter is input, and the calculation is performed using the value representing the time function (ft) and the constant frequency (fc), and the specific function (fc / ft ) Is generated, and a variable frequency divider that inputs a signal of a constant frequency (fc) and divides it by the specific function from the arithmetic unit, and outputs the output signal of the variable frequency divider to a phase bit. A multi-spectrum repeater characterized by converting to a signal and controlling the phase shifter. 2. A multi-spectrum repeater that performs transmission by modulating a received signal with a plurality of waves,
A mass storage device that includes a phase shifter that receives a received signal and performs phase modulation, that stores a plurality of function data representing time function (ft) values of a plurality of frequencies, and a time that specifies the plurality of function data. The variable frequency divider includes a time division control circuit that selectively switches and outputs a ratio, and a variable frequency divider that inputs a signal of a constant frequency and performs frequency division based on the function data that is selectively output. The multi-spectrum repeater characterized by converting the output signal of 1 to a phase bit signal and controlling the phase shifter. 3. A multi-spectrum repeater that performs transmission by modulating a received signal with a plurality of waves,
Equipped with a phase shifter that receives the received signal and performs phase modulation, a plurality of function generators that generate an analog voltage of a time function (ft) of a plurality of frequencies, and a time ratio that specifies the plurality of function generators. And a voltage / frequency converter for converting the voltage of the function generator selectively output to a frequency, the output signal of the voltage / frequency converter being A multi-spectrum repeater characterized by converting to a phase bit signal and controlling the phase shifter. 4. The mixer according to claim 1, comprising a mixer for performing phase modulation instead of the phase shifter to which a received signal is input,
A multi-spectral repeater, characterized in that a sine function generator for generating a sine wave having a frequency corresponding to the phase bit signal is provided, and an output of the sine function generator is input to the mixer. 5. The mixer according to claim 2, comprising a mixer for performing phase modulation instead of the phase shifter to which a received signal is input,
A multi-spectral repeater, characterized in that a sine function generator for generating a sine wave having a frequency corresponding to the phase bit signal is provided, and an output of the sine function generator is input to the mixer. 6. The frequency converter according to claim 3, further comprising a mixer that outputs a transmission signal instead of the phase shifter to which a reception signal is input, the frequency corresponding to the voltage of the function generator that is selectively output. A multi-spectrum repeater characterized by comprising a sine wave output type voltage / frequency converter for generating the sine wave, and inputting the output of the sine wave output type voltage / frequency converter to the mixer.