JP3134078B2 - Multi-spectrum repeater - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multispectral repeater for generating a plurality of waves during phase modulation.

[0002] Multi-spectrum repeaters are applied to techniques such as radio wave interference and others. It is used when a radar signal, a radio communication signal, or the like is disturbed to generate a disturbing signal so that the original signal cannot be identified.

[0003] In the case of radar, along with recent technological advances,
Specifications that can interfere with the radar signal (frequency,
The time variation of the frequency, the required power, etc.) are limited, and the values of the specifications differ depending on the individual radar.

For this reason, a circuit system has been provided which distributes microwaves, applies phase modulation (frequency modulation) using a plurality of phase shifters or mixers, and combines them again to generate a plurality of waves. However, power control over the time of each wave could not be performed.

[0005]

2. Description of the Related Art FIG. 17 is a block diagram of a first conventional example. In the figure, the transmission / reception switching of the radar signal input from the antenna 80 is performed by the transmission / reception switching device 81, and the reception signal (microwave) is distributed by the transmission / reception switching device 81 for a predetermined time length.
, And transmits the modulated signal from the switch 88 for a certain period of time thereafter, and repeats the operation. The distributor 82 divides the received signal into n signals as it is,
Each distributed signal is input to each of the n phase shifters 83.

On the other hand, each phase shifter 83 generates a different voltage which can be set arbitrarily from a voltage generator 1 to a voltage generator n (represented by 89), and the respective voltages are provided correspondingly. The V / F converter 90 converts the voltage into a frequency, and the frequency output from each V / F converter 90 is counted (divided) by a corresponding counter 91 and converted into a digital value. The output of each counter 91 is supplied to a corresponding phase shifter 83 to control the amount of phase shift to perform phase modulation.

Next, the signals subjected to different phase modulation generated from each phase shifter 83 are combined again by a combiner 84, and n
A plurality of waves with the converted frequencies are generated. Synthesizer 84
Is delayed (delayed until the next transmission cycle) by the delay line 85, and the output of the delay line 85 is amplified by the amplifier 86.
The signal is supplied to the switch 88. This switch 88 is output by the pulse oscillator 87 at each transmission cycle and is switched off at the reception cycle, and is transmitted from the antenna 80 when the transmission / reception switch 81 is switched to the transmission state at the next transmission timing.

The transmission / reception switch 81 prevents the transmission signal from flowing to the reception side and also prevents the reception signal from flowing to the transmission side. By performing modulation of different frequencies by the plurality of phase shifters 83, it is possible to cause interference by matching any of the frequencies with the frequency of a radio wave (radar signal) to be interrupted.

Next, FIG. 18 is a configuration diagram of a second conventional example. In this configuration, a plurality of voltage generators 89 are provided as in the first conventional example, but the voltage of each voltage generator 89 is input to the corresponding sine wave output V / F converter 93. Each sine wave output V / F converter 93 generates a sine wave having a frequency corresponding to the input voltage, and inputs each output to a mixer 92 provided correspondingly.
The mixer 92 modulates the frequency of the signal distributed from the distributor 82 by the output of the sine wave output V / F converter 93. The outputs of the mixers 92 are combined by the combiner 84 to generate a plurality of waves, which are input to the delay line 85, and the outputs of which are transmitted from the antenna 80 via the same circuits as in the first conventional example.

[0010]

According to the above-mentioned conventional examples 1 and 2, a plurality of waves having different frequencies are respectively generated at a frequency corresponding to the output of a voltage generator for generating a set voltage. Frequency (phase) by its output
Is modulated to generate multiple frequencies, and the object can be achieved if one of the frequencies coincides with the frequency of the other party to be disturbed.

However, even if there is a frequency that matches the frequency of the other party, if the power of each frequency component is uniform,
There is a problem that the effect of interference cannot be improved.
That is, in the case of a radar signal, there is no interference effect unless the power of the same frequency component as that of the reflected signal in the interference signal is larger than the power of the reflected signal to some extent.

On the other hand, it is only necessary to increase the power of each frequency signal of the conventional example 1 and the conventional example 2. However, in order to generate each frequency signal with high power, there is a problem in that the scale of the apparatus increases and the cost increases. was there.

As described above, in the conventional technique, there is a problem that it is difficult to supply electric power required to cause interference because power control with respect to time of each wave cannot be performed. SUMMARY OF THE INVENTION It is an object of the present invention to provide a multi-spectrum repeater that generates without limiting the frequency, time change of frequency, required power, and the like for interfering with a radar or a receiver.

[0014]

FIG. 1 is a diagram showing a first principle of the present invention, FIG. 2 is a diagram showing a second principle of the present invention, FIG. 3 is a diagram showing a third principle of the present invention, FIG. Is a fourth principle configuration diagram of the present invention, FIG. 5 is a fifth principle configuration diagram of the present invention, and FIG. 6 is a sixth principle configuration diagram of the present invention.

In FIG. 1, reference numeral 1 denotes a time division control circuit for switching a switch 12 and a function parameter (in the small capacity storage device 2) by time division, 1a a selection switch, 2 a small capacity storage device, and 2a a small capacity storage device. N function parameters 1 to n and 3 stored in 2 are registers, 4 is an arithmetic unit, 5 is a variable frequency divider, 5a is an oscillator for generating a pulse of a constant frequency (fc), 6 is a counter, 7 is an antenna (antenna), 8 is a transmission / reception switch, 9 is a phase shifter, 10 is a delay line for delaying a period from reception to transmission, 11 is an amplifier,
12 is a switch.

In FIG. 2, reference numerals 5 to 12 denote circuits similar to the same reference numerals in FIG. 1, reference numeral 20 denotes a time division control circuit,
Reference numeral 21 denotes different digital function data 1 to n
This is a large-capacity storage device storing (21a). In FIG. 3, reference numerals 6 to 12 denote circuits similar to the same reference numerals in FIGS. 1 and 2, reference numeral 30 denotes a time division control circuit, reference numeral 31 denotes an analog switch, and reference numerals 32-1 to 32-n denote function generators 1 for analog signals.
To n, and 33 is a V / F converter.

In FIG. 4, reference numerals 1 to 8, 10 to 12 denote circuits similar to the same reference numerals in FIG. 1, 40 denotes a sine function generator (indicated by a SIN function generator), and 41 denotes a mixer.

In FIG. 5, 5-8, 10-12
Represents the same circuit as the same reference numeral in FIGS.
Reference numerals 0 and 21 denote the same time division control circuits and mass storage devices having the same reference numerals in FIG. 2, and reference numerals 40 and 41 denote sine function generators and mixers having the same reference numerals in FIG.

Further, in FIG. 6, reference numerals 7, 8, 10 to 12 denote circuits similar to the same reference numerals in FIGS.
32-n corresponds to the same reference numeral in FIG. 3, 30 is a time division control circuit, 31 is an analog switch, 32-1 to 32-32.
n denotes each of the function generators 1 to n, 41 denotes a mixer, and 42 denotes a sine output type V / F converter.

According to a first principle of the present invention, a plurality of function parameters of a time function are selected by time division by a time division control circuit, a frequency of a time function is generated by an arithmetic unit based on the function parameters, and the frequency signal is generated. A plurality of waves are generated by counting and obtaining phase bits and performing frequency modulation on the received signal by time division.

[0021]

In the case of FIG. 1, a signal received from the antenna 7 is input to the phase shifter 9 at the timing of reception of the transmission / reception switch 8. On the other hand, function parameters (constants used for the function) of the time function ft of a plurality (n) of frequencies are stored in the small-capacity storage device 2. The function parameter is a parameter in a linear function, a quadratic function, or the like. For example, ft = at +
These are the values of a and b when b is used. Time division control circuit 1
Controls the selection switch 1a at a programmed time to select one from the n function parameters 2a one by one in a time division manner. The selected function parameter 2a is stored in the register 3. The arithmetic unit 4 generates a function fc / ft for the time function ft corresponding to the function parameter in the register 3 by using a preset frequency fc. The function value (digital value) generated by the arithmetic unit 4 is set in the variable frequency divider 5.

The variable frequency divider 5 divides the frequency of the signal of the oscillator 5 a having the frequency fc by the value output from the arithmetic unit 4. As a result, the signal of the frequency fc is divided by the value of fc / ft, so that a signal (pulse) of the frequency of the time function ft is generated, and the signal output is supplied to the counter 6. The counter 6 converts a signal having a frequency of the time function ft into a phase bit signal. That is, the number of pulse signals from the variable frequency divider 5 is counted and converted into a digital value, and the bit output is supplied to the phase shifter 9 to control the phase shifter 9.

As a result, the phase shifter 9 performs phase modulation (frequency modulation) on the reception signal input from the transmission / reception switch 8, and
A plurality of waves can be generated by performing phase modulation corresponding to each function parameter 2a by time division. The output of the phase shifter 9 is a delay line 10, an amplifier 11, a switch 12
And transmitted from the antenna 7 via the transmission / reception switch 8.

Selection switch 1a for each function parameter
Is connected, the power of the corresponding frequency component is controlled. Note that the switch 12 is also controlled by the time division control circuit 1 so as to be closed only for the transmission time.

Next, in the case of FIG. 2, function data 1 to function data n are stored in the mass storage device 21. The function data 1 to n store function data (digital values) of fc / ft obtained by dividing the frequency fc by the time function ft of a plurality of (n) frequencies, and correspond to the passage of time. Therefore, each of the function data 1 to n is composed of a large amount of data. The time division control circuit 20 controls the selection switch 20a at the programmed time and selects one from the n pieces of function data 21a one by one in time division. Selected function data 21
a are sequentially read and supplied to the variable frequency divider 5, the variable frequency divider 5 divides the frequency signal of the oscillator 5a by the value of the input function data in the same manner as in FIG. Function f
A signal (pulse) having a frequency of t is generated. This signal is output to the counter 6, and the same operation as in FIG. 1 is performed thereafter.

Next, in the case of FIG.
-1 to 32-n generate voltage waveforms corresponding to different time functions ft. Note that the voltage waveform of each function generator may be a constant value different from each other, or a value changing along a different straight line or curve. When the analog switch 31 is switched in a time division manner, the time division control circuit 30 changes the corresponding voltage waveform from the corresponding function generator to V / V.
It is supplied to the F converter 33. V / F converter 33
Generates a frequency signal having a time function ft corresponding to the input voltage. This frequency signal is counted by the counter 6 and converted into a phase bit signal to control the phase shifter 9.
A plurality of waves are generated by performing phase modulation (frequency modulation) by the phase shifter 9.

In the case of FIG. 4, a time division control circuit 1 similar to that of FIG.
a, a plurality (n) stored in the small-capacity storage device 2
The function parameter 2a of the time function ft of the frequency is selected and sent to the register 3. The arithmetic unit 4 generates a function fc / ft obtained by dividing the predetermined frequency fc by the function parameter 2a in the register 3. The variable frequency divider 5 divides the frequency of the pulse of the oscillator 5 a by the value output from the calculator 4, and outputs a signal (pulse) of the time function ft to the counter 6. The counter 6 counts the input signal and converts it into a phase bit signal. When the bit signal (parallel) is supplied to the sine function generator 40, it is converted into a sine waveform corresponding to the phase bit and supplied to the mixer 41. You.
The mixer 41 generates a plurality of waves by performing frequency modulation on the received frequency signal with the output of the sine function generator 40.

In the case of FIG. 5, the time division control circuit 20 similar to that of FIG. 2 switches the selection switch 20a at the programmed time interval, and the mass storage device 2 similar to that of FIG.
A plurality (n) of pieces of function data 21a stored in 1 are sequentially selected and output to the variable frequency divider 5. The variable frequency divider 5 divides the frequency fc of the oscillator 5a by a value of a function fc / ft generated from the variable frequency divider 5 to convert ft into a counter 6
Output to When the counter 6 generates a phase bit, it is supplied to a sine function generator 40 to generate a sine waveform corresponding to the phase bit. The sine waveform is supplied to a mixer 41 and frequency-modulates a received frequency signal to convert a plurality of waves. appear.

In the case of FIG. 6, a time division control circuit 30 similar to that of FIG. 3 switches an analog switch 31 at programmed time intervals, and a function generator 32 similar to that of FIG.
A voltage waveform representing one selected function from -1 to 32-n is output. This voltage waveform is a sine output type V / F
When input to the converter 42, it is converted to a corresponding frequency, and a sine waveform having a frequency representing the time function ft is generated. This is input to the mixer 41 to perform frequency modulation on the received signal to generate a plurality of waves.

[0030]

FIG. 7 is a block diagram of the first embodiment, and FIG. 8 is a processing flow of the first embodiment. The first embodiment corresponds to the first principle configuration of the present invention shown in FIG.

In FIG. 7, 1 to 12 correspond to the circuits having the same reference numerals in FIG. 1, 1 is a time division control circuit,
1b is a CPU, 1c is an external register 3, a switch (S
W4) An input / output port (I / O port) for outputting data or control signals to 12, 1d is a timer, 1e is a program ROM, 1f is a RAM, 1g is an external memory interface, 1h is a bus, and 1i is an external memory. A bus 2 between the external memory interfaces is provided as an external memory, and function parameters 1 to 3 (2-1 to 2-
3) is stored in a small-capacity programmable ROM (FIG. 1).
, Specifically, for example, a 16-Kbit serial EEPROM (Electrically).
Erasable Programmable ROM) can be used. 3 is a register, 4 is a computing unit, 5 is 1/100 to 1/16
Variable frequency divider that can divide frequency within the range of 77721, 5
a is a pulse oscillator for generating a pulse of frequency fc, 6 is a binary counting stage composed of four stages (each stage of 1/2, 1/4, 1/8, 1/16), and a 4-bit phase shifter. Counters for outputting bits to the phase shifter 9 and 7 to 11 have the same names as the same reference numerals in FIG. The phase shifter 9 uses a 4-bit digital phase shifter. Reference numeral 12 denotes a switch which is turned on at the time of transmission and turned off at the time of reception.

In the time division control circuit 1, the selection switch 1a selects a function parameter from the programmable ROM 2 by the CPU 1b in the time division control circuit 1 and selects an external memory interface 1g, a bus 1h, and an I / O port 1c.
Through the data transfer operation to the register 3.

In the first embodiment, three programs are stored in the program ROM 1e.
Shows an example in which three function parameters 1 to 3 are stored, and the CPU 1b of the time division control circuit 1 controls the program ROM 1e.
It operates according to the program stored in.

The processing flow of the first embodiment shown in FIG. 8 will be described. In this processing flow, a main flow is from the start to the end, and each of the branch flows is provided in the middle. First, N, T, Tpw, T1 to T4 representing each variable or constant provided in the RAM 1f are initialized (FIG. 8).
S1). Note that N is a variable indicating the number of multiple waves (N = 1 to 3) and the reception time (N = 4), and is set to 0 at initialization, and T is the time from the start (N = 4). ms) and is set to 0 at initialization. Tpw is a variable for counting the time width, T1 is the pulse width of plural waves 1 (corresponding to function parameter 1), T2 is the pulse width of plural waves 2 (corresponding to function parameter 2), and T3 is plural waves 3 (function The pulse width of T3 (corresponding to parameter 3) is the width of the reception time (time during which transmission is suspended).

In this initialization, the pulse width of the plurality of waves 1 to 3 is initially T1 = 30 (m) as shown in FIG.
s), T2 = 20 (ms), T3 = 50 (ms),
The reception time width T4 is set to 100 (ms), and the power of each of the multiple waves 1 to 3 is variable by changing the values of T1 to T3 with the passage of time as described later. The transmission time is T1 + T2 + T3 = 100 and the reception time (T4 = 10
0) and the transmission time occur alternately, and are switched by the switch SW4.

Next, T = T + 1, N = N + 1, and T =
1, N = 1 (S2 in FIG. 8), and SW4 is turned on (indicating the start of transmission operation) (S3). Next, it is determined whether T = 600 (S4), if not, it is determined whether T = 1000 (S5), and if not, it is determined whether N = 1 (S4).
6). In this case, the processing shifts to processing for N = 1.

First, the first function parameter 1 is read from the programmable ROM 2 and sent to the register 3 (S60). Next, a variable Tpw indicating the time width and a variable T indicating the time are incremented by 1 (S61).
During this time, the arithmetic unit 4 generates the function 1 using the function parameter 1 as described with reference to FIG.
2), and outputs the output to the variable frequency divider 5;
Then, the pulse of the oscillator 5a is frequency-divided by the value set in the arithmetic unit 4, and the output is output to the counter 6.

The counter 6 counts input pulses and outputs a 4-bit output to the phase shifter 9 as a phase bit. The phase shifter 9 performs phase modulation (frequency modulation) on the signal received from the transmission / reception switch according to the phase bit from the counter 6. The occurrence time of function 1 is Tpw> T1 (= 3
0) (S63 in FIG. 8), and when the time T1 is exceeded, Tpw is returned to 0 (S64), the process returns to the main flow, and returns to step S2 via S7 to S10.

In step S2, the variables T and N are updated (+1) so that N = 2. Thereafter, in S7, the condition of N = 2 is satisfied, and the routine goes to the processing of (2). In this case, the second function parameter 2 is sent to the register 3 (
S70), and thereafter in S71 to S73, the function 2 is generated for the period of time T2 (= 20) by the same processing as described above, and when the time exceeds the time T2, the process returns to the main flow via S74. Thereafter, in the main flow, when N = 3 is updated in step S2, the process proceeds to step S8 in which N = 3. In this case, the same processing as described above is executed, and the third function parameter is sent to the register 3 to generate the period function 3 of the time T3 (= 50) (S80 to S83). When the generation of the function 3 ends (when Tpw> 50), Tpw is set to 0.

After returning to the main flow after this processing, T = 101 (updated in the and steps) and N = 4 in step S2, and the processing proceeds to steps S9 to S9 through steps S3 to S8. In the determination of whether or not N = 4, the processing shifts to the processing because the condition is satisfied. In this case, the switch SW4 (12 in FIG. 7)
Turn off. Thereby, transmission of a plurality of waves is stopped.
Then, it waits until Tpw is sequentially updated to reach the time set in T4 (= 100 ms).
And Twp are set to 0, and the process returns to the main flow. Thereafter, N is incremented by one in step S2. In this case, since the condition of N = 1 is satisfied in step S6, the processing is executed in the same manner as described above. Then, N = 2, N
According to the processing of (3), the functions (2) and (3) are sequentially generated only for the periods of the time width 20 and the time width 50, respectively.

When the functions 1, 2, and 3 are sequentially generated (total 100 ms), and the operation for stopping the next 100 ms is repeated three times, the variable T becomes 600. In this case, it is determined that T = 600 in step S4, and the process is determined to be yes. In the processing, the generation time of each function parameter (representing the power ratio of each function) is changed. In this case, T1 = 50, T2
= 30, T3 = 20.

Thereafter, when returning to the main flow, since N = 1 at this time, the processing through step S6 is executed, and
Function 1 occurs during T1 (= 50). Thereafter, returning to the main flow, when N = 2, the processing through step S7 is executed, and the function 2 is generated for a period of T2 (= 30). Subsequently, at the next time, since N = 3, the processing through step S8 is executed, and the function 3 becomes T3 (= 2
0). Thereafter, when N = 4, 100
The period (reception time) of ms stops.

The generation time of each of the functions 1 to 3 based on the generation time of each function set by the above processing (total of 100
ms) and the reception time (100 ms) are repeated twice, the variable T becomes 1000. in this case,
In step S5 of the main flow, the process shifts to a process when it is determined that T = 1000. In this case, again, each function 1
To 3 (power ratio) are changed, and in this example, T1
= 20, T2 = 10, and T3 = 70. Thereafter, returning to the main flow, the function 1 is generated in step S6 for a time of T1 (20), and subsequently, when N = 2, the function 2 is changed to T2 (= 1).
0), and when N = 3, the function 3 becomes T3 (= 70)
Time to occur. Thereafter, when N = 4, the period is stopped for 100 ms.

When the operation cycle of the generation time and the reception time of the functions 1 to 3 is repeated twice, the variable T becomes 140
Since it exceeds 0, this is detected in step S10 of the main flow, and the processing is terminated.

FIG. 9 is a diagram showing characteristics of a plurality of waves generated by the present invention. Is a diagram showing a change in frequency (ft) of three multiple waves generated according to time, and FIG. Represents the change in the pulse width of three waves generated in response to time, and C.I. Represents the power of each of the plurality of waves that changes with time.

FIG. As shown in (1), the functions of the corresponding functions 1 to 3 are calculated for the frequencies (ft) of the plurality of waves using the respective function parameters. A. In the example, the multiple wave 1 is a function having a constant frequency, the multiple wave 2 is a linear function descending to the lower right, and the multiple wave 3 is an example of a linear function increasing to the upper right.

These plural waves 1 to 3 correspond to B.B. As shown in the figure, a plurality of waves 1 are generated for a pulse width of time T1,
A plurality of waves 2 are generated for a pulse width of time T2, and a plurality of waves 3 are generated for a pulse width of time T3. Thereafter, a stop time (reception time) of T4 is provided, and the operation is repeated. The plurality of waves 1 to 3 correspond to the functions 1 to 3 of the first embodiment, and the pulse widths T1 to T3 of the plurality of waves 1 to 3 are the first three cycles at the time of the initial setting shown in FIG. With the respective pulse widths of 30, 20, and 50 set in the above, the next two cycles are the same as those set in the processing of FIG.
With the respective pulse widths of 20, the subsequent two cycles have the respective pulse widths of 20, 10, and 70 set in the processing of FIG. The ratio of the time during which these multiple waves 1 to 3 exist is the power ratio.

C. of FIG. Is B. in FIG. Represents the power divided for each of the plurality of waves 1 to 3 when each of the plurality of waves 1 to 3 occurs. In this way, the power can be arbitrarily divided for each of the plurality of waves by changing the pulse widths (generation time widths T1 to T3) from one another and changing them over time. It can be generated without limiting the power. However, the sum of the powers of the plurality of waves 1 to 3 is constant.

FIG. 10 is a configuration diagram of the second embodiment, and FIG. 11 is a processing flow of the second embodiment. The second embodiment corresponds to the second principle configuration of the present invention shown in FIG. In FIG. 10, reference numerals 5 to 12, 20, and 21 correspond to the respective circuits having the same reference numerals in FIG. 2, and the variable frequency divider 5 and the counter 6 have the same configuration as that in FIG. 7 to 12 have the same names and configurations as the circuits of the same reference numerals in FIG.

Reference numeral 20 denotes a time division control circuit,
0b to 20i correspond to the respective parts of 1b to 1i in FIG.
20b is a CPU, 20c is an input / output port (I / O port), 20d is a timer, 20e is a program ROM,
20f is a RAM, 20g is an external memory interface, 20h is a bus, and 20i is a data bus between the external memory and the external memory interface. Reference numeral 20j, which is not provided in FIG. 7, denotes a bus (address and control line) for controlling sequentially reading out designated function data (waveform data) from the mass storage device 21, which is an external memory. A large-capacity storage device 21 stores function data 1 to 3 provided as an external memory.
In the second embodiment, six 1M-bit EEPROMs are provided.

The large-capacity storage device 21 is a programmable ROM in which function data 1 to 3 are stored. Specifically, for example, a 1-Mbit parallel EEPROM (Electrical
lyErasable Programmable ROM). Reference numeral 12 denotes a switch which is turned on at the time of transmission and turned off at the time of reception. In the time division control circuit 20, the selection switch 20a of FIG. 2 selects function data from the mass storage device 21 by the CPU 20b and performs read control from the data bus 20j via the external memory interface 20g. The operation corresponds to an operation of extracting read data from 20i and transferring the read data to the variable frequency divider 5 via the I / O port 20c.

The second embodiment shows an example in which three function data 1 to 3 are stored in the large-capacity storage device 21, and the program ROM 20e is controlled by the CPU 20b of the time division control circuit 20.
It operates according to the program stored in.

The processing flow of the second embodiment shown in FIG. 11 includes a main flow similar to that of the first embodiment (see FIG. 8) and a processing flow of the first embodiment.
And a branch flow including contents different from those indicated by.

First, N, T, Tpw, T1 to T4 representing each variable or constant provided in the RAM 20f are initialized in the same manner as in the first embodiment in FIG. 8 (S1 in FIG. 11). In this case, T1 is the pulse width of plural waves 1 (corresponding to function data 1), T2 is the pulse width of plural waves 2 (corresponding to function data 2), and T3 is the pulse width of plural waves 3 (corresponding to function data 3). , T4 is the width of the reception time (time during which transmission is suspended).

Thereafter, the same processing as in FIG.
5) is performed, and if it is determined that N = 1 in step S6, the process proceeds to the process of FIG. Here, first, the variable Tpw representing the time width and the variable T representing the time are each incremented by 1 (S60 in FIG. 11), and the large-capacity storage device 21
The first function data 1 is sent to the variable frequency divider (5 in FIG. 10) to generate the function 1 (S61 in FIG. 11). Thereafter, it is determined whether the variable Tpw does not exceed the set pulse width T1 (S62), and the operations in S60 and S61 are repeated until the variable Tpw exceeds the set pulse width T1. The variable frequency divider 5 generates a function 1 by dividing the frequency of the pulse from the pulse oscillator 5a according to the function data 1 input from the time division control circuit 20 according to the principle described in FIG. The occurrence time of function 1 is Tpw> T1
, Tpw is returned to 0 (S63), and the flow returns to the main flow.

Thereafter, the same processing as in FIG.
= 2, if the condition of N = 2 is satisfied in step S7, the processing in FIG. 11 (S70 to S7 in FIG. 11)
3) is executed. In this case, the second function data 2 is sent to the variable frequency divider 5 for a period of time T2, and returns to the main flow. Thereafter, when N = 3 is updated in the main flow, the process proceeds to step S8.
In this case, the same processing as described above (S8 in FIG. 11)
0 to S83), the third function data 3 is sent to the variable frequency divider 5, and when the time period T3 elapses, Tp
Set w to 0.

After this processing, returning to the main flow, N =
4, the process proceeds to step S9 because N = 4, and T4 is performed by the same process as in FIG.
Stops generating function data for the time set in.
Thereafter, the processing at time T = 600 and the processing at time T = 1000 are performed as described with reference to FIG. 8, and the pulse width of each function data is changed to change the power ratio. And the process is repeated, and the time T = 1
The process ends at 400.

The operation cycle of the generation time and reception time of each of the functions 1 to 3 generated in the processing flow of the second embodiment in FIG.
The characteristics of a plurality of waves generated in this case are the same as those in FIG. ~ C. Is the same as that shown in FIG.

Next, FIG. 12 is a configuration diagram of the third embodiment, and FIG. 13 is a processing flow of the third embodiment. The third embodiment corresponds to FIG.
Corresponds to the third principle configuration of the present invention shown in FIG. In FIG. 12, reference numerals 6 to 12 correspond to the circuits having the same reference numerals in FIG. 3, the counter 6 has the same configuration as in FIG. 7 (Embodiment 1), and reference numerals 7 to 12 designate the same reference numerals in FIG. Each circuit has the same name and configuration, and a description thereof will be omitted.

Numeral 30 denotes a time division control circuit, which has three internal circuits.
0a to 30g correspond to the parts 1b to 1h in FIG.
30a is a CPU, 30b is an input / output port (I / O port) for generating control signals for external 31 and 33, 30c is a timer, 30d is a program ROM, 30e is a RAM,
30f is an external memory interface, and 30g is a bus. Reference numeral 31 denotes an analog switch including switches SW1 to SW3. Reference numerals 32-1 to 32-3 denote ramp function generators 1 to 3 and 33 which generate ramp function waveforms (analog voltages) having different slopes, respectively, and V / F converters. .

In the third embodiment, three ramp function generators 3
An example including 2-1 to 32-3 is shown, and the CPU 30a of the time division control circuit 30 operates according to a program stored in a program ROM 30d.

The processing flow of the third embodiment shown in FIG. 13 includes a main flow similar to that of the first embodiment (FIG. 8) and the second embodiment (FIG. 11), and includes contents specific to the third embodiment. It consists of a branch flow.

First, N, T, Tpw, T1 to T4 representing each variable or constant provided in the RAM 30e are initialized with the same values as those in the first embodiment of FIG. 8 (S in FIG. 13).
1).

Thereafter, the same processing as in FIG.
5) is performed, and if it is determined that N = 1 in step S6, the process proceeds to the process of FIG. Here, first, the analog switch SW1 is turned on, the SW2 and SW3 are turned off (S60 in FIG. 13), and then the variable Tpw representing the time width is set.
And a variable T representing time are set to +1 (S in FIG. 13).
61). Thereby, the ramp function generator 32- of FIG.
1 is supplied to the V / F converter 33, and the output of FIG.
The frequency corresponding to the function 1 is generated according to the principle described in (1) and supplied to the counter 6 (S62 in FIG. 13). When the pulse width becomes Tpw> T1, Tpw is set to 0 (S6).
4) Return to the main flow.

Thereafter, the same processing as in FIG.
= 2, the condition of N = 2 is satisfied in step S7, and the processing in FIG. 13 (S70 to S73 in FIG. 11) is executed. In this case, the analog switch SW2 is turned on, the output of the second ramp function generator 32-2 is output during the pulse width T2, and the function data 2 is generated. This function data 2 is sent to the variable frequency divider 5 for a period of time T2, and returns to the main flow.

Next, when N = 3 is updated in the main flow, the process proceeds to step S8.
In this case, the analog switch SW3 is turned on, and 3
The output of the third ramp function generator 32-3 has a pulse width T3
And the function 3 is generated. When the period of time T3 has elapsed, Tpw is set to 0. After this process, when the process returns to the main flow and becomes N = 4, the process shifts to N4 in step S9, and is set to T4 by the same processes as those in FIG. 8 and FIG. The generation of function data is stopped for a period of time.

Thereafter, the processing at the time T = 600 and the processing at the time T = 1000 are executed and the pulse width of each function data is executed in the same manner as described with reference to FIGS. Is changed to change the power ratio, and the process is repeated, ending with time T> 1400.

Although the characteristics of each of the plurality of waves generated in the processing flow of the third embodiment shown in FIG.
9 (Example 1) and FIG. 11 (Example 2) in FIG. ~
C. Is the same as the example.

FIG. 14 is a block diagram of the fourth embodiment. The fourth embodiment corresponds to the fourth principle configuration of the present invention shown in FIG. In FIG. 14, 1 to 12 and 40 correspond to FIG.
1 to 6 and 7 to 12 are the same circuits as those in the configuration of the first embodiment (FIG. 7), and the description is omitted. 40 is a sine function generator, RO
It is composed of an M / D / A converter and a differential amplifier circuit (indicated by an OP amplifier), and generates a sine function in accordance with the values of the four-stage phase bits of the counter 6. Reference numeral 41 denotes a mixer for mixing the received signal and the frequency signal of the sine function generator 40.

The fourth embodiment shows an example in which three function parameters 1 to 3 stored in the programmable ROM 2 are used. The operation is performed by the CPU 1b of the time division control circuit 1 in accordance with the program stored in the program ROM 1e.

With the configuration shown in FIG. 14, the processing flow is the same as that of the first embodiment, and the operation is performed according to the processing flow shown in FIG. However, in the case of FIG. 14, unlike the configuration of the first embodiment (FIG. 7), the output of the sine function generator 40 driven by the output of the counter 6 is supplied to the mixer 41 so that the received signal is converted by each function. Modulate. Also in the case of the fourth embodiment, a plurality of waves are generated with the same characteristics as in FIG.

FIG. 15 is a block diagram of the fifth embodiment. The fifth embodiment corresponds to the fifth principle configuration of the present invention shown in FIG. In FIG. 15, 5-8, 10-12, 2
Reference numerals 0, 21, and 41 correspond to the respective circuits having the same reference numerals in FIG. 5, and reference numerals 5 to 8, 10, 12, 20, and 21 denote the same circuits as the reference numerals in the configuration of the second embodiment (FIG. 10). The explanation is omitted. Similarly to the fourth embodiment (FIG. 14), reference numerals 40 and 41 denote a sine function generator, and reference numeral 41 denotes a mixer for mixing the received signal and the frequency signal of the sine function generator 40.

In the fifth embodiment, three function data 1 to 3 stored in a mass storage device 21 composed of an EEPROM
3 shows an example in which the CPU of the time division control circuit 20 is used.
20b operates according to the program stored in the program ROM 20e.

The operation of the fifth embodiment shown in FIG. 15 is the same as that of the second embodiment, and operates according to the processing flow shown in FIG. However, in the case of FIG. 15, unlike the configuration of the second embodiment (FIG. 10), the output of the sine function generator 40 driven by the output of the counter 6 is supplied to the mixer 41 so that the received signal is converted by each function. Modulate.

Also in the case of the fifth embodiment, a plurality of waves are generated with the same characteristics as in FIG. Next, FIG. 16 is a configuration diagram of the sixth embodiment. The sixth embodiment corresponds to the sixth principle configuration of the present invention shown in FIG.

In FIG. 16, 7, 8, 10 to 12, 3
6 correspond to the circuits of the same reference numerals in FIG. 6, and 7 to 8, 10 to 12, and 30 to 32-2 correspond to the reference numerals of the configuration of the third embodiment (FIG. 12). The circuit is the same and the description is omitted. Reference numerals 40 and 41 denote a mixer, and reference numeral 42 denotes a sine (SIN) wave output type V / F converter, similarly to the fourth embodiment (FIG. 14).

In the sixth embodiment, the ramp function generator 32-1
An example is shown in which three function data 1 to 3 generated from .about.32-3 are used, and the CPU 30a of the time division control circuit 30 operates according to a program stored in a program ROM 30d.

The operation according to the configuration of the sixth embodiment of FIG. 16 is the same as that of the third embodiment, and operates according to the processing flow shown in FIG. However, in the case of FIG. 16, unlike the configuration of the third embodiment (FIG. 12), the voltage of the ramp function generators 32-1 to 32-3 output from the analog switch 31 is applied to the sine output type V / F converter 42. The signal is converted into a sine wave frequency signal and input to the mixer 41 for modulation.

In the operation shown in each of the above-described first to sixth embodiments, three examples are shown in which three functions are generated by providing three function parameters, function data, function generators, etc., respectively. It is needless to say that the number can be provided. Further, the pulse widths (T1 to T3) at which the signals of the respective functions used in the embodiment are generated, and the first and second pulse widths are generated.
It is clear that the change time and stop time numerical value and unit can be arbitrarily changed depending on the performance of the program or the circuit element and the target signal.

[0080]

According to the present invention, it is possible to realize a multispectral repeater that effectively interferes with a radar signal, a radio communication signal, and the like so that a radar or a receiver cannot identify an original signal. it can. In particular, since it is possible to generate a plurality of waves without limiting the frequency of the signal, the time change of the frequency, and the specifications of the power, it is possible to improve the performance of a device that interferes with a radar or the like.

[Brief description of the drawings]

FIG. 1 is a first principle configuration diagram of the present invention.

FIG. 2 is a second principle configuration diagram of the present invention.

FIG. 3 is a third principle configuration diagram of the present invention.

FIG. 4 is a fourth principle configuration diagram of the present invention.

FIG. 5 is a diagram illustrating a fifth principle configuration of the present invention.

FIG. 6 is a diagram illustrating a sixth principle configuration of the present invention;

FIG. 7 is a configuration diagram of the first embodiment.

FIG. 8 is a processing flow of the first embodiment.

FIG. 9 is a diagram showing characteristics of a plurality of waves generated according to the present invention.

FIG. 10 is a configuration diagram of a second embodiment.

FIG. 11 is a processing flow according to the second embodiment.

FIG. 12 is a configuration diagram of a third embodiment.

FIG. 13 is a processing flow according to the third embodiment.

FIG. 14 is a configuration diagram of a fourth embodiment.

FIG. 15 is a configuration diagram of a fifth embodiment.

FIG. 16 is a configuration diagram of a sixth embodiment.

FIG. 17 is a configuration diagram of Conventional Example 1.

FIG. 18 is a configuration diagram of Conventional Example 2.

[Explanation of symbols]

 Reference Signs List 1 time division control circuit 1a selection switch 2 small capacity storage device 2a function parameters 1 to n 3 register 4 arithmetic unit 5 variable frequency divider 5a oscillator 6 counter 7 antenna (antenna) 8 transmission / reception switch 9 phase shifter 10 delay line 11 Amplifier 12 switch

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hideaki Yonekura 1-18-32A Building, Fuchinobe, Sagamihara City, Kanagawa Prefecture 105 (72) Inventor Jun Arima 1-18-32D Building, Fuchinobe, Sagamihara City, Kanagawa Prefecture 301 (72) Inventor Shigeru Fujisawa 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Keito Kondo 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-4-286979 ( JP, A) JP-A-5-37223 (JP, A) JP-A-5-307077 (JP, A) JP-A-4-154301 (JP, A) JP-A-64-53184 (JP, A) JP JP-A-7-27856 (JP, A) JP-A-7-38463 (JP, A) JP-A-63-4075 (JP, A) JP-A-2-309834 (JP, A) JP-A-2-69777 (JP) , U) Japanese Utility Model Showa 63-62786 (JP, U ) Hikaru 4-41675 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01S 7/38 H04B 1/40 H04K 3/00

Claims (6)

(57) [Claims] 1. A multi-spectrum repeater that transmits a received signal by modulating the received signal with a plurality of waves.
A small-capacity storage device including a phase shifter that receives a received signal and performs phase modulation, and stores a plurality of function parameters corresponding to a time function (ft) of a plurality of frequencies, and a time ratio that specifies the plurality of function parameters A time division control circuit for selectively switching and outputting the function parameter, and the output function parameter being input, performing an operation using a time function (ft) and a value representing a constant frequency (fc), and performing a specific function (fc / ft ), And a variable frequency divider that receives a signal of a constant frequency (fc) and divides the frequency by the specific function from the arithmetic unit, and outputs an output signal of the variable frequency divider as a phase bit. A multi-spectrum repeater that converts the signal into a signal and controls the phase shifter. 2. A multi-spectrum repeater for transmitting a modulated signal by modulating a received signal with a plurality of waves.
A large-capacity storage device that includes a phase shifter to which a received signal is input and performs phase modulation, and that stores a plurality of function data representing a value of a time function (ft) of a plurality of frequencies; A time-division control circuit for selectively switching and outputting at a ratio, and a variable frequency divider for inputting a signal of a constant frequency and dividing the frequency by the selectively output function data; A multi-spectrum repeater, which converts the output signal of (1) into a phase bit signal and controls the phase shifter. 3. A multi-spectrum repeater that transmits a received signal by modulating the received signal with a plurality of waves.
A plurality of function generators having a phase shifter to which a received signal is input and performing phase modulation, and generating a time function (ft) analog voltage of a plurality of frequencies; and a time ratio specifying the plurality of function generators And a voltage / frequency converter for converting the voltage of the selectively output function generator into a frequency. The output signal of the voltage / frequency converter is A multi-spectrum repeater that converts the signal into a phase bit signal and controls the phase shifter. 4. The apparatus according to claim 1, further comprising a mixer that performs phase modulation instead of the phase shifter to which a received signal is input,
A multispectral repeater, comprising: a sine function generator for generating a sine wave having a frequency corresponding to the phase bit signal, and inputting an output of the sine function generator to the mixer. 5. The apparatus according to claim 2, further comprising a mixer that performs phase modulation instead of the phase shifter to which a received signal is input,
A multispectral repeater, comprising: a sine function generator for generating a sine wave having a frequency corresponding to the phase bit signal, and inputting an output of the sine function generator to the mixer. 6. The apparatus according to claim 3, further comprising a mixer that outputs a transmission signal instead of the phase shifter to which a reception signal is input, wherein a frequency corresponding to the voltage of the selectively output function generator is provided. A multi-spectrum repeater, comprising: a sine wave output type voltage / frequency converter for generating a sine wave of the formula (1), and inputting the output of the sine wave output type voltage / frequency converter to the mixer.