JPH09172785A - Control method for power circuit and device thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate dead time applied to the rise of a switching signal such as a PWM signal in controlling the power circuit of an inverter or the like. SOLUTION: A motor current feedback value or estimated value, and positive and negative reference voltage are compared with each other to discriminate the direction of current I supplied to a motor from an inverter for each a.c. output terminal of the inverter. Switching in the transistor Q2 which needs no switching of upper and lower transistors Q1 and Q2 is prohibited forcibly according to the results of discrimination. It is thus possible to prevent the upper transistor Q1 and the lower transistor Q2 from turning on at the same time without providing dead time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power circuit control method and apparatus for controlling a power circuit such as an inverter.

[0002]

2. Description of the Related Art A general structure of a three-phase inverter 10 is shown in FIG. Inverter 1 shown in this figure
0 is a three-phase AC load that converts a DC current supplied from the DC power supply 12 through the smoothing capacitor C into a three-phase AC current.
4, for example, a circuit that supplies a motor, and includes six transistors (eg, IGBT: Insulated Gate Bipolar Tra
nsistor) Q1 to Q6 and diodes D1 to D6. Transistors Q1 and Q2, Q3 and Q4, Q5
And Q6 form a pair, and are connected in series in the forward direction between the positive and negative terminals of the DC power supply 12. The diodes D1 and D2, D3 and D4, D5 and D6 are paired with each other, and are connected in reverse series between the positive and negative terminals of the DC power supply 12. Furthermore, each transistor Q1 to Q6
And the diodes D1 to D6 are connected in reverse parallel to each other. U, V and W phase output terminals to the AC load 14 are
Connection points of transistors Q1 and Q2, Q3 and Q, respectively
It is provided at the connection point of 4 and the connection point of Q5 and Q6. The transistors Q1 to Q6 are turned on / off by a PWM (pulse width modulation) signal supplied from the circuit shown in FIG.
The off-switched current sensors 16U, 16V, 16W provided at the U-, V-, and W-phase output terminals of the inverter 10 detect the detected value (of the current flowing through the AC load 14 in the circuit shown in FIG. 6). Hereinafter referred to as motor current feedback).

The circuit shown in FIG. 6 is disclosed in, for example, Japanese Unexamined Patent Publication No.
3 is a schematic configuration of an inverter control device configured according to the disclosure of Japanese Patent No. 316738. The circuit shown in this figure includes a command wave generator 18, a carrier oscillator 20, and a modulator 2.
2. The upper / lower distribution unit 24 and the rising delay circuit 26 are provided. The command wave generation unit 18 responds to the target output of the AC load (hereinafter also referred to as a motor) 14 and the current sensor 16
Command wave e for each phase of U, V and W while referring to motor current feedback values from U, 16V and 16W
Generate 0U, e0V and e0W. Each of the command waves e0U, e0V, and e0W has a sine waveform whose phases are different from each other by 2π / 3 as shown in FIG. 7, for example. The carrier wave oscillator 20 generates a carrier wave eS having a waveform such as a triangular wave or a sawtooth wave. The modulator 22 has three comparators provided corresponding to the U, V, and W phases, and the command waves e0U, e0V, and e0W of the respective phases are provided by the comparators.
And carrier eS. The resulting signal is
PW as shown in FIG. 7 as “modulator output”
It becomes the M signal. The upper and lower distribution unit 24 has the above-mentioned modulation unit 2
2 outputs the upper transistors Q1 and Q of the inverter 10.
The output of the modulator 22 is logically inverted and distributed to the lower transistors Q2, Q4 and Q6. As shown in FIG. 8, the rise delay circuit 26 is supplied with P from the modulator 22 via the upper / lower distributor 24.
By delaying the rising edge of the WM signal by a predetermined time (usually about 5 μs), a period in which the upper transistor (eg Q1) and the lower transistor (eg Q2) of the inverter 10 are not turned on at the same time, that is, a dead time is provided,
The prevention of simultaneous firing of both transistors is ensured. The output of the rising delay circuit 26 is supplied to the transistors Q1 to Q6 of the inverter 10 after being processed by a circuit (not shown).

[0004]

The above dead time is necessary to prevent the upper and lower transistors of the power circuit such as an inverter from being turned on at the same time, that is, to prevent the positive and negative terminals of the DC power supply from being short-circuited. It is valid. However, since the dead time is provided, the waveform of the current supplied from the power circuit to the load is distorted.
This distortion substantially reduces the power transfer rate of the power circuit to the load. Further, by providing the dead time, the voltage utilization factor of the DC power supply is also lowered, so that there is also a problem that the output of the AC load is likely to be reduced due to the voltage drop of the DC power supply.

One of the objects of the present invention is to provide switching signals (eg, PWM) to the upper and lower switching elements (eg, transistors) that constitute a power circuit such as an inverter.
Controlling the supply of the (signal) ensures that the positive and negative terminals of the DC power supply are not short-circuited, eliminates the dead time, and eventually improves the effective power transfer rate to the AC load, and also the DC power supply. It is to improve the voltage utilization rate of and to maintain the output of the AC load.

[0006]

In order to achieve such an object, the inventor has studied the switching operation in the prior art shown in FIGS. As shown in FIG. 9 by taking the U phase as an example, in the above-described conventional technique, a period in which the upper transistor is on and the lower transistor is off (see FIG.
(See (a)) and the period in which the upper transistor is off and the lower transistor is on (see FIG. 9 (c)), when switching between the upper side and the lower side as shown in FIG. 9 (b). A dead time is provided by the rise delay circuit so that all the lower transistors are turned off. What the inventor has paid attention to is that there is a transistor that is switched when it is originally not necessary when viewed from the flow path of the current inside the inverter. For example, in the state where the current I is supplied from the inverter to the AC load as shown by the solid line arrow in FIG. 9, the current I is supplied only to the upper transistor and the lower diode.
Current flows through the lower transistor (Q2 in the figure). In the state where the current I is flowing from the AC load to the inverter as indicated by the broken line arrow in the figure, the current I flows only in the upper diode and the lower transistor, and the current I flows in the upper transistor (Q1 in the figure). Does not flow. However, the lower transistor is also switched during the period indicated by the solid line arrow, and the upper transistor is also switched during the period indicated by the broken line arrow.

The inventor paid attention to such a fact, and
And as shown in FIG. 2, switching of either the upper side transistor or the lower side transistor (more generally a switching element) is performed according to the direction of the current I flowing between the inverter (more generally a power circuit) and the AC load. I devised a way to ban. For example, as shown in FIG. 1 using the U phase as an example, when the current is flowing from the inverter to the AC load, the switching of the lower transistor which does not need to be switched is prohibited (that is, kept in the OFF state). ), And when the current I is flowing from the AC load to the inverter as shown in FIG. 2 using the U phase as an example, the switching of the upper transistor which does not need to be switched is prohibited (that is, kept off). I decided. Based on such a principle, the present invention eliminates the dead time in the prior art, improves the transfer rate of effective power from a power circuit such as an inverter to an AC load, and improves the utilization rate of a DC power supply. is there.

[0008]

In order to realize the above-mentioned principle, the first configuration of the present invention is to provide an upper and lower switching element (eg, IGBT) connected in series in the forward direction between the positive and negative terminals of a DC power source. Etc.) and upper and lower current direction regulating elements (eg, diodes) reversely connected in parallel to the upper and lower switching elements, and a load (eg, motor) via a connection point of the upper and lower switching elements. In a power circuit control method for controlling a power circuit (for example, an inverter) connected to a switch so that the upper and lower switching elements thereof do not turn on at the same time, an on / off of an upper switching element and an on / off of a lower switching element are performed. Generate a switching signal so that they are complementary, and whether the direction of the current between the connection point and the load is toward the load. In either case, the step of determining whether it is suitable for the power circuit, the step of cutting off the supply of the switching signal to the lower switching element when it is directed to the load, and the step of cutting off the supply of the switching signal to the upper switching element when directed to the power circuit, respectively. The switching element is forcibly kept in the off state by interrupting the supply of the switching signal to either the upper or lower switching element according to the direction of the current.

The second structure of the present invention is that the upper and lower switching elements connected in series in the forward direction between the positive and negative terminals of the DC power supply and the upper and lower switching elements connected in reverse parallel to the upper and lower switching elements. In a power circuit control device for controlling a power circuit having a lower current direction regulating element and connected to a load through a connection point of the upper and lower switching elements so that the upper and lower switching elements do not turn on at the same time, Means for generating a switching signal so that the on / off of the upper switching element and the on / off of the lower switching element are complementary, and the direction of the current between the connection point and the load is for the load or for the power circuit. And a switching signal supply to the lower switching element when the load circuit is suitable for the power circuit. Means for supplying the switching signal to the upper switching element, to cut off each of the,
And shutting off the supply of the switching signal to either the upper side switching element or the lower side switching element according to the direction of the current, thereby forcibly keeping the switching element in the off state.

In these configurations, when the direction of the current between the connection point of the upper and lower switching elements and the load is in the load direction, the switching signal is supplied to the lower switching element and in the power circuit direction. The supply of the switching element to the upper switching element is cut off. Accordingly, the switching element whose supply of the switching signal is interrupted is kept in the off state, and as a result, when transitioning from the upper on lower off off period to the upper off lower side on period or vice versa, There is no need to provide dead time.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. It should be noted that the same or corresponding configurations as those of the conventional technique shown in FIGS. Further, the present invention can be implemented with the inverter 10 shown in FIG. 5 as a target, and therefore the configuration of FIG. However, the present invention is not limited to the three-phase inverter shown in FIG. 5, but can be applied to various single-phase or multi-phase switching power circuits. In addition, the switching element to be directly controlled is not limited to the transistor such as IGBT. Furthermore, the element that regulates the current direction is not limited to the diode, and the switching element is not limited to the PWM signal. Further, when the three-phase alternating current is supplied to the motor 14, one of the sensors 16U, 16V and 16W can be omitted by utilizing the relationship that the sum of the phase currents becomes zero. When the command wave is generated in accordance with the logic capable of estimating the motor current, all of these sensors can be abolished and the motor current estimated value can be used in the operation described later instead of the motor current feedback value.

FIG. 3 shows the main configuration of the control device for the inverter 10 according to the first embodiment of the present invention.
In this figure, only the current direction determination unit 28 and the switching pause gate 30 according to the features of the present invention are shown in addition to the above-mentioned vertical distribution unit 24, but this is for simplification of the illustration. Actually, the command wave generator 18 shown in FIG.
The carrier wave oscillator 20 and the modulator 22 are used together.

The feature of this embodiment lies in that the rise delay circuit 26 shown in FIG.
And W by eliminating the motor current feedback value from W to eliminate the dead time in the prior art. As a result, in the present embodiment, the distortion of the current I flowing through the motor 14 is reduced to improve the transfer rate of effective electric power to the motor 14, and the voltage utilization rate of the DC power supply 12 is improved to reduce the voltage of the DC power supply 12. The output of the motor 14 is prevented from being decreased due to the decrease.

In the circuit shown in FIG. 3, the current direction determination unit 28 compares the U-phase motor current feedback value with the positive reference voltage and the negative reference voltage, respectively.
And 28b, a comparator 28 for comparing the V-phase motor current feedback value with the positive and negative reference voltages, respectively.
c and 28d, and a comparator 28 that compares the W-phase motor current feedback value with the positive and negative reference voltages.
e and 28f. The positive reference voltage is a reference voltage for detecting that a current is flowing from the inverter 10 to the AC load 14, that is, a current in the direction shown in FIG.
a, 28c and 28e output H value signals when the motor current feedback value of the corresponding phase exceeds the positive reference voltage, that is, when the current flows in the direction shown in FIG. The negative reference voltage is a reference voltage for detecting that a current is flowing from the motor 14 to the inverter 10, that is, a current is flowing in the direction shown in FIG. 2, and the comparators 28b, 28d and 28f outputs a signal of H value when the motor current feedback value of the corresponding phase is below the negative reference voltage. The inverters 28g, 28h and 28i provided in the subsequent stage of the comparators 28a, 28c and 28e are
The output of the corresponding comparator is logically inverted and supplied to the switching pause gate 30.

The switching pause gate 30 has a total of six AND gates 30a to 30f provided corresponding to the comparators 28a to 28f. Each of the AND gates 30a to 30f has two input terminals, one of which is the output of the corresponding comparator (or inverter) in the current direction determination unit 28, and the other is the output of the upper / lower distribution unit 24. , Each supplied. Therefore, AN
The outputs of the D gates 30a to 30f are values obtained by gating the output of the upper / lower distribution unit 24 with the output of the current direction determination unit 28. That is, when the motor current feedback value exceeds the positive reference voltage and therefore it can be considered that the current in the direction shown in FIG. 1 is flowing, the PWM signal supply to the lower transistors Q2, Q4 and Q6 is cut off, When the current feedback value is below the negative reference voltage and therefore it can be considered that the current in the direction shown in FIG. 2 is flowing, the upper transistors Q1 and Q
The supply of the PWM signal for 3 and Q5 is cut off. P
The transistor in which the supply of the WM signal is cut off is turned off. Therefore, with the circuit shown in FIG. 3, it is possible to realize the operational effects according to the principle shown in FIGS.

Further, in the present embodiment, even though the dead time is eliminated, the upper and lower transistors are turned on at the same time even near the zero cross point where the sign (direction) of the current I is reversed. It can be surely prevented. Conventionally, as shown in FIG.
4 in the period in which the current I is decreasing (see FIG. 4A), immediately after time t1, and in the period in which the current I is increasing (see FIG. 4B) immediately after time t5, respectively. A dead time is provided so that the upper transistor and the lower transistor (Q1 and Q2 in FIG. 4, which is an example of the U phase) are turned off at the same time. In contrast,
In the present embodiment, either the upper transistor or the lower transistor is forcibly turned off in accordance with the direction of the current I, so that the dead time is not provided between t1 and t2 or between t5 and t6. During this period, both the upper and lower transistors are turned off, so that the dead time is eliminated and the upper and lower sides are turned on simultaneously.
The risk of a short circuit between the positive and negative terminals of can be reliably avoided.

[0017]

As described above, according to the first and second configurations of the present invention, when the direction of the current between the connection points of the upper and lower switching elements and the load is the load, the lower side is selected. Since the supply of the switching signal to the switching element is cut off and the supply of the switching signal to the upper switching element is cut off when the power circuit is suitable, the upper switching element is turned on and the lower switching element is turned off from the upper switching element. It is not necessary to provide a dead time in which both the upper and lower switching elements are turned off at the time of transition to the period of = off and lower switching element = on or vice versa. As a result, the waveform of the current flowing through the load becomes an ideal waveform determined by the switching signal, and it is possible to prevent distortion of a type unintended for generating the switching signal. By reducing such distortion,
The transfer rate of effective power to the load is improved. Further, as the dead time is eliminated, the voltage utilization factor of the DC power supply is improved, and as a result, it is possible to prevent or suppress the output reduction of the load due to the voltage reduction of the DC power supply.

[0018]

[Addendum] The present invention can be understood as the following configurations.

(1) In a third configuration of the present invention, in the first or second configuration, the connection is based on a current value detected by a sensor and fed back to generate a command related to the operation of the power circuit. It is characterized in that the direction of the current between the point and the load is determined. According to this configuration, the first
Also, the same operational effect as the second configuration can be obtained. further,
This configuration is suitable for application to a device that has conventionally been provided with a current feedback sensor for command generation in that it does not require addition of a sensor.

(2) In the fourth configuration of the present invention, in the first or second configuration, the connection point and the load are based on the current value estimated when the command related to the operation of the power circuit is generated. It is characterized in that the direction of the current between the two is determined. According to this configuration, the same operational effects as those of the first and second configurations can be obtained. Furthermore, this configuration is suitable for application to a device that estimates the direction of current by an estimation operation in control logic, etc., in that the current value obtained by estimation at the time of command generation can be used.

(3) An electric vehicle according to a fifth aspect of the present invention is an AC motor for driving a vehicle, a DC power supply for supplying a drive current to the AC motor, and the DC power supply to the AC motor. It is characterized by including an inverter that converts a supplied drive current from a direct current to an alternating current, and a power circuit control device that controls the inverter that is the power circuit according to the first to fourth configurations of the present invention. According to this configuration, the same operational effects as those of the first to fourth configurations can be obtained. In particular, as a result of the reduction of current distortion due to the elimination of dead time, iron loss of the AC motor is reduced and the travelable distance per charge of the DC power supply is increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram for explaining the principle of the present invention. In particular, FIG. 1A shows a control state in which a current flows from an inverter to an AC load via an upper transistor,
FIG. 1B is a diagram showing a control state in which a current is flowing from the inverter to the AC load via the lower diode.

FIG. 2 is a circuit diagram for explaining the principle of the present invention. In particular, FIG. 2A shows a control state in which a current is flowing from an AC load to an inverter via a lower transistor,
FIG. 2B is a diagram showing a control state in which current flows from the inverter to the AC load via the upper diode.

FIG. 3 is a circuit diagram showing a main configuration of a control device according to an embodiment of the present invention.

FIG. 4 is a timing chart showing a control state in the vicinity of a motor current zero cross in this embodiment, and FIG. 4A particularly shows the control state when the motor current decreases.
(B) is a figure which shows the control state when increasing, in comparison with the conventional technology.

FIG. 5 is a circuit diagram showing a general circuit configuration of an inverter.

FIG. 6 is a block diagram showing a circuit configuration of an inverter control device according to a conventional technique.

FIG. 7 is a timing chart showing the principle of inverter control by a PWM signal.

FIG. 8 is a timing chart showing a process of giving a dead time to a PWM signal.

FIG. 9 is a circuit diagram showing a control state when dead time is added, and in particular, FIG. 9A shows a state in which an upper transistor is on and a lower transistor is off.
9B is a diagram showing dead time, and FIG. 9C is a diagram showing a state in which the upper transistor is off and the lower transistor is on.

[Explanation of symbols]

10 Inverter, 14 AC load (motor), 16
U, 16V, 16W current sensor, 18 command wave generation unit, 20 carrier wave oscillator, 22 modulation unit, 24 vertical distribution unit, 28 current direction determination unit, 28a to 28f comparator, 28g to 28i inverter, 30 switching pause gate, 30a ~ 30f AND gate, Q
1-Q6 transistor (IGBT), D1-D6 diode, es carrier, e0U, e0V, e0W command wave.

Claims (2)

[Claims] 1. An upper and lower switching element connected in series in a forward direction between positive and negative terminals of a DC power supply, and an upper and lower current direction regulating element connected in reverse parallel to the upper and lower switching elements. In a power circuit control method for controlling a power circuit connected to a load through a connection point of upper and lower switching elements so that the upper and lower switching elements do not turn on at the same time, an upper switching element is turned on / off and a lower switching element is turned on / off. Generating a switching signal so that the ON / OFF of the side switching element is complementary, determining whether the direction of the current between the connection point and the load is for the load or for the power circuit, and for the load The switching signal is supplied to the lower switching element when Respectively, the step of cutting off the supply of the switching signal to the switching element, and the switching element is cut off by cutting off the supply of the switching signal to either the upper side or the lower side switching element according to the direction of the current. A control method for a power circuit, which is characterized by forcibly maintaining an off state. 2. An upper and lower switching element connected in series in a forward direction between positive and negative terminals of a DC power supply, and an upper and lower current direction regulating element connected in reverse parallel to the upper and lower switching elements. In a power circuit control device that controls a power circuit connected to a load through a connection point of upper and lower switching elements so that the upper and lower switching elements do not turn on at the same time, ON / OFF and ON / OFF of the upper switching element Means for generating a switching signal so that ON / OFF of the side switching element is complementary, means for determining whether the direction of current between the connection point and the load is for the load or for the power circuit, and for the load , The switching signal is supplied to the lower switching element, and when the power circuit is suitable, the upper switching element is supplied. And a means for cutting off the supply of the switching signal to the switching element, and by forcibly shutting off the switching element by cutting off the supply of the switching signal to either the upper or lower switching element according to the direction of the current. A power circuit control device characterized by being kept in an off state.