JPH09107107A - Thin film transistor, this film transistor array and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a TFT having high reliability kept for a long time. SOLUTION: A thin film transistor comprises an insulating substrate 1, a poly-Si layer 100a formed on the insulating substrate 1, and a channel transistor 2 and source and drain regions 5 and 6 formed on the poly-Si layer 100a, the channel transistor 2 put between the source and drain regions 5 and 6. In the transistor, a region 7 of a conductivity type opposite to that of the source and drain regions 5 and 6, is formed next to and contacting with the channel region 2 on the poly-Si layer 100a. The potential of the opposite conductivity type region 7 is kept lower than that of the source region 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading sensor, a load of a RAM (Random Access Memory), a thin film transistor used in a liquid crystal display device, and the like.
sistor: Hereinafter, abbreviated as TFT. ), A thin film transistor array (hereinafter also referred to as a TFT array), and a liquid crystal display device (hereinafter also abbreviated as an LCD).

[0002]

2. Description of the Related Art In the field of liquid crystal display devices using thin film transistors, polycrystalline silicon thin film transistors (hereinafter abbreviated as poly-Si TFTs) in which a driving circuit can be incorporated are mainly used in viewfinders and projections of video tape recorders. Type liquid crystal display device has been put to practical use, and further research and development have been actively conducted. In particular, a low-temperature poly-Si TFT using a low-temperature poly-Si that can be manufactured at a relatively low temperature (generally 600 ° C. or lower) using an inexpensive glass substrate instead of an expensive quartz substrate has been particularly attracting attention. As an example of this low temperature poly-Si TFT, "Society of Informa
tion Dislay International Symposium Digest of Tech
nical Papers / Volume XXIV (1993) pp387-390 ", and Fig. 10 shows this low temperature poly-Si TF.
It is the figure which showed the cross-section of T. Hereinafter, the manufacturing process of the conventional low temperature poly-Si TFT will be briefly described with reference to FIG. First, after depositing an amorphous silicon layer on the entire surface of the substrate 1, the amorphous silicon layer is locally heated and melted and crystallized by laser irradiation to obtain polycrystalline silicon. Then, the polycrystalline silicon layer 10 patterned into desired islands by photolithography and etching techniques.
Get 0. Next, the gate insulating layer 3 made of SiO ₂ is covered with the ECR (Electron) so as to cover the polycrystalline silicon layer 100.
Cyclotron Resonance) -CVD (Chemical Vapor De)
position) method. Next, the gate insulating layer 3
Gate electrode 4 made of tantalum (Ta) at a predetermined position above
And a source region 5 and a drain region 6 are formed by introducing an impurity serving as a donor or an acceptor into the polycrystalline silicon layer 100 by ion doping without mass separation using the gate electrode 4 as a mask. . At this time, the region of the polycrystalline silicon layer 100 immediately below the gate insulating layer 3 becomes the channel region 2. Next, after forming the interlayer insulating layer 8 on the gate insulating layer 3 so as to cover the gate electrode 4, each penetrates the interlayer insulating layer 8 and the gate insulating layer 3 to form the source region 5 or the drain. The low temperature poly-Si TFT is completed by forming the source electrode 10 and the drain electrode 11 which are joined to the region 6.

Low temperature poly-Si T produced as described above
Since FT uses poly-Si as a semiconductor layer, it is more preferable than a transistor using amorphous silicon as a semiconductor layer.
It has a large field effect mobility (hereinafter, simply referred to as mobility). In the manufacturing process, P-type and N-channel transistors are selectively formed on the substrate by selectively using p-type impurities such as boron and n-type impurities such as phosphorus as impurities in the CMO.
An S (Complementary-Metal-Oxide-Semiconductor) circuit can be manufactured. Therefore, it is possible to manufacture a liquid crystal display device in which the pixel transistor and its drive circuit are built on the same substrate.

[0004]

However, FIG.
The conventional poly-Si TFT shown in FIG. 1 has the following problems. FIG. 11 shows the conventional structure shown in FIG.
The drain current (ID) -drain voltage (VD) characteristics of the poly-Si TFT are shown. Normal MOSFET (Meta
In the l-Oxide-Semiconductor Field Effect Transistor), the drain current tends to saturate at high drain voltage. However, as shown in FIG. 11, in the conventional poly-Si TFT shown in FIG. 10, the drain current increases once the drain voltage increases, but the drain current increases again when the voltage further increases. Begin to. This is generally called a Kink current, and similar phenomena have been reported not only in poly-Si TFTs but also in TFTs having an SOI (Silicone on insulating substrate) structure. The cause will be described below. When a high electric field is applied to the drain end, carriers accelerated by the high electric field cause avalanche amplification to form electron-hole pairs. And
This is because the electrons flow toward the high-voltage drain side, whereas the holes flow toward the low-voltage source, increasing the current. For example, in the case of an n-channel TFT, the holes created by avalanche amplification go backwards in the channel, so that the mobility deteriorates and the reliability deteriorates. Since liquid crystal display devices are thin, lightweight and highly portable, they are often used outdoors. Not only are they exposed to direct sunlight outdoors, but temperature conditions become extremely severe in some regions. Therefore, ensuring the reliability of the TFT in the liquid crystal display device is an important issue. Further, the liquid crystal display device is also used as a cockpit display of an aircraft, and the liquid crystal display device used as a cockpit display for an aircraft requires a higher level of reliability of the device. Therefore, a liquid crystal display device for an aircraft is required. In the above, ensuring the reliability of the TFT has become a particularly important issue.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a TFT, a TFT array, and a liquid crystal display device that maintain high reliability for a long time.

[0006]

To achieve the above object, a thin film transistor according to the present invention comprises a semiconductor thin film formed on an insulating substrate in which a channel region and source and drain regions sandwiching the channel region are formed. In a thin film transistor in which a gate electrode is formed on a semiconductor thin film so as to overlap the channel region via an insulating layer, a semiconductor layer having a conductivity type opposite to that of the source and drain regions is in contact with the channel region of the semiconductor thin film. Thus, the potential of the semiconductor layer is kept lower than the potential of the source region.

In the thin film transistor array according to the present invention, a plurality of the thin film transistors are arranged in a two-dimensional matrix of rows and columns, and the gate electrodes of the thin film transistors arranged in the same row are connected to one gate bus line. , The source electrodes of the thin film transistors arranged in the same column are connected to one source bus line, and the semiconductor layers of the thin film transistors arranged in the same row are parallel to the gate bus line and are in electrical contact with the gate electrode. Not 1
It is characterized in that it is connected to a bus line of a book.

In the thin film transistor array according to the present invention, a plurality of the thin film transistors are arranged in a two-dimensional matrix of rows and columns, and the gate electrodes of the thin film transistors arranged in the same row are connected to one gate bus line. , The source electrodes of the thin film transistors arranged in the same column are connected to one source bus line, and the semiconductor layers of the thin film transistors arranged in the same row are parallel to the source bus line and are in electrical contact with the source electrodes. Not 1
It is characterized in that it is connected to a bus line of a book.

The thin film of the liquid crystal display device according to the present invention is
A liquid crystal display device comprising a substrate in which a liquid crystal is sandwiched between two substrates, and a pixel electrode and a pixel transistor for switching the pixel electrode are arranged in a matrix pattern on its main surface as one substrate. The substrate on which the pixel transistors are arranged and formed in a matrix is a substrate on which the thin film transistor array is formed.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION In a thin film transistor of the present invention, a channel region and source and drain regions sandwiching the channel region are formed in a semiconductor thin film formed on an insulating substrate, and the semiconductor thin film is formed on the semiconductor thin film with an insulating layer interposed therebetween. In a thin film transistor in which a gate electrode is formed so as to overlap with a channel region, a semiconductor layer having a conductivity type opposite to that of the source and drain regions is provided so as to contact the channel region of the semiconductor thin film, and the potential of the semiconductor layer is increased. Is kept lower than the potential of the source region, holes generated at the drain end flow into the semiconductor layer without moving backward in the channel region, resulting in deterioration of the channel region, that is, migration. Deterioration can be suppressed, and the reliability of the element can be maintained for a long time.

Further, in the thin film transistor of the present invention, as a preferred example of the above structure, when the semiconductor layer is formed below the semiconductor thin film so as to contact the semiconductor thin film, the semiconductor layer and the semiconductor The thin film is surely contacted with the channel region with a large contact area, and the effect of suppressing deterioration of mobility can be more reliably obtained. Therefore, the effect of maintaining the high term reliability of the device for a long time is further enhanced.

Further, in the thin film transistor array of the present invention, a plurality of the thin film transistors are arranged in a two-dimensional matrix of rows and columns, and the gate electrodes of the thin film transistors arranged in the same row are connected to one gate bus wiring. , 1 for the source electrode of the thin film transistor arranged in the same row
Connected to one source bus line, and the semiconductor layers of the thin film transistors arranged in the same row are connected to one bus line that is parallel to the gate bus line and does not make electrical contact with the gate electrode. Therefore, by setting the potential of the bus line lower than the potential of the source bus line, deterioration of the channel region in each thin film transistor is suppressed, and the reliability is kept high for a long time.

In the thin film transistor array of the present invention, a plurality of the thin film transistors are arranged in a two-dimensional matrix of rows and columns, and the gate electrodes of the thin film transistors arranged in the same row are connected to one gate bus line. , 1 for the source electrode of the thin film transistor arranged in the same row
A plurality of thin film transistors arranged in the same row are connected to one bus line parallel to the source bus line and not in electrical contact with the source electrode. Therefore, by setting the potential of the bus line lower than the potential of the source bus line, deterioration of the channel region in each thin film transistor is suppressed, and the reliability is kept high for a long time.

In the liquid crystal display device of the present invention, 2
A liquid crystal display device comprising a substrate in which a liquid crystal is sandwiched between a plurality of substrates, and a substrate on which a pixel electrode and a pixel transistor for performing switching of the pixel electrode are arranged in a matrix pattern on one of the substrates, Since the substrate on which the pixel transistors are arranged and formed in a matrix is the substrate on which the thin film transistor array is formed, the liquid crystal display device can maintain reliability for a long time.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 shows poly-Si according to Embodiment 1 of the present invention.
FIG. 2A is a plan view showing the structure of the TFT, and FIG.
FIG. 2B is a sectional view taken along the line BB ′ of FIG. 1, taken along the line A ′. The TFT of this embodiment is a coplanar poly-Si TFT, and a semiconductor region having a conductivity type opposite to that of the source / drain regions is arranged beside the channel region so as to be in contact with the channel region.

The po of this embodiment will be described below with reference to these figures.
The structure of the ly-Si TFT will be described in the order of manufacturing steps. On a substrate (# 1733 glass manufactured by Corning Incorporated) 1 having a SiO ₂ film as a buffer layer for preventing diffusion of impurities in the glass substrate, amorphous silicon (hereinafter referred to as a -Si is abbreviated.)
A film is deposited and formed, and then the film is microfabricated by an ordinary photolithography and etching technique into an island shape.
By irradiating with an excimer laser beam of 08 nm, it is locally heated and melted and crystallized to form a polycrystalline silicon layer (hereinafter abbreviated as poly-Si layer) 100a. Next, S is formed so as to cover the polycrystalline silicon layer 100a.
Approximately 100 nm thick gate insulating layer 3 made of i0 ₂
It is formed by using the CR-CVD method. Then, a chromium (Cr) film is deposited on the gate insulating layer 3 by, for example, a sputtering method, and the Cr film is patterned by a usual photolithography and etching technique to form the gate electrode 4. Next, using the gate electrode 4 as a mask, the source region 5 and the drain region 6 of the polycrystalline silicon layer 100a should be formed by ion doping with phosphorus (P) serving as a donor without mass separation. Inject into each area. Here, a region sandwiched between the source region 5 and the drain region 6 of the polycrystalline silicon layer 100a to be formed is defined as the channel region 2. Next, a doping mask is formed by photolithography, and using the mask as a mask, boron (B) is added to the source region 5 and the drain region 6 of the polycrystalline silicon layer 100a and the respective regions where these are to be formed. The implantation is selectively performed only in the regions adjacent to the channel region 2 other than the channel region 2 sandwiched between the regions. Next, 300-60
After the heat treatment at about 0 ° C., the injected phosphorus (P) is injected.
And impurities of boron (B) are activated, and the source region 5 and the drain region 6 are formed in the polycrystalline silicon layer 100a.
And the opposite conductivity type region 7 is formed. Then, for example, AP
(Atmosphere Pressure) -Insulating film SiO _{2 by} CVD method
An interlayer insulating layer 8 made of a film is formed, and a contact hole 9 is formed on the insulating layer 8. Then, finally, for example, an aluminum (Al) film is deposited and formed by a sputtering method, and this is patterned by a photolithography etching technique, so that the source electrode 10, the drain electrode 11,
And the opposite conductivity type region electrode 12 is formed, poly-S
iTFT is completed. Poly- produced in this way
In the Si TFT, the potential of the opposite conductivity type region 7 is set lower than the potential of the source region 5 by the opposite conductivity type region electrode 12, and a predetermined transistor operation is performed in this state.

FIG. 3 shows the drain current (ID) -drain voltage (VD when the poly-Si TFT of this embodiment is operated.
) Characteristic, it can be seen from this figure that the drain current is completely saturated in the high drain voltage region and no Kink current is observed. Further, FIG. 4 shows the change characteristics of the mobility when an electric stress is applied. From this figure, the poly-Si TFT of this embodiment is the poly-Si TFT of the conventional example.
It can be seen that the deterioration of mobility is extremely smaller than that of T.

As described above, in the poly-Si TFT of this embodiment, the source region 5 and the drain region 6 are opposite in conductivity type to the source region 5 and the drain region 6 so as to be adjacent to the channel region 2 in the polycrystalline silicon layer 100a. By forming 7,
Mobility deterioration can be made extremely small, and high reliability can be maintained for a long time.

(Embodiment 2) FIG. 5 is a plan view showing the structure of a poly-Si TFT according to Embodiment 2 of the present invention, FIG. 6 (a) is a sectional view taken along the line CC ′ of FIG. 5, and FIG. 6B is a sectional view taken along the line DD ′ of FIG. Example 1 poly
In the polycrystalline silicon layer 100a in which the Si TFT has formed the channel region 2, the source region 5 and the drain region 6, the opposite conductivity type region 7 having the opposite conductivity type to the source region 5 and the drain region 6 is provided beside the channel region 2. In contrast, the poly-Si TFT of this embodiment is formed so as to be in contact with the channel region, whereas the poly-Si TFT of this embodiment has a poly-Si layer 1 in which a channel region 2, a source region 5 and a drain region 6 are formed.
Underneath 00, poly-Si containing an impurity of a conductivity type opposite to that of the impurities forming the source region 5 and the drain region 6 is formed.
The layer 7a is formed so as to contact the channel region 2.

Hereinafter, the poly-Si TFT of this embodiment TFT
The configuration will be described in the order of manufacturing steps. A poly-Si layer 7a containing boron (B), which is an impurity having an opposite conductivity type, to phosphorus (P), which is an impurity forming a source region 5 and a drain region 6, which will be described later, is formed on the substrate 1. The poly-Si layer 7a containing this boron (B) is, for example, plasma CV.
An a-Si film containing boron (B) is deposited and formed by the D method, and the film is finely processed into an island shape by a normal photolithography and etching technique, and then an excimer laser beam having a wavelength of 308 nm is irradiated to locally form the film. It is formed by heating, melting, and crystallization. The subsequent steps are basically the same as those in the first embodiment and the conventional example.
An impurity-free poly-Si layer 100 is formed on the Si layer 7a, a gate insulating layer 3 is formed so as to cover the poly-Si layer 100, a gate electrode 4 is formed, and then a gate electrode is formed. Phosphorus (P), which serves as an acceptor, is ion-implanted as a mask to form source and drain regions 5 and 6,
Next, an interlayer insulating layer 8 is formed, a contact hole 9 is opened in the interlayer insulating layer 8, and finally metallization is performed to form a source electrode 10, a drain electrode 11 and an opposite conductivity type region electrode 1.
2 is formed to complete the thin film transistor. In the above, the area of the poly-Si layer 7a containing boron (B) is
It is formed so as to be slightly larger than the area of the poly-Si layer 100, and one end of the opposite conductivity type region electrode 12 is po
It is formed so as to be joined to a part of the exposed portion of the poly-Si layer 7a after the formation of the ly-Si layer 100.

In the poly-Si TFT of this embodiment, the poly-Si layer 100 in which the channel region 2 is formed is formed.
Is formed on the poly-Si layer 7a containing an impurity having a conductivity type opposite to that of the impurities forming the source region 5 and the drain region 6, the channel region 2 and the source region 5 and the drain region 6 have opposite conductivity types. The contact with the opposite conductivity type region is surely performed with a large contact area. Therefore, the effect of reducing the deterioration of the mobility can be more reliably obtained, and the long-term maintenance effect of high reliability is further enhanced.

In the first and second embodiments, a TFT having a coplanar device structure has been described, but it goes without saying that the present invention can be applied to a TFT having a staggered device structure or an inverted staggered device structure.

In the first and second embodiments, the semiconductor layer in which the channel region is formed is a poly-Si layer crystallized by laser irradiation, but the semiconductor layer in which the channel region is formed is described as follows. Poly-Si formed by other methods such as solid phase growth method and direct deposition method
Layers and those using a single crystal Si layer such as SOI,
It goes without saying that the present invention can be applied.

Further, in the first and second embodiments, the impurity introduction for forming the source region and the drain region is performed by using the ion doping method, but in the present invention, the same effect can be obtained by using the plasma doping method. Obtainable.

In the first and second embodiments, Cr is used as the material of the gate electrode and Al is used as the material of the source electrode, the drain electrode and the electrode for the opposite conductivity type region. However, in the present invention, the material of the gate electrode is used. As a metal such as aluminum (Al), tantalum (Ta), molybdenum (Mo), chromium (Cr), and titanium (Ti), or an alloy thereof, or poly-Si or po containing a large amount of impurities.
A ly-SiGe alloy may be used, a source electrode,
As a material for the drain electrode and the electrode for the opposite conductivity type region, a metal such as aluminum (Al), tantalum (Ta), molybdenum (Mo), chromium (Cr), and titanium (Ti) or an alloy thereof, or ITO or the like is used. A transparent conductive layer may be used.

Further, the poly-SiTF of Examples 1 and 2 above
Although not particularly adopted in T, in the present invention, an LDD (Lightly Doped Drain) is used in the TFT in order to improve off characteristics.
It is also possible to adopt a structure.

Although not specifically described in the first and second embodiments, in the present invention, acceptor impurities such as boron and arsenic and donor impurities such as phosphorus and aluminum are selectively used in the manufacturing process. It is also possible to simultaneously form a CMOS circuit on a substrate by selectively forming P-channel and N-channel transistors.

(Third Embodiment) FIG. 7 is a plan view showing the structure of a TFT array according to a third embodiment of the present invention. In the drawing, the same reference numerals as those in FIGS. Reference numerals 14 and 15 denote a gate bus wiring, a source bus wiring, and a bus wiring for the opposite conductivity type area, respectively. The TFT array of the present embodiment has a structure in which the TFT of the first embodiment is formed on the substrate 1.
Are arranged in a two-dimensional matrix of rows and columns, the opposite conductivity type electrodes 12 of the TFTs arranged in the same row are connected to the same bus wire 15 for the opposite conductivity type region, and the gate electrodes 4 of the TFTs arranged in the same row are the same. Of the TFTs connected in the same column and connected to the gate bus line 13 of the same source bus line 14
, And the potential of the opposite conductivity type electrode 12 of the TFT can be changed according to ON / OFF of the gate.

In the TFT array of this embodiment as described above,
By setting the potential of the opposite conductivity type region bus line 15 lower than the potential of the source bus line 14, deterioration of the channel region in each TFT is suppressed, and the reliability of the array is kept high for a long time.

(Embodiment 4) FIG. 8 is a plan view showing the structure of a TFT array according to Embodiment 4 of the present invention. In the drawing, the same reference numerals as those in FIGS. There is. In the TFT array of this embodiment, the TFTs of the first embodiment are arranged in a two-dimensional row / column matrix on the substrate 1, and the opposite conductivity type electrodes 12 of the TFTs arranged in the same column are for the same opposite conductivity type region. The gate electrodes 4 of the TFTs connected to the bus line 15 and arranged in the same row are connected to the same gate bus line 13
And the source electrodes 10 of the TFTs arranged in the same column are connected to the same source bus line 14 to turn on / off the gate.
According to F, the potential of the opposite conductivity type electrode 12 of the TFT can be changed.

In the TFT array of this embodiment, the same action and effect as those of the TFT array of the third embodiment can be obtained. (Embodiment 5) FIG. 9 is a sectional view showing the structure of a liquid crystal display device according to Embodiment 5 of the present invention. In the drawing, the same reference numerals as those in FIGS. In the liquid crystal display device of the present embodiment, a TFT array similar to the TFT array of the third or fourth embodiment is formed as the one side substrate, and the pixel electrode 16 is connected to each drain electrode 11 of each TFT. Using a first substrate body formed of a transparent conductive layer such as ITO (Indium-Tin-Oxide), a color filter 18, a black matrix 19, and a transparent conductive layer 20 are formed on the surface of the counter substrate 17 as the other side substrate. Using the formed second substrate body, the alignment films 21 are applied to the respective surfaces of the both substrate bodies and subjected to rubbing treatment,
A polarizing plate 23 is attached to the back surface of each of the substrates, and a twisted nematic liquid crystal 22 is sealed between the two substrates.

When this liquid crystal display device was subjected to a reliability test, it was possible to obtain a reliability life which was 10 to 100 times that of a liquid crystal display device produced using a conventional TFT array.
Although the twisted nematic liquid crystal is used as the liquid crystal in the liquid crystal display device of the present embodiment, if the polymer dispersion type liquid crystal is used as the liquid crystal, the alignment film and the polarizing plate become unnecessary.
However, in the case of the liquid crystal display device using the polymer dispersed liquid crystal, the driving voltage is 2-3 times higher than that of the liquid crystal display device using the twisted nematic liquid crystal, and the reliability required for the TFT array becomes more severe. However, even in this case, as compared with the liquid crystal display device using the conventional TFT array, 10
It was confirmed that a reliable life of up to 100 times was obtained.

[0033]

As described above, according to the thin film transistor of the present invention, a semiconductor region having a conductivity type opposite to that of the source and drain regions is provided in contact with the channel region, and the potential of the semiconductor region is set to the potential of the source region. By keeping it lower than the above, deterioration of mobility is extremely small, and high reliability is maintained for a long time. Further, according to the thin film transistor array of the present invention, since the mobility of each thin film transistor is extremely small and the high reliability is maintained for a long time, the reliability can be maintained high for a long time. Further, according to the liquid crystal display device of the present invention, the substrate on one side thereof is a substrate in which the thin film transistor array is formed and the pixel electrode is connected to each drain electrode of each TFT. Will be kept high for a long time.

[Brief description of the drawings]

FIG. 1 is a plan view showing the structure of a poly-Si TFT according to a first embodiment of the present invention.

2A is a sectional view taken along the line AA ′ of FIG. 1, and FIG. 2B is a sectional view taken along the line BB ′ of FIG.

FIG. 3 is a diagram showing a drain current (ID) -drain voltage (VD) characteristic when a poly-Si TFT according to a second embodiment of the present invention is operated.

FIG. 4 is a diagram showing the change characteristics of the mobility when an electrical stress is applied to the poly-Si TFT according to the first embodiment of the present invention in comparison with that of the conventional poly-Si TFT.

FIG. 5 is a plan view showing a configuration of a poly-Si TFT according to a second embodiment of the present invention.

6A is a cross-sectional view taken along the line CC ′ of FIG. 5, and FIG. 6B is a cross-sectional view taken along the line DD ′ of FIG.

FIG. 7 is a plan view showing a configuration of a TFT array according to a third embodiment of the present invention.

FIG. 8 is a plan view showing the structure of a TFT array according to a fourth embodiment of the present invention.

FIG. 9 is a sectional view showing a configuration of a liquid crystal display device according to a fifth embodiment of the present invention.

FIG. 10 is a plan view showing the structure of a conventional poly-Si TFT.

FIG. 11 is a diagram showing a drain current (ID) -drain voltage (VD) characteristic when a conventional poly-Si TFT is operated.

[Explanation of symbols]

 1 substrate 2 channel region 3 gate insulating layer 4 gate electrode 5 source region 6 drain region 7 opposite conductivity type region 7a poly-Si layer containing boron (B) 8 interlayer insulating layer 9 contact hole 10 source electrode 11 drain electrode 12 opposite conductivity Electrode for type region 13 Gate bus line 14 Source bus line 15 Bus line for opposite conductivity type region 16 Pixel electrode 17 Counter substrate 18 Color filter 19 Black matrix 20 Transparent conductive layer 21 Alignment film 22 Twisted nematic liquid crystal 23 Polarizing plate 100 poly- Si layer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuya Kawamura 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Yutaka Miyata, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (5)

[Claims] 1. A semiconductor thin film formed on an insulating substrate is formed with a channel region and source and drain regions sandwiching the channel region, and a gate electrode is formed on the semiconductor thin film so as to overlap the channel region via an insulating layer. In the thin film transistor formed, a semiconductor layer having a conductivity type opposite to that of the source and drain regions is provided so as to contact a channel region of the semiconductor thin film, and the potential of the semiconductor layer is lower than the potential of the source region. A thin film transistor characterized by being held. 2. The thin film transistor according to claim 1, wherein the semiconductor layer is formed below the semiconductor thin film so as to be in contact with the semiconductor thin film. 3. A plurality of thin film transistors according to claim 1 are arranged in a two-dimensional matrix of rows and columns, and the gate electrodes of the thin film transistors arranged in the same row are connected to one gate bus line, and the same column is formed. One source electrode of the thin film transistors arranged in parallel is connected to one source bus line, and each semiconductor layer of the thin film transistors arranged in the same row is parallel to the gate bus line and is not in electrical contact with the gate electrode. A thin film transistor array, which is connected to a bus line of a. 4. A plurality of thin film transistors according to claim 1 are arranged in a two-dimensional matrix of rows and columns, and the gate electrodes of the thin film transistors arranged in the same row are connected to one gate bus line, and the same column is formed. One source electrode of the thin film transistors arranged in line is connected to one source bus line, and each semiconductor layer of the thin film transistors arranged in the same row is parallel to the source bus line and is not in electrical contact with the source electrode. The thin film transistor array is characterized in that it is connected to the bus wiring of. 5. A liquid crystal display comprising a substrate in which a liquid crystal is sandwiched between two substrates, and a substrate in which a pixel electrode and a pixel transistor for switching the pixel electrode are arranged in a matrix form on one of the substrates as one substrate. A liquid crystal display device, wherein the substrate on which the pixel transistors are arranged and formed in a matrix is a substrate on which the thin film transistor array according to claim 3 or 4 is formed.