JPH08306640A - Mos field effect transistor and its manufacture - Google Patents

Abstract

PURPOSE: To provide a MOS field effect transistor of low leakage current in the off-state. CONSTITUTION: Both a low crystallizability source region 114A and a drain region 114b as high resistant layers as well as both a high crystallizability source region 109a and a drain region 109b as active layers are formed on both sides of a channel layer 103 so as to form a flare stopping film 104 to be used for laser activation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS field effect transistor and a method for manufacturing the same, and more specifically, it relates to
The present invention relates to a thin film type that can be used for an active matrix type image display device or an image sensor.

[0002]

2. Description of the Related Art As a semiconductor device having a thin film transistor (TFT) on an insulating substrate such as glass, an active matrix type liquid crystal display device using a thin film transistor for driving pixels and an image sensor are known. Thin film silicon semiconductors are generally used for thin film transistors used in these devices.

Thin-film silicon semiconductors are roughly classified into two types, those consisting of amorphous silicon semiconductors and those consisting of crystalline silicon semiconductors. Amorphous silicon semiconductors are most commonly used because they have a low manufacturing temperature, can be relatively easily manufactured by a vapor phase method, and have high mass productivity. Since it is inferior to semiconductors, in the future, in order to obtain higher speed characteristics, establishment of a method for manufacturing a thin film transistor made of a crystalline silicon semiconductor is strongly required.

As a crystalline silicon semiconductor,
Single crystal silicon (c-Si), polycrystalline silicon (p-S)
i), microcrystalline silicon (μc-Si), amorphous silicon containing a crystalline component, semi-amorphous silicon having an intermediate state between crystalline and amorphous are known. These crystalline silicon thin film transistors have higher carrier mobility than amorphous silicon thin film transistors. Therefore, as a display device, a driver integrated type is possible due to improved driving capability, and mobility is improved. With this, miniaturization is possible, and high aperture ratio and high density can be realized.

A p-Si (polycrystalline silicon) TFT which is a conventional top gate type silicon thin film transistor (MOS type field effect transistor) having crystallinity is described below.
Will be described. FIG. 8 shows a sectional view of a conventional p-Si TFT.

First, a base coat film 202 made of a SiO ₂ film is formed on an insulating substrate 201 made of quartz, glass or the like by a sputtering method or the like, and then CVD (Chemical V
aporDeposition: vapor phase growth) to form an amorphous silicon film, and then to form a channel by solid-phase growth (SPC) or laser crystallization in which thermal annealing is performed in a thermal diffusion furnace at about 600 ° C. A polycrystalline silicon film 203 to be an active layer is formed. Next, the polycrystalline silicon film 20
3 is etched into an island pattern to form a gate insulating film 206 made of a SiO ₂ film by a CVD method or the like.
A gate electrode 207 made of an Al film is formed by a sputtering method or the like.

After that, the gate insulating film 206 other than the region of the gate electrode 207 is masked with the gate electrode 207.
(Not shown) is etched to form a polycrystalline silicon film 203
A source region and a drain region are formed by doping with an impurity element. At this time, a large number of accelerated ions (P
⁺ , B ⁺ , H ^+, etc. are implanted, the crystallinity of the implanted region is destroyed and deteriorates. Therefore, as indicated by 210, the source region 209a and the drain region 209b are formed by laser activation 210 from the substrate surface.

Next, as shown in FIG. 9, after an interlayer insulating film 211 made of a SiO ₂ film is formed by a CVD method or the like,
Contact holes are formed in the source region 209a and the drain region 209b, and a source electrode 212a and a drain electrode 212b made of an Al film are formed by a sputtering method or the like. Finally, if the transparent display electrode made of the ITO film (indium tin oxide film) is provided by the protective film 213 made of the SiN _x film by the CVD method or the sputtering method,
A display device as shown in FIG. 9 can be used.

[0009]

When the conventional p-Si (polycrystalline silicon) TFT having the above-mentioned structure is used,
In the case of an n-channel TFT, when a negative gate voltage is applied to the gate electrode and the TFT is turned off, a p-channel layer is formed under the gate electrode. In the case of a p-channel TFT, when a positive gate voltage is applied to the gate electrode and the TFT is turned off,
An n-channel layer will be formed under the gate electrode.

Therefore, in the case of a semiconductor layer having a channel of either n or p, the electric field applied to the gate is generated between the active layer, which is the drain region or the source region, and the channel layer, that is, the active layer, below the gate region. Concentrate near the joint. The polycrystalline silicon film includes many traps (carrier paths due to impurities at crystal grain boundaries), and a leak current flows through such traps even when the TFT is off. Therefore, p-S
The i (polycrystalline silicon) TFT has a problem that a large leak current depending on the gate voltage and the drain voltage flows.

The present invention was devised in view of the above circumstances, and a MOS type field effect transistor capable of reducing a leak current in an off state and a MOS type field effect transistor which can be manufactured with high accuracy by a simple process. It is intended to provide a manufacturing method of.

[0012]

In the MOS field effect transistor of the present invention according to claim 1, a high resistance region is formed between a channel layer and source and drain regions arranged on both sides of the channel layer. It is characterized by

The high resistance region may preferably be made of a low crystalline material.

In the MOS field effect transistor according to the third aspect of the present invention, the source region and the drain region arranged on both sides of the channel layer have a high crystalline region which becomes an active layer and a low crystalline region which becomes a high resistance layer. A low-crystalline region, and the low-crystalline region is arranged between the channel layer and the high-crystalline region.

In these field effect transistors,
Preferably, a light shielding film made of a refractory metal layer may be formed on the insulating substrate.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a MOS field effect transistor in which a channel layer and a source region and a drain region on both sides of the channel layer are formed on an insulating substrate via a base coat film. In the method of manufacturing a field effect transistor, impurities are ion-implanted into the source region and the drain region to form a low crystalline source region and drain region, and then, from the back surface of the insulating substrate to the channel layer and both sides thereof. Laser activation is performed through a light shielding film that shields a part of the low crystalline source region and a part of the drain region in the vicinity, so that the low crystalline source region on both sides of the channel layer is activated. It is characterized in that the highly crystalline source region and the highly crystalline drain region are formed through the portion and a part of the drain region.

The light-shielding film may preferably be composed of a refractory metal layer.

[0018]

In the MOS field effect transistor of the present invention, since the high resistance region is formed between the channel layer and the source region and the drain region arranged on both sides of the channel layer, the high resistance region is formed between the source region and the channel layer. The electric field concentration at the junction is relaxed, and the leak current when the transistor is off is reduced.

In the method of manufacturing a MOS field effect transistor of the present invention, impurities are ion-implanted into the source region and the drain region to form the low crystalline source region and drain region, and then from the back surface of the insulating substrate. Laser activation is performed through a light shielding film that shields the channel layer and a part of the low crystalline source region and a part of the drain region in the vicinity of both sides of the channel layer. Since the highly crystalline source region and the highly crystalline drain region are formed through a portion of the low crystalline source region and a portion of the drain region, the light shielding film is incident upon laser activation. It serves as a reflection film for laser light, which enables efficient crystallization and reduces damage to the insulating substrate. Further, the light-shielding film serves as a light-shielding film for the active layer from the backlight in the direct-view type panel or the projection lamp in the projection type panel in the completed state of the transistor, and also suppresses the leak current due to photoexcitation and has high crystallinity. Laser activation for forming the source region and the drain region is also facilitated, and manufacturing can be performed by an easy process.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The MOS type field effect transistor of the present invention will be described below in detail with reference to the drawings by taking a silicon thin film transistor as an embodiment and focusing on a manufacturing method thereof.

1 to 7 are provided for explaining each step of the manufacturing method of the transistor. FIG. 1 is before laser crystallization, FIG. 2 is laser crystallization, and FIGS. 3 and 4 are before ion implantation. FIG. 5 shows ion implantation, FIG. 6 shows crystallization by laser irradiation from the back surface and activation of impurities, and FIG. 7 shows a completed thin film transistor (TFT).

Referring to FIG. 1, first, a light shielding film 104 made of a Ta film or the like, which is a refractory metal, having a thickness of 150 is formed on an insulating substrate 101 made of quartz, glass or the like by a sputtering method or the like.
After forming a thickness of about 10 nm, a base coat film 102 made of a SiO ₂ film is formed to a thickness of about 300 nm by a sputtering method, and an amorphous silicon film 105 is formed to a thickness of about 50 nm by a CVD method (vapor phase growth method) or the like. .

Next, the amorphous silicon film 105 is formed into a polycrystalline silicon film 103 by a solid phase growth method (SPC method), a laser crystallization method or the like. FIG. 2 shows the case of laser crystallization 108. The conditions for laser crystallization 108 are
The oscillation wavelength is 308 nm of XeCl excimer laser, the irradiation energy density is about 300 mJ / cm ² , the oscillation time (pulse width) is about 50 ns, and the oscillation frequency is 30.
It was set to 0 Hz. However, the conditions differ depending on the state (film quality, film thickness, structure) of the film irradiated with the laser.

Next, as shown in FIG. 3, the polycrystalline silicon film 103 is etched into an island pattern by photolithography and dry etching.

Next, a gate insulating film 106 made of a SiO ₂ film is formed to a thickness of about 100 nm by a CVD method or the like, and then a gate electrode 10 made of an Al film is formed by a sputtering method or the like.
7 is formed to a thickness of about 500 nm. Thereafter, as shown in FIG. 4, the gate electrode 107 is etched into a gate line pattern by a photolithography method, a wet etching method, or the like, and then the gate electrode 107 is used as a mask.
The gate insulating film 106 (not shown) other than the 07 region is etched.

Next, as shown in FIG. 5, the polycrystalline silicon film 103 is doped with an impurity element to form a low crystalline source region 114a and a low crystalline drain region 114b.
To form. In the case of FIG. 5, the source region 114a and the drain region 11 having low crystallinity due to the ion implantation 115 are formed.
4b shows formation of 4b.

The conditions of this ion implantation 115 are: P ⁺ and H ^{+ as the} ion species and 30 at the implantation acceleration voltage in the case of n-channel.
The total injection amount was about 1 × 10 ¹⁶ / cm ^{2 at} about kV. In the case of p-channel, the ion species are B ⁺ and H ⁺ ,
The injection acceleration voltage is about 15 kV, and the total injection amount is 1 × 10 ^16.
/ Cm ² . However, the conditions vary depending on the state (film quality, film thickness, structure) of the ion-implanted film, and the contact resistance after activation, which will be described later, is set to be about 1 kΩ or less.

Then, as shown in FIG. 6, the insulating substrate 1
The laser activation 110 from the back surface of the light shielding film 104
(Laser annealing method) by performing the crystallization and the activation of impurities while partially leaving the low crystalline source region 114a and the drain region 114b. The drain region 109b can be formed.

The conditions for laser activation 110 were such that the oscillation wavelength was 308 nm of XeCl excimer laser, the irradiation energy density was about 400 mJ / cm ² , the oscillation time (pulse width) was about 50 ns, and the oscillation frequency was 300 Hz. However, the conditions differ depending on the state (film quality, film thickness, structure) of the film irradiated with the laser. Specifically, usually the melting starts amorphous silicon irradiation surface irradiation energy density is from about 150 mJ / cm ^2, 100 nm from the irradiated surface irradiation energy density of about 250 mJ / cm ²
It is melted to a depth. However, in this embodiment, the source region 109a is provided under the condition that the irradiation energy is absorbed by the insulating substrate 101 and the base coat film 102.
Further, in order to sufficiently activate the drain region 109b, the irradiation energy density needs to be about 300 mJ / cm ² or more.

Here, the remaining low crystalline source region 114a and drain region 114b serve as a contact layer having high resistance. As for the high resistance low crystalline contact regions 114a and 114b, the wider the
The leakage current in the off state of can be suppressed. However, if the width is too wide, the on-current will also be suppressed and the field effect movement will decrease, so it must be adjusted according to the required specifications. Specifically, 0.1-1.
It may be adjusted within a range of about 5 μm.

Finally, as shown in FIG. 7, an interlayer insulating film 111 made of a SiO ₂ film having a thickness of 600 is formed by a CVD method or the like.
After being formed to a thickness of about 10 nm, the highly crystalline source region 109a is formed.
And on the drain region 109b, the interlayer insulating film 1
11, contact holes are formed by a photolithography method and a wet etching method, and the source electrode 112a and the drain electrode 112b made of an Al film are formed to a thickness of 500 nm by a sputtering method or the like in a state of making contact with each contact hole.
After forming the film to a desired extent and etching the source / drain line pattern by photolithography and wet etching, a protective film 113 made of a SiN _x film is formed on the interlayer insulating film 111, the source electrode 112a and the drain electrode 112b by CVD or the like. A display device as shown in FIG. 7 can be obtained by forming and providing a display electrode made of an ITO film (indium tin oxide film) by a sputtering method or the like.

In the top gate type silicon thin film transistor which becomes the MOS field effect transistor manufactured as described above, the highly crystalline source region 109a and drain region 109b which are active layers and the polycrystalline silicon film which is an active layer ( Since the vicinity of the junction of the channel layer) 103 is a low crystalline source region 114a and drain region 114b, which form a high resistance region,
It is possible to reduce the electric field concentration at the junction portion and reduce the leak current when the TFT is in the off state.

That is, in the case of the n-channel TFT, the electron flow flows from the source electrode 112a to the source region 109a, the surface of the channel layer 103, the drain region 109b, and the drain electrode 112b in this order, as indicated by the arrow, and conversely, the current flows. From the drain electrode 112b to the drain region 109
b, the surface of the channel layer 103, the source region 109a, and the source electrode 112a flow in the order opposite to the arrow. n
In the off state of the channel TFT, an inversion layer of P ^{− to} P ⁺ is formed on the surface of the channel layer 103, and n is formed at the drain end.
A reverse bias state of the p-n between the drain region 109b having a ⁺ to become highly crystalline. Unlike the conventional structure, the reverse bias state of pn is p− with the low crystallinity region (high resistance) 114b sandwiched in the embodiment of the present invention.
With the n ⁻ −n ⁺ structure, it is possible to reduce the electric field concentration at the drain end, which was the cause of the leakage current in the past, and to suppress the leakage current.

In the case of a p-channel TFT, the same as the above can be said if holes are replaced as carriers.

Further, by forming the light-shielding film 104 with a refractory metal layer, the amorphous silicon film 105 shown in FIG. 2 is formed.
In the case of laser crystallization 108 from its surface, the film becomes a reflection film of incident laser light, and efficient crystallization of the thin film semiconductor layer and reduction of damage to the insulating substrate 101 can be achieved.

After the TFT is completed, the light-shielding film 104 is the channel layer 1 which is an active layer from a backlight in a direct-view type panel or a projection lamp in a projection-type panel.
It becomes a light-shielding film for 03 and can suppress the leak current due to photoexcitation.

Further, laser activation 110 for forming the highly crystalline source region 109a and drain region 109b is performed from the back surface of the insulating substrate 101 through the light shielding film 104, and the top gate having the above structure is formed. Type silicon thin film transistors can be formed by an easy process.

[0038]

According to the field effect transistor of the present invention, since the high resistance region is provided between the channel layer and the source region and between the channel layer and the drain region, the channel between the channel layer and the source region is The electric field concentration at the junction between the layer and the drain region is relieved, and leakage current in the off state of the transistor can be reduced.

According to the method for manufacturing a field effect transistor of the present invention, since there is a light-shielding film, it becomes a reflecting film of an incident laser beam at the time of activation by laser irradiation from the back surface of the insulating substrate, resulting in high efficiency. Good crystallization can be achieved, damage to the insulating substrate can be reduced, and a transistor can be manufactured by an easy process.

[Brief description of drawings]

FIG. 1 is a cross-sectional view before laser activation in a method for manufacturing a transistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing laser activation in an example.

FIG. 3 is a cross-sectional view showing a state of etching in the example.

FIG. 4 is a cross-sectional view when forming a gate electrode in an example.

FIG. 5 is a cross-sectional view showing ion implantation in an example.

FIG. 6 is a cross-sectional view showing laser activation from the back surface in the example.

FIG. 7 is a cross-sectional view showing a completed state of the transistor of the example.

FIG. 8 is a cross-sectional view at the time of laser activation in a conventional transistor manufacturing method.

FIG. 9 is a cross-sectional view of a conventional transistor in a completed state.

[Explanation of symbols]

 101 ... Insulating substrate 102 ... Base coat film 103 ... Polycrystalline silicon film (channel layer) 104 ... Light-shielding film (refractory metal layer) 105 ... Amorphous silicon film 106 ... Gate insulating film 107 ... Gate electrode 108 ... Laser crystallization 109a ... Highly crystalline source region (low resistance) 109b ... Highly crystalline drain region (low resistance) 110 ... Laser activation 111 ... Interlayer insulating film 112a ... Source electrode 112b ... Drain electrode 113 ... Protective film 114a ... Source region with low crystallinity (high resistance) 114b ... Drain region with low crystallinity (high resistance) 115 ... Ion implantation

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/78 627G

Claims (6)

[Claims] 1. A MOS field effect transistor, characterized in that a high resistance region is formed between a channel region and a source region and a drain region arranged on both sides of the channel layer. 2. The MOS field effect transistor according to claim 1, wherein the high resistance region is formed of a low crystalline material. 3. The source region and the drain region arranged on both sides of the channel layer are composed of a highly crystalline region which becomes an active layer and a low crystalline region which becomes a high resistance layer, and the low crystalline region is the above A MOS field effect transistor characterized by being arranged between a channel layer and the highly crystalline region. 4. The MOS field effect transistor according to claim 1, wherein a light-shielding film made of a refractory metal layer is formed on the insulating substrate. 5. A method for manufacturing a MOS field effect transistor in which a channel layer and a source region and a drain region on both sides of the channel layer are formed on an insulating substrate through a base coat film, wherein the source region and the drain region are formed on the insulating layer. Impurities are ion-implanted to form a low crystalline source region and a drain region, and then the channel layer is formed from the back surface of the insulating substrate and a part of the low crystalline source region near both sides of the channel layer and the drain region. By activating the laser through a light-shielding film that shields the light-shielding part from the high-crystallinity source region and the high-crystallinity source region on both sides of the channel layer, a part of the low-crystallinity source region and a part of the drain region are provided. A method for manufacturing a MOS field effect transistor, which comprises forming a crystalline drain region. 6. The method for manufacturing a MOS field effect transistor according to claim 5, wherein the light shielding film is made of a refractory metal layer.