JPH08274041A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To reduce a junction leakage current in the end parts of a LOCOS in a MOS transistor by a method wherein a silicon film having each facet on its end parts is formed on the end parts of the LOCOS on diffused layer formation regions and thereafter, an impurity layer having the sectional shape reflecting a facet shape is formed by ion implantation and heat treatment. CONSTITUTION: A field oxide film 2 of a LOCOS is formed on a silicon substrate 1 and moreover, a gate oxide film 3 and a polysilicon film 4 are formed. Subsequently, after arsenic is ion-implanted in diffused layer formation regions, an oxide film 5 is formed, a silicon film 6 is grown on the scheduled diffused layer formation regions and facets are respectively formed on the end parts of this film 6. Subsequently, arsenic is implanted in the scheduled diffused layer formation regions by an ion-implantation of the second time, heat treatment of the scheduled diffused layer formation regions is performed and an impurity layer 8, which has the sectional shape reflecting a facet shape and has an LDD structure, is formed. Moreover, after a prescribed process, a MOS transistor of a structure, wherein a junction leakage current in the end parts of the LOCOS is reduced, is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a MOS (Metal Oxide Semiconductor) type transistor and its manufacturing method.

[0002]

2. Description of the Related Art FIG. 2 shows an M of a semiconductor device according to the prior art.
FIG. 6 is a cross-sectional view showing an OS transistor and a process for forming the OS transistor in the order of processes.

As shown in FIG. 2A, p-type (100)
LOCOS: LOCal Oxidised on the silicon substrate 1 of
A field oxide film 2 of silicon) is formed. Figure 2
As shown in (b), a gate electrode composed of the gate oxide film 3 and the polysilicon film 4 to which phosphorus (P) is added is formed. Further, arsenic (As) is ion-implanted in the diffusion layer formation planned region. As shown in FIG. 2 (c), monosilane
A gate sidewall spacer made of a silicon oxide film 5 formed by a high temperature thermal CVD method using (SiH ₄ ) gas and nitrous oxide (N ₂ O) gas as raw materials is formed. Further, by the second ion implantation, arsenic is implanted into the diffusion layer formation planned region through the oxide film having a thickness of 5 nm. Then, heat treatment is performed in a nitrogen atmosphere at 800 ° C. to form a diffusion layer 8 having an LDD structure. As shown in FIG. 2D, the first layer, the second layer, and the third layer wiring are formed.

Here, in the first ion implantation,
A shallow junction is required to prevent the short channel effect.
So 1x1 at 15keV through 10nm thick oxide film
Implant 0 ¹⁴ / cm ² arsenic ions. The depth of the junction formed by this first ion implantation is about 50 nm. The depth of the junction formed by the second ion implantation must be 100 nm or more so that the resistance of the diffusion layer region is sufficiently lowered and there is no inconvenience in growing the metal film or the metal silicide film. I won't. Therefore, arsenic ions of 3 × 10 ¹⁵ / cm ² are implanted at 20 keV through a 10 nm thick oxide film.

[0005]

In the MOS type transistor formed by the conventional technique, the junction leakage current at the end of the locos is large, which may cause problems such as deterioration of operating characteristics of the transistor and increase of power consumption. Interface between silicon and field oxide at the end of locos,
Crystal defects are likely to be formed in the so-called bird's beak portion during locos formation. It is considered that the junction leakage current increases as a result of the formation of crystal defects at the junction interface. Therefore, as a method of reducing the junction leakage current, a method of forming the junction interface at a position deeper in the silicon substrate than the crystal defects can be considered. However, when the junction is deepened in the conventional technique, the short channel resistance deteriorates. As described above, it is difficult to reduce the junction leak current at the end of the locos without degrading the short channel resistance by the conventional technique.

An object of the present invention is to provide a MOS transistor in which the junction leakage current at the end of the locos is reduced without deteriorating the short channel resistance, and a manufacturing method thereof.

[0007]

In order to achieve the above object, the present invention provides a MOS transistor in which a silicon film having a facet at a locus end portion on a diffusion layer formation region is formed by a selective growth method such as a selective epitaxial growth method. After the formation, an impurity layer whose cross-sectional shape reflects the facet shape is formed by an ion implantation step and a heat treatment step.

[0008]

When the silicon film is selectively grown on the region where the diffusion layer is to be formed, facets can be formed at the ends of the locos. Facets composed of (111) planes and (311) planes are formed near the boundary between the field oxide film at the end of the locos and the region where the diffusion layer is to be formed. In this case, since the field oxide film at the end of the locos is clean as compared with the other insulating films, the facet can be formed only at the end of the locos without forming on the side wall of the gate electrode. By implanting impurities into the silicon substrate through the silicon film having this facet, an impurity layer can be formed at a position deeper than the other parts at the locos end. According to this method, it is possible to form a junction interface at a position deeper than the crystal defect at the locos end, while keeping the junction at a portion other than the locos end shallow. Therefore, it is possible to reduce the junction leakage current at the locos end portion without deteriorating the short channel resistance.

[0009]

【Example】

(Embodiment 1) A first embodiment in which a MOS transistor is formed according to the present invention will be described. 1A to 1C are cross-sectional views showing an embodiment in the order of steps.

As shown in FIG. 1A, p-type (100)
A 20 nm thick pad oxide film on the silicon substrate 1 of
A 0 nm thick silicon nitride film was formed. Then, the silicon nitride film other than on the diffusion layer formation planned region was removed by the photolithography technique and the dry etching technique. Further, it was oxidized in a wet oxygen atmosphere at 1000 ° C. to form a locos field oxide film 2.

As shown in FIG. 1B, a gate oxide film 3 having a thickness of 5 nm and a polysilicon film 4 having a thickness of 200 nm to which phosphorus (P) has been added are formed by a low pressure CVD method. And
The polysilicon film 4 was processed into a gate electrode shape having a gate length of 200 nm by an electron beam lithography technique and a dry etching technique. Subsequently, arsenic was ion-implanted into the diffusion layer formation planned region. Here, 1 × 10 ¹⁴ / cm ² arsenic ions were implanted at 15 keV through a 10 nm thick oxide film.

As shown in FIG. 1C, high temperature (750
A silicon oxide film 5 was formed by a thermal CVD method, and a gate sidewall spacer was formed by a dry etching technique. After that, a 50 nm-thick silicon film 6 was selectively epitaxially grown on the diffusion layer formation planned region. As shown in an enlarged view in FIG. 3, facets 7 were formed at the locos end portions of the silicon film 6. The silicon film contains 100 sccm of dichlorosilane (SiH ₂ Cl ₂ ) gas and hydrogen chloride (HC
l) gas is 10 sccm, hydrogen (H ₂ ) gas is 1000 sccm,
The film formation temperature was 750 ° C., the film formation pressure was 100 Pa, and the film formation time was 5 minutes. At the same time, a polysilicon film having a thickness of 50 nm was further laminated on the polysilicon film 4 of the gate electrode.

Subsequently, arsenic was implanted into the diffusion layer formation planned region by the second ion implantation. Here 3 100keV through oxide film of 10nm thickness × 10 ¹⁵ /
A cm ² arsenic ion was implanted. Then, heat treatment was performed in a nitrogen atmosphere at 800 ° C. to form a diffusion layer 8 having an LDD structure.

As shown in FIG. 1D, a first layer wiring was formed. 600 by the CVD method using TEOS as a raw material
After forming the silicon oxide film 9 having a thickness of nm, a connection hole is formed by electron beam lithography and dry etching, and a sputter method and a blanket (overall growth) are formed on the connection hole.
The tungsten film 10 formed by the CVD method was processed into a wiring shape by the photolithography technique and the dry etching technique. After that, the second layer and the third layer wiring were formed. Here, the same method as that for the first layer wiring was used, but the silicon oxide film had a thickness of 400 nm, and the third layer wiring used the aluminum film 11 formed by the sputtering method instead of the tungsten film. The connection hole between the second-layer wiring and the third-layer wiring was filled with the tungsten plug 12 formed by the selective CVD method.

In order to examine the cross-sectional shape of the impurity layer in the silicon substrate, etching was performed using a mixed solution of hydrofluoric acid and nitric acid. As a result, as shown in FIG. 3, the cross-sectional shape of the impurity layer had a structure that reflected the facets 7 at the locos end of the silicon film 6 selectively epitaxially grown. The junction depth is 50 nm in the lower part of the gate electrode, the end of the locos and the other part of the diffusion layer,
It was 150 nm and 100 nm.

For comparison, the cross-sectional shape of the impurity layer according to the conventional technique is shown in FIG. The junction depth from the surface of the silicon substrate is the same in both figures except for the locos end portion. On the other hand, at the end of the locos, the junction in FIG. 3 according to the present invention is deeper by the amount corresponding to the film thickness of the silicon film 6 than in FIG. 4 according to the conventional technique. As a result, according to the present invention, the junction leakage current at the end of the locos was reduced as compared with the conventional case.

In this embodiment, an N-channel type transistor has been described as an example of a MOS type transistor, but it can be similarly applied to a P-channel type transistor and further to a CMOS type transistor.

In this embodiment, a (100) -oriented silicon substrate is used, but this is because facets composed of (111) planes and (311) planes are formed, and impurities can be implanted deeper into the locos end by ion implantation. Is.

In this embodiment, the selective epitaxial growth method is used as the selective growth method for the silicon film 6, but a selective growth method for polycrystalline silicon may be used instead. However, the selective epitaxial growth method is the best in terms of facet orientation controllability.

In this embodiment, the LDD structure is formed by performing the ion implantation twice, but the first ion implantation can be omitted. However, in this case, since the lower portion is not made low in resistance, in order to operate the MOS type transistor at high speed, the thickness of the gate sidewall spacer (thickness in the horizontal direction with respect to the silicon substrate 1) is made thin. Ingenuity is needed.

(Embodiment 2) A second embodiment in which a MOS transistor is formed according to the present invention will be described. FIG. 5 is a sectional view showing an embodiment.

According to the method described in Example 1, p-type (10
A gate electrode composed of Locos field oxide film 2, gate oxide film 3 and polysilicon film 4 was formed on the silicon substrate 1 of 0), and arsenic was ion-implanted into the diffusion layer formation planned region. Then, a gate sidewall spacer made of the silicon oxide film 5 is formed by the high temperature thermal CVD method, and 50n having a facet at the end of the locos is formed on the diffusion layer formation planned region.
A m-thick silicon film was selectively epitaxially grown. Further, arsenic was implanted into the diffusion layer formation planned region by the second ion implantation, and then the diffusion layer 8 having the LDD structure was formed by heat treatment.

Then, the entire surface of the substrate is sputtered to form 2
A titanium (Ti) film having a thickness of 0 nm was formed. By heat treatment, silicon was reacted with the titanium film to form a titanium silicide film 13 having a thickness of 10 nm. Heat treatment is RTA (R
650 in nitrogen atmosphere by apid Thermal Annealing method
It carried out for 30 second on (degreeC) condition. By this heat treatment, the titanium silicide film was formed in a self-aligned manner only on the selectively epitaxially grown silicon film 6 and the gate electrode.

Subsequently, the unreacted titanium film was removed by wet treatment. The wet treatment is ammonia (N
H ₃ ), hydrogen peroxide (H ₂ O ₂ ) and water were mixed at a ratio of 1: 1/5, and the mixture was heated at 60 ° C. for 5 minutes. Further, by heat treatment, the resistance of the titanium silicide film 13 was lowered. This heat treatment was performed for 30 seconds under the condition of 750 ° C. in an argon (Ar) atmosphere by the RTA method.

After that, the first layer, the second layer and the third layer wiring were formed by the method described in Example 1.

In this embodiment, the titanium silicide film is used as the metal silicide film, but a cobalt silicide film or a nickel silicide film can be used instead.

Conventionally, when a metal silicide film is formed on a diffusion layer, a reaction between silicon and a titanium film occurs particularly violently at the end of locos, causing a problem that a junction is broken or a junction leak current increases. There was an occasion. By deepening the junction at the locos end according to this example, the destruction of the junction and the increase of the junction leakage current were suppressed.

(Embodiment 3) A third embodiment in which a MOS transistor is formed according to the present invention will be described. FIG. 6 is a sectional view showing an embodiment.

By the method described in Example 1, p-type (10
A gate electrode composed of Locos field oxide film 2, gate oxide film 3 and polysilicon film 4 was formed on the silicon substrate 1 of 0), and arsenic was ion-implanted into the diffusion layer formation planned region. Then, a gate sidewall spacer made of the silicon oxide film 5 is formed by the high temperature thermal CVD method, and 50n having a facet at the end of the locos is formed on the diffusion layer formation planned region.
A m-thick silicon film was selectively epitaxially grown. Further, arsenic was implanted into the diffusion layer formation planned region by the second ion implantation, and then the diffusion layer 8 having the LDD structure was formed by heat treatment.

After that, a 50 nm tungsten film 14 was deposited on the diffusion layer and the gate electrode in a self-aligned manner by a selective CVD method. At the time of forming the tungsten film 14, monosilane (SiH ₄ ) and tungsten hexafluoride (WF ₆ ) are fed as a source gas at a ratio of 1: 2, and the substrate temperature is set to 28.
It was set to 0 ° C.

After that, the first layer, the second layer, and the third layer wiring were formed by the method described in Example 1.

Conventionally, when a tungsten film is formed on a diffusion layer, there is a problem that so-called encroachment occurs, in which the tungsten film is partially eroded by silicon. Encroachment is prominent at the locos end, and the junction may be broken or the junction leakage current may increase. As a result of deepening the junction at the locos end according to this example, no problems such as destruction of the junction and increase of junction leakage current occurred.

[0033]

According to the present invention, it is possible to reduce the junction leakage current at the end of the locos without deteriorating the short channel resistance, and to miniaturize the MOS type transistor, improve the operating speed, and reduce the power consumption. It is possible.

[Brief description of drawings]

FIG. 1 is a sectional view of a MOS transistor showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view of a MOS transistor showing a conventional technique in the order of steps.

FIG. 3 is a cross-sectional view of a locos end formed according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view of a locos end formed by a conventional technique.

FIG. 5 is a sectional view of a MOS transistor showing a second embodiment of the present invention.

FIG. 6 is a sectional view of a MOS transistor showing a third embodiment of the present invention.

[Explanation of symbols]

1 ... Silicon substrate, 2 ... Locos field oxide film, 3
... gate oxide film, 4 ... polysilicon film, 5 ... high temperature thermal CV
Silicon oxide film by D method, 6 ... Silicon film selectively grown epitaxially, 7 ... Facet, 8 ... Diffusion layer, 9
... Silicon oxide film, 10 ... Tungsten film wiring, 11 ... Aluminum film wiring, 12 ... Tungsten plug.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/78 301R (72) Inventor Akihiro Miyauchi 7-1 Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Hitachi Research Laboratory, Hitachi Ltd.

Claims (8)

[Claims] 1. A structure in which a selectively grown silicon film is stacked on a diffusion layer formation scheduled region of a MOS transistor, wherein the silicon film is located at a LOCOS (LOCal Oxidised Silicon) end portion of the diffusion layer formation scheduled region. A semiconductor device having a facet and having a structure in which a cross-sectional shape of an ion-implanted impurity layer reflects the shape of the facet. 2. The semiconductor device according to claim 1, having a structure in which a metal silicide film is stacked on the silicon film in a self-aligned manner. 3. The semiconductor device according to claim 2, wherein the metal silicide film is a titanium silicide film, a cobalt silicide film or a nickel silicide film. 4. The semiconductor device according to claim 1, having a structure in which a refractory metal film is stacked on the silicon film in a self-aligned manner. 5. The semiconductor device according to claim 4, wherein the refractory metal film is a tungsten film. 6. The semiconductor device according to claim 1, wherein the silicon film is selectively epitaxially grown silicon. 7. The semiconductor device according to claim 1, wherein the diffusion layer formation planned region is made of (100) -oriented single crystal silicon. 8. The method of claim 1, 2, 3, 4, 5, 6 or 7, wherein a step of selectively growing a silicon film, a step of ion-implanting impurities, and a heat treatment step for activating the impurities are performed. A method for manufacturing a semiconductor device, comprising: