JPH0822264A - Multi-level output circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption and to increase a data transfer speed by using a digital circuit as an output circuit not an analog circuit. CONSTITUTION:This circuit is provided with input terminals 1-8, an output terminal 9 and liquid crystal drive potential input terminals 10-14, and the output terminal 9 is connected to a liquid crystal panel 100 being a display device. Then, a decoder circuit 17 outputs a driving data signal, and is connected to a level shift circuit 18. The level shift circuit 18 is connected to the output circuit 19 to which the liquid crystal drive potential input terminals 10-14 and the output terminal 9 are connected. At this time, an analog switch in the output circuit 19 transmits a signal with the drive potential of the display device 100 to the output terminal 9 in response to the driving data signal from the circuit 17. That is, the analog switch outputs the drive potential of the display device 100 in digital.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driver circuit for driving a display device such as a liquid crystal panel, and more particularly to a multi-gradation output circuit capable of driving the display device with multiple gradations.

[0002]

2. Description of the Related Art A conventional multi-gradation output circuit is disclosed in, for example, Japanese Patent Laid-Open No. 5-94159. This conventional multi-gradation output circuit is disclosed in column 7, line 14 to column 8 of the publication.
TFT as described in column 44, line and FIG.
As a circuit for driving the liquid crystal panel 1, a video RAM 5,
RAM 7, display controller 30, inversion / non-inversion circuit 3
1. A display data output circuit including a shift register 32, a data latch circuit 34, and a level shifter circuit 35, and a DA converter circuit 36 which is an output circuit.

[0003]

However, in the multi-gradation output circuit having the above structure, the liquid crystal driving digital display data signal is converted by the DA converter 36 into the TF.
There is a problem that the power consumption increases because the analog liquid crystal drive signal is applied to the pixels of the T liquid crystal panel. In particular, this problem becomes remarkable when the liquid crystal drive voltage becomes high.

[0004]

According to the present invention, in order to solve the above problems, a multi-gradation output circuit is provided with a predetermined length based on display data input from a plurality of input terminals and a signal for timing generation. Drive data output circuit which outputs a plurality of drive data signals having a pulse waveform of a length from its output terminal, and its input is connected to any one of a plurality of drive potential input terminals, and its output is a drive potential A plurality of analog switches each having a control input connected to an output terminal and having a control input connected to any one of the output terminals of the drive data output circuit, and a plurality of different display device drive potentials from the plurality of drive potential input terminals; And a signal having a plurality of different display device drive potentials is output for a predetermined time by operating the analog switch based on the drive data signal. It was composed of the output circuit for.

[0005]

The analog switch transmits the signal having the display device drive potential to the output terminal in response to the drive data signal.
That is, the analog switch digitally outputs the display device drive potential.

[0006]

1 is a block diagram showing a multi-gradation output circuit according to an embodiment of the present invention. This multi-gradation output circuit has input terminals 1, 2, 3, 4, 5, 6, 7, and 8, an output terminal 9 and liquid crystal drive potential input terminals 10, 11, 12, 13, and 14. The output terminal 9 is a liquid crystal panel 1 which is a display device.
00 is connected.

The input terminals 1, 2, 3, 4, 5, 6 and 8 are connected to the latch circuit 15, and the input terminal 8 is also connected to the coincidence circuit 16 and the timing circuit 20. The input terminal 7 is connected to the timing circuit 20. Latch circuit 15
The timing circuit 20 is connected to the coincidence circuit 16, and the coincidence circuit 16 is connected to the decoder circuit 17. The latch circuit 15, the timing circuit 20, the coincidence circuit 16, and the decoder circuit 17 constitute a drive data output circuit that outputs drive data. That is, the decoder circuit 17 outputs the driving data signal. The decoder circuit 17 is connected to the level shift circuit 18, and the level shift circuit 1
8 is a liquid crystal drive potential input terminal 10, 11, 12, 13, 1
4 and the output terminal 9 are connected to the output circuit 19. Next, the multi-gradation output circuit of one embodiment of the present invention will be specifically described.

FIG. 2 is a circuit diagram specifically showing a multi-gradation output circuit according to an embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. Latch circuit 1
The data inputs D1, D2, D3, D4, D5 and D6 of 5 are connected to the input terminals 1, 2, 3, 4, 5 and 6, respectively, and the L terminal thereof is connected to the input terminal 8. The latch circuit 15 further outputs data outputs Q1, Q2, Q3, Q4, Q.
5 and Q6. FIG. 3 shows the latch circuit 1 of this embodiment.
5 is a specific circuit diagram of FIG. As can be seen from FIG. 3, the latch circuit 15 includes the first to sixth flip-flops 151, 1
52, 153, 154, 155, 156. Each flip-flop 151, 152, 153,
Data inputs D of 154, 155 and 156 are data inputs D1, D2, D3, D4 and D of the latch circuit 15, respectively.
It becomes 5, D6. Each flip-flop 151, 152,
The L terminals of 153, 154, 155, and 156 are commonly connected to the L terminal of the latch circuit 15. In addition, each flip-flop 151, 152, 153, 154, 155,
The data output Q of 156 becomes the data outputs Q1, Q2, Q3, Q4, Q5, Q6 of the latch circuit 15, respectively.

The timing circuit 20 is composed of an up counter with a reset, which counts up at the falling edge of the clock. The input terminal 7 is connected to the clock terminal CK of the timing circuit 20 and its reset terminal R
An input terminal 8 is connected to. Furthermore, the timing circuit 20 has counter outputs O1, O2, O3, O4.

FIG. 4 is a specific circuit diagram showing the timing circuit 20 of this embodiment. The timing circuit 20 includes first to fourth flip-flops 201 and 20 with reset.
It is composed of 2, 203, and 204. Here, each flip-flop 201, 202, 203, 204 has a data input D, a data output Q, a clock input CK and a reset input R, respectively. Input terminal 7 is the first
Connected to the clock input CK of the flip-flop 201. The input terminal 8 is each flip-flop 201, 2
Commonly connected to the reset inputs R of 02, 203, and 204. The data output Q of the first flip-flop 201 is its data input D and the second flip-flop 2
02 is connected to the clock input CK and also serves as the counter output O1 of the timing circuit 20. Similarly, the data output Q of the second flip-flop 202 is connected to its data input D and the clock input CK of the third flip-flop 203, and serves as the counter output O2 of the timing circuit 20. The data output Q of the third flip-flop 203 is connected to its data input D and the clock input CK of the fourth flip-flop 204, and serves as the counter output O3 of the timing circuit 20. The data output Q of the fourth flip-flop 201 is connected to the data input D thereof, and also serves as the counter output O4 of the timing circuit 20.

The coincidence circuit 16 is a 2-input OR circuit (hereinafter, referred to as 2
Abbreviated as OR) 21, 22, 23, 24 and 5-input NAND
A circuit (hereinafter abbreviated as 5 NAND) 25, an inverter (hereinafter abbreviated as INV) 26, and a 2-input NAND circuit (hereinafter abbreviated as 2 NAND) 27, 28.

The data output Q3 of the latch circuit 15 is 2OR.
21 is connected to one input, and the other input of the 2OR21 is connected to the counter output O4 of the timing circuit 20. The data output Q4 of the latch circuit 15 is 2OR22.
The counter output O3 of the timing circuit 20 is connected to the other input of the 2OR22. The data output Q5 of the latch circuit 15 is connected to one input of the 2OR23, and the counter output O2 of the timing circuit 20 is connected to the other input of the 2OR23.
The data output Q6 of the latch circuit 15 is connected to one input of the 2OR24, and the counter output O1 of the timing circuit 20 is connected to the other input of the 2OR24.

The outputs of the 2ORs 21, 22, 23, and 24 are connected to the first, second, third, and fourth inputs of the 5NAND 25, and the input terminal 7 is connected to the fifth input of the 5NAND 25. . The output of 5NAND25 is 2NA
The output of the 2NAND 28 is connected to one input of the ND 27 and the other input of the 2NAND 27.
The input terminal 8 is connected to the input of the INV 26, and the output thereof is connected to one input terminal of the 2NAND 28.
The output of the 2NAND 27 is connected to the other input of the 2NAND 28.

The decoder circuit 17 includes INVs 29, 32, 2
Input EOR circuit (hereinafter, abbreviated as 2EOR) 30, 31,
33, 34, 2-input AND circuit (hereinafter, abbreviated as 2AND) 35, 36, 37, 3-input AND circuit (hereinafter, 3A)
ND) 38 and 4-input NOR circuit (hereinafter, 4NO)
(Abbreviated as R) 39.

The data output Q1 of the latch circuit 15 is INV.
29 inputs, one input of 2EOR31, 2AND37
Connected to one input and the first input of the 3AND38. The latch circuit 15 is connected to the other input of the 2EOR 31.
Data output Q2 of 2EOR34 is connected to the other input of 2AND37. 3 AND
The output of the 2NAND 27 and the data output Q2 of the latch circuit 15 are connected to the second and third inputs of 38, respectively. The data output Q2 of the latch circuit 15 is further 2EO
One input of R30, input of INV32 and 2EOR
34 is connected to one input. The output of the INV 32 is connected to one input of the 2EOR 33. 2E
2 NAND27 is provided to the other input of OR 30, 33, and 34.
The output of is connected. The output of INV29 is 2 AND
The output of the 2EOR 30 is connected to the other input of the 2AND 35. 2EOR
The output of 31 is connected to one input of 2AND36,
The input of the 2EOR 33 is connected to the other input of the AND 36.

The level shift circuit 18 has first to fifth inputs I1, I2, I3, I4 and I5 and first to fifth outputs R1 for level-converting and outputting the signals respectively inputted to these inputs. It has R2, R3, R4, and R5.

FIG. 5 is a partial circuit diagram (a circuit diagram for 1 bit) of the concrete level shift circuit 18. FIG. 5 is a circuit diagram showing a 1-bit circuit of the level shift circuit of this embodiment. This circuit includes first to fourth transistors 18
2, 183, 184, 185 and INV186. The first transistor 182 is composed of a PMOS transistor, the source of which is the high potential input terminal 18
1 (specifically, the liquid crystal drive potential input terminal 10). The second transistor 183 is also composed of a PMOS transistor, and its source is the high potential input terminal 181.
In addition, its gate is connected to the drain of the first transistor 182, its drain is connected to the gate of the first transistor 182, and is also connected to the output R of the level shift circuit 18.

The third transistor 184 is composed of an NMOS transistor, the source thereof is connected to the ground potential which is a low potential source, and the gate thereof is connected to the input I of the level shift circuit 18 and the input of the INV 186. . The drain of the third transistor 184 is connected to the drain of the first transistor 182. The fourth transistor 185 is also an NMOS transistor,
Its source is connected to the ground potential which is a low potential source, its gate is connected to the output of INV186, and its drain is connected to the drain of the second transistor 183.

Returning to FIG. 2, the description will be continued. 2 AND35
Is connected to the first input of the 4NOR 39 and the first input I1 of the level shift circuit 18. The output of 2AND36 is the second input of 4NOR39 and the level shift circuit 1
8 second input I2. The output of 2AND37 is the third input of 4NOR39 and the level shift circuit 18
Is connected to the third input I3 of. The output of 3AND38 is connected to the fourth input of 4NOR39 and the fourth input I4 of the level shift circuit 18. The output of the 4NOR 39 is connected to the fifth input I5 of the level shift circuit 18.

The output circuit 19 includes first to fifth analog switches (hereinafter abbreviated as analog SW) 40, 41 and 4.
It is composed of 2, 43 and 44. Here, each analog SW has a control input T, an input N and an output S.
The first output R1 of the level shift circuit 18 is the control input T of the first analog SW40, the second output R2 is the control input T of the second analog SW41, and the third output R3 is the control input of the third analog SW42. T, the fourth output R4 are connected to the control input T of the fourth analog SW43, and the fifth output R5 is connected to the control input T of the fifth analog SW44. First to fifth analog SWs 40, 41, 42,
First to fifth liquid crystal drive potential input terminals 13, 12, 11, 10 and 14 are connected to inputs N of 43 and 44, respectively. First to fifth analog SWs 40, 4
The outputs S of 1, 42, 43 and 44 are commonly connected to the output terminal 9.

A concrete example of the analog SW of this embodiment is shown in FIG. This analog SW is an NMOS transistor 61,
It is composed of a PMOS transistor 62 and an INV 63. The sources / drains of the NMOS transistor 61 and the PMOS transistor 62 are commonly connected to the input N and the output S of the analog SW, respectively. The control input T of the analog SW is connected to the gate of the NMOS transistor 61 and the input of the INV 63. INV6
The output of 3 is connected to the gate of the PMOS transistor 62.

The analog SW can be modified depending on the potential to be supplied, and can be composed of an NMOS transistor 71 as shown in FIG. 7 or an INV 81 and a PMOS transistor 82 as shown in FIG. .

Next, the operation of the multi-gradation output circuit of one embodiment of the present invention having the above structure will be described.
9 and 10 show input terminals 1, 2, 3, 4, 5, 6,
Input signal levels ("1" and "1" input to 7 and 8)
This is the waveform of the output signal output from the output terminal 9 for the expression 0).
When liquid crystal display data signals are input from 3, 4, 5 and 6, and the signal input from the input terminal 8 becomes "1", the input terminals 1, 2, 3, 4 are connected to the inputs D1 to D6 of the latch circuit 15.
Data from 5 and 6 are taken in, and signals are output from the outputs Q1 to Q6 of the latch circuit 15 to the matching circuit 16. The latch circuit 15 is provided while the input signal from the input terminal 8 is "0".
The signals output from the outputs Q1 to Q6 of the above are retained. The timing circuit 20 is counted up when the input signal input to the input terminal 7 falls, and is reset when the input signal from the input terminal 8 becomes "1".

When either the output Q3 of the latch circuit 15 or the output signal O4 of the timing circuit 20 is "1", the 2OR21 outputs a signal "1" from that output, and both output signals are "1". When it is "0", the signal "0" is output from the output. The 2ORs 22, 23, and 24 perform the same operation. Input signal input to the input terminal 7 and 20
When the output signals of R21, 22, 23, 24 are all "1", the output signal from 5NAND25 becomes "0",
Otherwise, the 5NAND 25 outputs the output signal "1". Since the signal from the input terminal 8 inverted by the INV 26 is input to one input of the 2NAND 28, when the signal from the input terminal 8 becomes “1”, IN
The output signal of V26 becomes "0", and the output signal of 2NAND28 becomes "1" regardless of the output signal of 5NAND25.

At this time, the output signal of the 5NAND 25 is "
The output signal of the 2NAND 27 becomes "0" because it becomes "1". After that, even if the signal from the input terminal 8 becomes "0", the 2NAND 2 outputs 2NAND while the output signal of the 5NAND 25 is "1".
The output signal of 28 becomes "1", and the output of 2NAND 27 becomes "0". The signal from the input terminal 7 and 2OR21,
When all the output signals of 22, 23, and 24 become "1", the output signal from the 5NAND 25 becomes "0", so 2
The output from the NAND 27 becomes "1". At this time, since the signal from the input terminal 8 is "0", 5NAND25
Even if the output signal of 1 becomes "1", the signal "1" is output from the 2NAND 27 while the signal from the input terminal 8 is "0".

FIG. 11 is a timing chart showing the relationship between the output signal waveform of the 2NAND 27 and the signal levels from the input terminals 3, 4, 5, and 6. As can be seen from this timing chart, the output signal waveform of the 2NAND 27 is input to the input terminal 7 in the section from when the signal input to the input terminal 8 becomes "1" to the next "1". The input terminals 3, 4, based on the waveform period of the signal
Signal waveforms having lengths corresponding to the signals (data) input to 5 and 6 are generated. That is, the signal (data) at the input terminal 6 is set to the least significant bit, and the signal (data) at the input terminal 3 is set.
2 NAND corresponding to the digital value with the most significant bit
The output signal of 27 has a fixed "1" period. In addition,
It is prohibited to set the input signals of the input terminals 7 and 8 to "1" at the same time.

Now, returning to FIG. 2, the relationship of the signal levels will be described while considering the input relationship of the signals of the multi-gradation output circuit of this embodiment. The output signal of 2NAND27 is 2EOR3
It is input to 0, 33, 34 and 3AND38. 2EOR
The output signal of the output Q2 of the latch circuit 15 is further input to 30. The output signal of the 2EOR 30 is input to the 2AND 35. The output signal of the INV 29 is further input to the 2AND 35. The output signal of the output Q1 of the latch circuit 15 is input to the INV 29.

Therefore, (1) when the input signal to the input terminal 1 is "0", the input signal to the input terminal 2 is "0", and the output signal of the 2NAND 27 is "1", or (2 ) When the input signal to the input terminal 1 is "0", the input signal to the input terminal 2 is "1", and the output signal of the 2NAND 27 is "0", the output signal of the 2AND35 is "1". Become. Similarly, the output signal of 2AND36 becomes "1" because (1) the input signal to the input terminal 1 is "1".
0 ", the input signal to input terminal 2 is" 1 "and 2NA
When the output signal of ND27 is "1" and (2) the input signal to input terminal 1 is "1", the input signal to input terminal 2 is "0", and the output signal of 2NAND27 is "0". This is the case.

Further, the output signal of 2AND37 is "1".
(1) The input signal to input terminal 1 is "1",
When the input signal to the input terminal 2 is “0” and the output signal from the 2NAND 27 is “1”, and (2) when the input signals to the input terminals 1 and 2 are both “1”, the output signal of the 2NAND 27 is “0”. Is the case. The output signal of the 3AND38 becomes "1" because (1) both the input signals to the input terminals 1 and 2 are "1", and the output signal of the 2NAND27 is "1".
This is the case of 1 ".

Each of the four inputs of the 4NOR 39 has a 2
The outputs of AND 35, 36, 37 and 3AND 38 are connected. Therefore, when both the input signals of the input terminals 1 and 2 are “0” and the output signal of the 2NAND 27 is “0”,
That is, when the output signals of 2AND35, 36, 37 and 3AND38 are all "0", the output signal of 4NOR39 is "
1 ”.

2AND35, 36, 37, 3AND38
And the outputs of 4NOR39 are the first to fifth inputs I1, I2, I3, I4 of the level shift circuit 18, respectively.
It is connected to I5. Therefore, 2AND35, 36,
37, 3AND38 and 4NOR39 output signal levels are set by the level shift circuit 18 to the decoder circuit 17
Output level (about 3V) to liquid crystal drive level (about 30V)
Boosted to V). The output R1 of the level shift circuit 18,
The output signals from R2, R3, R4, and R5 are "
When 1 ”, analog SW 40, 41, 42, 43, 44
Is turned on. From the above, the output signal value of the output terminal 9 has the following relationship. That is, when both input signals to the input terminals 1 and 2 are "0", (1) 2NAND2
When the output signal of 7 is "0", the output signal value of the output terminal 9 becomes the potential of the input signal of the liquid crystal drive potential input terminal 14,
(2) When the output signal of the 2NAND 27 is "1", the output signal value of the output terminal 9 becomes the potential of the input signal of the liquid crystal drive potential input terminal 13. If the input signals to the input terminals 1 and 2 are "0" and "1", respectively, (1) 2NAN
When the output signal of D27 is "0", the output signal value of the output terminal 9 becomes the potential of the input signal of the liquid crystal drive potential input terminal 13, and when the output signal of 2NAND27 is "1", the output signal value of the output terminal 9 Is the potential of the input signal of the liquid crystal drive potential input terminal 12. Further, when the input signals to the input terminals 1 and 2 are "1" and "0" respectively, "(1) 2NA
When the output signal of the ND27 is "0", the output signal value of the output terminal 9 becomes the potential of the input signal of the liquid crystal drive potential input terminal 12, and (2) when the output signal of the 2NAND27 is "1", the output terminal 9 is of the output terminal 9. The output signal value becomes the potential of the input signal of the liquid crystal drive potential input terminal 11. When the input signals to the input terminals 1 and 2 are "1" and "1" respectively, (1) 2N
When the output signal of the AND27 is "0", the output signal value of the output terminal 9 becomes the potential of the input signal of the liquid crystal drive potential input terminal 11, and (2) when the output signal of the 2NAND27 is "1", the output terminal 9 is of the output terminal 9. The output signal value becomes the potential of the input signal of the liquid crystal drive potential input terminal 10.

FIG. 12 shows a circuit diagram of a multi-gradation output circuit of another embodiment of the present invention. In FIG. 12, the same parts as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted.

In the multi-gradation output circuit of this embodiment, the output of the decoder circuit 17 is directly connected to the output circuit 19.
That is, this embodiment has a circuit configuration in which the level shift circuit 18 of the previously described embodiment is omitted. Output circuit 1
The analog SWs 40, 41, 42, 43, 4 constituting 9
It goes without saying that the level shift circuit 18 is not necessary if 4 operates sufficiently at the level of the output signal of the decoder circuit 17.

[0034]

As described above, according to the multi-gradation output circuit of the present invention, unlike the conventional circuit, since the output circuit uses the digital circuit instead of the analog circuit, the power consumption can be reduced. . Moreover, since all the circuit configurations are digital circuits, the data transfer rate can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of a multi-gradation output circuit according to an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of FIG.

FIG. 3 is a circuit diagram of the latch circuit of FIG.

FIG. 4 is a circuit diagram of the timing circuit shown in FIG.

5 is a circuit diagram of one bit of the level shift circuit of FIG.

6 is a circuit diagram of an example of the analog switch of FIG.

7 is a circuit diagram of another example of the analog switch of FIG.

8 is a circuit diagram of still another example of the analog switch of FIG.

FIG. 9 is a waveform diagram of the output signal from the output terminal 9 with respect to the level of the input signal to the input terminal.

FIG. 10 is a waveform diagram of the output signal from the output terminal 9 with respect to the level of the input signal to the input terminal (2).

FIG. 11 is a timing chart showing the relationship between the output signal waveform of the 2NAND 27 and the signal level from the input terminal.

FIG. 12 is a circuit diagram of a multi-gradation output circuit according to another embodiment of the present invention.

[Explanation of symbols]

1, 2, 3, 4, 5, 6, 7, 8 Input terminal 9 Output terminal 10, 11, 12, 13, 14 Liquid crystal drive potential input terminal 15 Latch circuit 16 Matching circuit 17 Decoder circuit 18 Level shift circuit 19 Output circuit 20 Timing circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshimitsu Fujisawa 4-2-1 Imabashi, Chuo-ku, Osaka City, Osaka Prefecture Oki SLS Technology Co., Ltd. Kansainai (72) Inventor Yasuhiro Shin, Minato-ku, Tokyo Toranomon 1-7-12 Oki Electric Industry Co., Ltd.

Claims (3)

[Claims] 1. A display having a plurality of input terminals for receiving display data for driving a display device and a signal for timing generation, a plurality of output terminals, and being input from the plurality of input terminals. A drive data output circuit that outputs a plurality of drive data signals having a pulse waveform of a predetermined length from the output terminal based on the data and the signal for generating the timing; and a plurality of drive potential input terminals. A drive potential output terminal and its input connected to one of the plurality of drive potential input terminals, and its output connected to the drive potential output terminal,
A signal having a plurality of analog switches whose control inputs are connected to any one of the output terminals of the drive data output circuit, and having the plurality of different display device drive potentials from the plurality of drive potential input terminals. And an output circuit that outputs a signal having a plurality of different display device drive potentials from the drive potential output terminal for a predetermined time by operating the analog switch based on the drive data signal. Multi-gradation output circuit. 2. The driving data output circuit is connected to the input terminal, temporarily holds the display data, receives a signal for generating the timing, and drives the driving circuit based on the signal. A timing circuit for outputting a signal for controlling the pulse width of the data signal for use, and connected to the latch circuit and the timing circuit,
A matching circuit that outputs an output signal in accordance with the matching relationship between the output signal of the latch circuit and the output signal of the timing circuit; and a matching circuit that is connected to the matching circuit and decodes the output of the matching circuit to generate the driving data signal. The multi-gradation output circuit according to claim 1, further comprising a decoder circuit. 3. A level shift circuit connected between the decoder circuit and the output circuit, the level shift circuit providing a signal obtained by converting a potential level of an output signal of the decoder circuit to the output circuit. Item 2. The multi-gradation output circuit according to item 2.