KR100848090B1 - A level shifter and a liquid crystal display using the same - Google Patents

Abstract

The liquid crystal display of the present invention includes a liquid crystal panel, a timing controller, and a power supply unit. The liquid crystal panel includes a level shifter, a gate driver, a source driver and a display. The level shifter receives a logic signal from the timing controller, applies a proper signal to the gate driver and the source driver, and is driven by voltages of Vpos and Vneg of the power supply unit. In particular, the level shifter according to the present invention has two inputs which are differential input stages using the structure of the differential amplifier. The gate driver receives a gate clock and a gate on enable signal from a level shifter and sequentially applies a gate on signal to the gate line in synchronization with the two signals. The source driver receives a data signal synchronized with the driving of the gate driver from the level shifter and applies it to all data lines. The display unit includes a plurality of pixel regions in which a plurality of gate lines and a plurality of data lines cross each other to form a matrix. The display unit displays an image for each frame by receiving a data voltage and a gate-on signal output from the gate driver and the source driver. )do.

Description

Level shifter and a liquid crystal display using the same

1 illustrates a structure of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a level shifter according to a first embodiment of the present invention.

FIG. 3 is a waveform diagram of a main part signal of the circuit shown in FIG.

4 is a level shifter according to a second embodiment of the present invention.

FIG. 5 is a waveform diagram of signals of main parts of the circuit shown in FIG.

6 is a level shifter according to a third embodiment of the present invention.

7 is a level shifter according to a fourth embodiment of the present invention.

The present invention relates to a liquid crystal display, and more particularly, to a level shift circuit and a liquid crystal display using the same.

In the liquid crystal display, a plurality of pixel regions formed by crossing a plurality of gate lines and a plurality of data lines is formed in a matrix form, and a data signal and a gate-on signal are applied to each gate line and data line to display an image for each frame. Display.

In general, a liquid crystal display includes a liquid crystal panel for receiving a data signal and a gate on signal to display an image for each frame, a gate driver for supplying the gate on signal to each gate line of the liquid crystal panel, and transmitting the data signal to the liquid crystal panel. And a level shifter for shifting a signal having a level suitable for the gate driver, the source driver, and the like.

Here, the level shifter receives a digital signal from an external timing controller and shifts the digital signal to an appropriate level to provide the gate driver and the source driver.

The conventional level shifter receives a logic signal swinging between a ground potential and a level of about 3V from the timing control, and level shifts to a positive voltage (hereinafter, referred to as a positive level shifter) and a negative voltage. It is separated into a part for level shifting (negative voltage shifter) with (negative voltage).

A positive level shifter amplifies the logic signal swinging between 0V and 3V only to a positive level to generate an output (e.g., an output swinging between 0V and 10V), and a negative level shifter to produce the positive level shifter. By taking the output of the signal as an input signal and amplifying only the negative level to generate an output (for example, an output swinging between -6V to 10V), the level shift is performed with a signal having a level suitable for the source driver and the gate driver.

As described above, the conventional level shifter has a large circuit volume problem because the positive level shifter and the negative level shifter are separated.

In particular, in the structure in which the gate driver and the source driver are mounted inside the liquid crystal panel by chip on glass (COG), the volume of the level shifter is large, and thus it is difficult to be mounted together on the liquid crystal panel.

On the other hand, such a conventional level shifter may cause a malfunction. For example, when the input terminal of the positive level shifter is an NMOS transistor and the input terminal of the negative level shifter is composed of a PMOS transistor, the positive level shifter is an N. When the threshold voltage of the MOS transistor is higher than the high level of the logic signal, it does not operate, and the negative level shifter does not operate when the threshold voltage of the PMOS transistor is above the high level of the logic signal. Therefore, a method of improving the input terminal of the positive level shifter of the level shifter has also been developed to improve the inoperability problem caused by the threshold voltage. However, such a method also has a problem that the volume of the level shifter becomes larger.

Therefore, an object of the present invention is to solve the above-mentioned conventional problems, and to provide a level shifter that operates reliably while reducing volume. In addition, another object of the present invention is to provide a liquid crystal display device using such a level shifter.

A liquid crystal display of the present invention for achieving the above object comprises a timing controller for generating a logic signal; A display unit having a plurality of gate lines, a plurality of data lines intersecting the gate lines, a pixel area formed in an area where the gate lines and the data lines intersect, and displaying an image for each frame; A gate driver driven according to an applied signal to supply a gate driving voltage to the gate line; A source driver configured to supply a data signal to the data line in synchronization with driving of the gate driver according to an applied signal; And a level shifter which is driven by a positive level voltage and a negative level voltage applied from the outside, and level shifts a logic signal output from the timing controller to output the gate driver and the source driver. The level shifter may differentially amplify and output the first input signal of the logic signal and the second input signal of the logic signal.

Here, the level shifter may include a first transistor configured to receive the first input signal; A second transistor connected to the first transistor through a common drain, and a third transistor connected to the second transistor through a common gate, wherein the common gate of the second and third transistors includes the first and the second transistors; A current mirror unit connected to the common drain of two transistors; And a fourth transistor connected to the third transistor through a common drain to receive a second input signal, wherein the source of the first to fourth transistors is externally applied to the negative level voltage or the positive voltage. It is preferable that a differentially amplified output signal of the first input signal and the second input signal is generated through a common drain of the third and fourth transistors.

In this case, the first input signal may be a square wave swinging between the ground potential and the first potential, and the second input signal may be an inverted signal of the first input signal.                     

The first input signal may be a square wave swinging between a ground potential and a first potential, and the second input signal may be a reference voltage for supplying an average voltage of the first input signal to a predetermined level.

The method may further include a fifth transistor having a drain connected to a source of the first and fourth transistors and operating according to a control signal applied to a gate to control turn-off of the first and fourth transistors. desirable.

Here, the first, fourth and fifth transistors are PMOS transistors, the second and third transistors are NMOS transistors, and the source of the PMOS transistor is applied from the outside. The NMOS transistor may be coupled to a positive level voltage applied from an external source.

The first, fourth, and fifth transistors are NMOS transistors, the second and third transistors are PMOS transistors, and the source of the PMOS transistor is connected to a negative level voltage applied from the outside. Coupled, the source of the NMOS transistor may be coupled with a positive level voltage applied from the outside.

The level shifter of the present invention, which level shifts a logic signal provided from a timing controller of a liquid crystal display and applies the gate driver and a source driver, includes: a first transistor configured to receive a first input signal of the logic signal; A second transistor connected to the first transistor through a common drain, and a third transistor connected to the second transistor through a common gate, wherein the common gate of the second and third transistors includes the first and the second transistors; A current mirror unit connected to the common drain of two transistors; And a fourth transistor connected to the third transistor and a common drain and receiving a second input signal of the logic signal, wherein the source of the first to fourth transistors is applied from an external level. Preferably, a differentially amplified output signal of the first input signal and the second input signal is generated through a common drain of the third and fourth transistors, coupled to a voltage or the positive level voltage.

At this time, the drain is connected to the source of the first and the fourth transistor, and further comprising a fifth transistor for controlling the turn-off of the first and fourth transistor by operating in accordance with a control signal applied to the gate. desirable.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 illustrates a structure of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the liquid crystal display of the present invention includes a liquid crystal panel 100, a timing controller 200, and a power supply unit 300.

The level shifter 110, the gate driver 120, the source driver 130, and the display 140 are formed in the liquid crystal panel 100. In the exemplary embodiment of the present invention, a liquid crystal display device having a COG structure has been described as an example, but the present invention is not limited thereto, and the present invention can be equally applied to a liquid crystal display device in which each driver and a level shifter are not formed on the liquid crystal panel.

The level shifter 110 receives a logic signal from the timing controller 200, applies a proper signal to the gate driver 120 and the source driver 130, and is driven by voltages of Vpos and Vneg of the power supply 300. . In particular, the level shifter according to the present invention has two inputs which are differential input stages using the structure of the differential amplifier. Here, the logic signal includes a clock signal and a start signal, and refers to all digital signals for driving the gate driver and the data driver.

The gate driver 120 receives a gate clock and a gate on enable signal from the level shifter 110 and sequentially applies a gate on signal to the gate line in synchronization with the two signals.

The source driver 130 receives a data signal synchronized with the driving of the gate driver 120 from the level shifter 110 and applies it to all data lines.

The display unit 140 includes a plurality of pixel areas in which a plurality of gate lines and a plurality of data lines cross each other to form a matrix, and a data voltage and a gate-on signal output from the gate driver 120 and the source driver 130. Is applied to display an image for each frame.

Next, the level shifter 110 of the liquid crystal display according to the present invention will be described in more detail.

FIG. 2 is a level shifter according to a first embodiment of the present invention, and FIG. 3 is a waveform diagram of main part signals of the circuit shown in FIG.

As shown in FIG. 2, the level shifter according to the first embodiment of the present invention includes three NMOS transistors M1, M4, and M5 and two PMOS transistors M2 and M3.

The NMOS transistors M1 and M4 serve as input terminals of the differential amplifiers, and receive the input signal IN and the input inversion signal INB as shown in FIG. 2 to receive the NMOS transistors M4 and PMOS. The output signal OUT is generated through the common drain of the transistor M3.

A drain of the NMOS transistor M1 and a drain of the PMOS transistor M2 are connected, and an input inversion signal INB is applied to a gate terminal of the NMOS transistor M1.

PMOS transistors M2 and M3 have their respective gates connected in common and are connected to a common drain of PMOS transistor M2 and NMOS transistor M1. In addition, the source terminal of the PMOS transistors M2 and M3 is connected to the positive level voltage Vpos of the external voltage supply unit.

The drain of the PMOS transistor M3 is connected to the drain of the NMOS transistor M4, and an input signal IN is applied to the gate terminal of the NMOS transistor M4.

Each source terminal of the NMOS transistors M1 and M4 is connected together to be connected to the drain of the NMOS transistor M5. The source terminal of the NMOS transistor M5 is connected to the negative level voltage Vneg of the external voltage supply unit. In addition, a mode signal Mode is applied to the gate terminal of the NMOS transistor M5. The mode signal Mode is a control signal for applying the 0V in the standby mode state so that the level shifter does not operate.

The operation of the level shifter according to the first embodiment of the present invention will be described.                     

First, the NMOS transistor M1 receives an input inversion signal INB, which is a square wave signal generated from a timing controller, through the gate terminal to conduct a first current to the drain. Here, the input inversion signal INB is a signal in which the input signal IN described later is inverted.

In the NMOS transistor M1 and the PMOS transistor M2, drains are connected to flow the same current, and the first current is connected to the PMOS transistors M2 and M3 connected to a common gate to form a current mirror. It also flows to the drain of the transistor M3.

In addition, an input signal IN is applied to the gate terminal of the NMOS transistor M4 to conduct a second current to the drain. In this case, the output current OUT is generated by combining with the first current flowing in the drain of the radiated PMOS transistor M3. Here, the input signal IN is a signal of a square wave generated by the timing controller, and swings between a ground potential and a voltage level of about 3V. In addition, the output voltage OUT swings between a positive voltage level Vpos connected to the source terminal of the PMOS transistor M3 and a negative voltage level Vneg connected to the source terminal of the NMOS transistor M4. do. Here, the signals of the positive voltage level Vpos and the negative voltage level Vneg are signals output from an external voltage supply unit, and Vpos is about 10V and Vneg has a level of about -6V.

On the other hand, since the source terminals of the NMOS transistors M1 and M4 are connected to the negative voltage Vneg, when the threshold voltages of the NMOS transistors M1 and M4 are Vthn, Vthn <| Vneg | When the equation is satisfied, the level shifter may be operated to improve the problem caused by the change of the threshold voltage Vthn, which has been a problem in the related art.

When the level shifter does not need to operate, such as in a standby mode, 0V may be applied to the gate of the NMOS transistor M5 for control.

That is, the level shifter according to the first embodiment of the present invention inputs the input signal IN and the input inverted signal INB to both ends of the input of the differential amplifier by using the principle of the differential amplifier. Amplify the difference between

As shown in FIG. 3, the input signal IN is a square wave swinging between a ground potential and a voltage level of about 3V, and the input inversion signal INB is a signal in which the input signal IN is inverted. When the difference between the input signal IN and the input inverted signal INB is 0V or more, the output signal OUT of the differential amplifier has a valid state, and the swing of the output signal OUT is a positive voltage that is a voltage source of the differential amplifier. Swing at level Vpos to negative voltage level Vneg.

The level shifter according to the first embodiment of the present invention forms a circuit with only five transistors, so that the area occupied by the circuit can be reduced, and malfunctions due to threshold voltage variations can be prevented. In addition, power consumption can be reduced by not operating in the standby mode.

Next, a second embodiment of the present invention will be described with reference to FIGS. 4 and 5.

4 is a level shifter according to a second embodiment of the present invention, and FIG. 5 is a waveform diagram of main part signals of the circuit shown in FIG.

As shown in FIG. 4, the level shifter according to the second embodiment of the present invention has the same structure as the first embodiment of the present invention, and is provided only at the gate end of the NMOS transistor M1, which is an input terminal of the differential amplifier. The only difference is that a reference voltage level (Vref) is applied, not the input inversion signal INB. Here, the reference voltage Vref is an average voltage of the input signal IN, as shown in FIG. 4, and is a DC voltage of a predetermined level. This can reduce the number of input signals that must be applied outside the panel when the LCD panel has multiple level shifts.

In other words, in general, an LCD panel has a built-in multiple level shift and inputs a square wave signal having a different timing at each level shift to an input terminal. A second embodiment of the present invention provides a reference voltage Vref, which is a DC voltage. The same reference voltage Vref may be applied to each level shift by inputting instead of the input inversion signal INB.

Therefore, the second embodiment of the present invention not only has the same effect as the first embodiment, but also has the advantage of reducing the number of input signals.

Next, a third embodiment of the present invention will be described with reference to FIG.

6 is a level shifter according to a third embodiment of the present invention.

As shown in FIG. 6, the level shifter according to the third embodiment of the present invention is composed of three PMOS transistors M6, M9, and M10 and two NMOS transistors M7 and M8.

The PMOS transistors M6 and M9 serve as input terminals of the differential amplifiers, and are applied to the PMOS transistor M9 and the NMOS transistor M8 by receiving an input signal IN and an input inversion signal INB. The output signal OUT is generated through the common drain.

A drain of the PMOS transistor M6 and a drain of the NMOS transistor M7 are connected, and an input inversion signal INB is applied to a gate terminal of the PMOS transistor M6.

The NMOS transistors M7 and M8 have their respective gates connected in common, and are connected to the common drain of the NMOS transistor M7 and the PMOS transistor M6. In addition, the source terminal of the NMOS transistors M7 and M8 is connected to a negative level voltage of the external voltage supply unit.

The drain of the NMOS transistor M8 is connected to the drain of the PMOS transistor M9, and an input signal IN is applied to the gate terminal of the PMOS transistor M9.

Each source terminal of the PMOS transistors M6 and M9 is connected together to be connected to the drain of the PMOS transistor M10. The source terminal of the PMOS transistor M10 is connected to the positive level voltage of the external voltage supply. In addition, a mode signal Mode is applied to the gate terminal of the PMOS transistor M10. The mode signal Mode is a control signal for applying the 0V to the standby mode state so that the level shifter does not operate.

That is, the level shifter according to the third embodiment of the present invention has a basic circuit configuration similar to that of the first embodiment of the present invention, but the portion which receives the input signal IN and the input inverted signal INB is a PMOS transistor. Only one mode signal (Mode) for determining the operation of the level shifter is applied to the gate of the PMOS transistor. Therefore, the operation of the level shifter according to the third embodiment of the present invention is the same principle as that of the first embodiment of the present invention. When the threshold voltages of the PMOS transistors M6 and M9 are Vthp, Vthp <| Vpos | If the equation is satisfied, the level shifter may be operated to improve the problem caused by the change of the threshold voltage Vthp, which has been a problem in the related art.

That is, the level shifter according to the third embodiment of the present invention has the same effect as the first embodiment of the present invention.

Next, a fourth embodiment of the present invention will be described with reference to FIG.

7 is a level shifter according to a fourth embodiment of the present invention.

As shown in FIG. 7, the level shifter according to the fourth embodiment of the present invention has the same structure as that of the third embodiment of the present invention, and is provided only at the gate terminal of the PMOS transistor M6, which is an input terminal of the differential amplifier. The only difference is that a reference voltage level (Vref) is applied, not the input inversion signal INB. The reference voltage Vref is an average voltage of the input signal IN and is a DC voltage of a predetermined level.

That is, like the level shifter according to the second embodiment of the present invention, the same principle as that of applying the reference voltage Vref instead of the input inversion signal INB to the input terminal of the differential amplifier.

Therefore, the fourth embodiment of the present invention not only has the same effect as the third embodiment of the present invention, but also has the advantage of reducing the number of input signals.

Although the present invention has been described with reference to the most practical and preferred embodiments, it is not limited to the embodiments disclosed above, but also includes various modifications and equivalents falling within the scope of the following claims.

The level shifter according to the present invention can reduce the area occupied by the circuit by simplifying a circuit shifting to a negative level and a positive level, and can prevent a malfunction due to a threshold voltage variation. In addition, power consumption can be reduced by not operating in the standby mode. Moreover, the said level shifter can be used effectively for the liquid crystal display device of this invention.

Claims (9)

A timing controller for generating a logic signal; A display unit having a plurality of gate lines, a plurality of data lines crossing the gate lines, a pixel region formed in an area where the gate lines and the data lines intersect, and displaying an image for each frame; A gate driver driven according to an applied signal to supply a gate driving voltage to the gate line; A source driver configured to supply a data signal to the data line in synchronization with driving of the gate driver according to an applied signal; A level shifter driven by a positive level voltage and a negative level voltage applied from the outside, and level shifting a logic signal output from the timing controller to output the gate driver and the source driver. Including, And the level shifter differentially amplifies and outputs a first input signal of the logic signal and a second input signal of the logic signal. In claim 1, The level shifter A first transistor receiving the first input signal; A second transistor connected to the first transistor through a common drain, and a third transistor connected to the second transistor through a common gate, wherein the common gate of the second and third transistors includes the first and the second transistors; A current mirror unit connected to the common drain of two transistors; A fourth transistor connected to the third transistor through a common drain and receiving a second input signal; Sources of the first to fourth transistors are coupled to the negative level voltage or the positive level voltage applied from the outside, and are connected to the first input signal through a common drain of the third and fourth transistors. And a differentially amplified output signal of the second input signal. In claim 2, And the first input signal is a square wave swinging between a ground potential and a first potential, and the second input signal is an inverted signal of the first input signal. In claim 2, Wherein the first input signal is a square wave swinging between a ground potential and a first potential, and the second input signal is a reference voltage for supplying an average voltage of the first input signal. In claim 2, A liquid crystal display further includes a fifth transistor connected to a source of the first and fourth transistors, the fifth transistor controlling a turn-off of the first and fourth transistors in response to a control signal applied to a gate. . In claim 5, The first, fourth and fifth transistors are PMOS transistors, the second and third transistors are NMOS transistors, and a source of the PMOS transistor is applied from outside. And a source voltage of the NMOS transistor coupled with a positive level voltage applied from the outside. In claim 5, The first, fourth and fifth transistors are NMOS transistors, the second and third transistors are PMOS transistors, and a source of the PMOS transistor is coupled with a negative level voltage applied from the outside. And the source of the NMOS transistor is coupled with a positive level voltage applied from the outside. A level shifter for level shifting a logic signal provided from a timing controller of a liquid crystal display device and applying the level signal to a gate driver and a source driver, A first transistor receiving a first input signal of the logic signal; A second transistor connected to the first transistor through a common drain, and a third transistor connected to the second transistor through a common gate, wherein the common gate of the second and third transistors includes the first and the second transistors; A current mirror unit connected to the common drain of two transistors; A fourth transistor connected to the third transistor through a common drain and receiving a second input signal of the logic signal, Sources of the first to fourth transistors are coupled to a negative level voltage or a positive level voltage applied from an external source, and the first input signal and the fourth input signal are connected through a common drain of the third and fourth transistors. A level shifter, characterized in that a differentially amplified output signal of two input signals is generated. In claim 8, And a fifth transistor having a drain connected to the sources of the first and fourth transistors and operating according to a control signal applied to a gate to control the turn-off of the first and fourth transistors.

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