JPH08214177A - Photoelectric converter - Google Patents

Abstract

PURPOSE: To attain image pickup of a moving image even by a sensor whose reset time requires 1H period or over by driving horizontal drive lines scanned horizontally for 2× horizontal period or over as to drive of a photoelectric conversion element. CONSTITUTION: Each electrode 6 of a photoelectric conversion element of each line is connected in common to each of horizontal drive lines HL1-HLn and an odd number horizontal line is connected to a tri-state pulse terminal 20 and an even number horizontal line is connected to a tri-state pulse terminal 25 via horizontal selection switches SWd1 -SWdn . An output terminal of a latch circuit 29 is connected to gate terminals of the horizontal selection switches SWd1 -SWdn and the gate terminals are controlled by output pulses ϕV'1-ϕV'n of the latch circuit 29. An odd number control pulse ϕL1is given to a latch circuit 21 of an odd number horizontal line and an odd number output ϕV(2n-1) of a vertical scanning circuit 21 is latched by using the odd number control pulse ϕL1. An even number control pulse ϕL2 is given to a latch circuit 29 of an even number horizontal line and an even number output ϕV(2n) of the vertical scanning circuit 21 is latched by using the even number control pulse ϕL2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device in which photoelectric conversion pixels are two-dimensionally arranged and a read operation and a reset operation are performed for each pixel in a horizontal column, and more particularly to an amplification type photoelectric conversion device.

[0002]

2. Description of the Related Art Conventionally, photoelectric conversion pixels are arranged one-dimensionally to form a line sensor and two-dimensionally to form an area sensor, and an image signal is obtained from each photoelectric conversion pixel. Here, as an example of image reading of the photoelectric conversion pixels arranged two-dimensionally, a three-value level drive type photoelectric conversion element will be described as an example. Regarding this type of photoelectric conversion element, JP-A-63-186466 and Japanese Patent Application No. 62-1
The details are disclosed in Japanese Patent No. 7150.

First, the photoelectric conversion element will be described with reference to the schematic sectional view of the photoelectric conversion element shown in FIG. In the figure, a plurality of photoelectric conversion elements S1 to S3 ... Are formed on an n-type silicon substrate 1, and a p-type impurity is doped on an n ⁻ region 2 having a low impurity concentration formed by an epitaxial technique or the like. By doing so, the p region 3 is formed, and the n ⁺ region 4 is formed in the p region 3 by the impurity diffusion technique or the ion implantation technique. P region 3 and n ⁺ region 4 are the base and emitter of the bipolar transistor, respectively.

The n ⁻ region 2 formed in each region in this way
An oxide film 5 is formed on the oxide film 5, and a capacitor electrode 6 having a predetermined area is formed on the oxide film 5 so as to extend between the p base regions 3 and the adjacent p base regions 3. The capacitor electrode 6 on the p base region 3
Is a capacitor C _ox for controlling the base potential facing the p base region 3, and the capacitor electrode 6 between adjacent bases is a pMOS having the adjacent p base region 3 as a source / drain region. It is the gate electrode of the transistor Tr. Therefore, the capacitor electrode 6 is connected to the gate electrode of the pMOS transistor Tr.

The pMOS transistor Tr is a p-channel type and normally-off type, and is in an off state if the potential of the capacitor electrode 6 is the ground potential or a positive potential. Therefore, the p base region between adjacent elements is electrically isolated, and it is not necessary to form an element isolation region, which is advantageous for miniaturization of the element.

On the contrary, the capacitor electrode 6 has the threshold potential V
_{If the} negative potential exceeds _th , the pMOS transistor Tr
Is turned on, and the p base regions 3 of the respective elements are brought into conduction with each other.

Besides, an emitter electrode 7 connected to the n ⁺ emitter region 4, a protective film 8, an n ⁺ region 9 having a high impurity concentration on the back surface of the substrate 1, and a collector electrode for applying a potential to the collector of the bipolar transistor. 10 are formed respectively.

FIG. 9 is an equivalent circuit diagram of the photoelectric conversion element of FIG. 8 above. The portion surrounded by the broken line in the figure is an equivalent circuit of one photoelectric conversion element S1 to S3. In FIG. 9, the capacitor electrodes 6 of the photoelectric conversion elements S1 to S3 ...
And a ternary pulse φd is input to the terminal 20.

Further, p of each photoelectric conversion element S1 to S3 ...
The MOS transistors Tr are connected in series,
P base regions (not shown) are formed in the p base regions 3 of the terminal devices S1 and Sn with a certain distance, and a p-channel type and normally-off type MOS transistor Qx is provided on the device Sn side. Has been formed.

A ternary pulse φd similar to the capacitor electrode 6 is input to the gate electrode of the pMOS transistor Qx, and the source or drain of the p base region (not shown) is fixed at a constant potential Vc. Further, the source or drain, which is a p base region (not shown) of the pMOS transistor Tr of the element S1, also has a constant potential Vc.
It is fixed to.

Therefore, when all the pMOS transistors Tr and Qx are turned on, the p of each element is reduced.
The potential of the base region 3 can be set to a constant potential Vc. Further, in the off state, the photoelectric conversion elements are in an electrically separated state.

The emitter electrodes 7 connected to the n ⁺ emitter region 4 of each element are reset transistors Qb _{1 to} Q _3.
... grounded via Qb _n , and transistors Qb _{1 to} Qb
The gate electrodes of _n are commonly connected and the reset pulse φr is input. A positive voltage Vcc is applied to the collector electrode 10 of the bipolar transistor.

FIG. 10 is a schematic circuit diagram of a conventional solid-state image pickup device using such a photoelectric conversion element. This device of FIG. 10 is an m × n area sensor having a structure in which the photoelectric conversion elements S1 to S3 ... Sn shown in FIG. However, each line has the structure shown in FIG.
A normal element isolation region is formed between the lines to electrically isolate them.

Capacitor electrode 6 of the device in each line
Are connected in common to the respective horizontal lines HL1 to HLn, and each of them is a switch SW1 of an n-type MOS transistor.
Is connected to the terminal 20 through SWn. A ternary pulse φd for driving a ternary level is input to the terminal 20.

The switches SW1 to SWn are analog switches composed of nMOS transistors, and the output terminals of the vertical scanning circuit 21 are connected to their gate terminals.
It is controlled by its output pulses φv1 to φvm.

The emitter electrode 7 of each element is connected to each vertical line VL1 to VLn for each column. Vertical line V
L1 to VLn are reset transistors Qb1 to Qbn
It is grounded via the gate and the reset pulse .phi.r is input to the gate electrodes of the transistors Qb1 to Qbn.

Further, each vertical line VL1 to VLn is n
The storage capacitors C1 to Cn are connected to the storage capacitors C1 to Cn via the MOS transistors Qa1 to Qan, respectively.
.About.Cn are connected to the output line 22 via nMOS transistors Q1 to Qn.

A transfer pulse .phi.t for transferring the accumulated carriers of each pixel to the storage capacitors C1 to Cn is commonly input to the gate electrodes of the nMOS transistors Qa1 to Qan, and the horizontal scanning circuit is input to the gate electrodes of the nMOS transistors Q1 to Qn. Horizontal pulses .phi.h1 to .phi.hn are respectively input from 23.

The output line 22 is an nMOS transistor Q.
It is grounded via rh and is connected to the input terminal of the amplifier 24. The reset pulse φrh of the output line 22 is input to the gate electrode of the nMOS transistor Qrh.

The constant potential Vc for setting the base potential of each of the photoelectric conversion elements S11 to Smn is the ground potential.

Next, the operation of the solid-state image pickup device of FIG. 10 will be described with reference to the timing chart of FIG.

First, at time t1, only the vertical pulse φv1 of the vertical scanning circuit 21 is set to the high level, and the switch SW1
Is turned on. At time t2, transfer pulse φt
Is set to a high level to turn on the transistors Qa1 to Qan.

Next, at time t3, the ternary pulse φd is set to a positive potential for the period T1.
A positive voltage is applied to the electrodes 6 of the line elements S11 to S1n. As a result, the npn transistor is turned on, and the photon charge in the p base region 3 is transmitted through the emitter to the first line HL1.
Of the first line HL1 and the read signal of the first line HL1 is applied to the horizontal lines VL1 to VLn and the transistor Qa1.
The charges accumulated in the p-base region 3 are transferred to the capacitors C1 to Cn through .about.Qan.

Next, at time t4, the transfer pulse φt becomes low level and the transistors Qa1 to Qan are turned off. Then, at time t5, the horizontal scanning circuit 21 sequentially outputs the pulses φh1 to φhn, and the read signals accumulated in the capacitors C1 to Cn are sequentially taken out to the output line 22 via the pMOS transistors Q1 to Qn, and the amplifiers are sequentially output. Through 24, the data of each pixel is serially output to the outside as an output signal Vout. At time t6 after time t5, the horizontal reset pulse φrh rises every time each read signal is output, the nMOS transistor Qrh is turned on, and the residual carriers in the output line 22 are removed.

In parallel with this image signal output operation, time t
At 6, the reset pulse .phi.r is set to the high level to turn on the transistors Qb1 to Qbn and the vertical lines VL1 to Vb
The residual charge on the vertical line is reset by grounding Ln (second reset).

Further, from time t7, the ternary pulse φd is set to a negative potential in the period T2 to turn on the pMOS transistor Tr of the first line (first reset). This first
Reset time is proportional to (horizontal pixel number) ² and is usually 50μ
It requires about s.

As a result, the potentials of the p base regions 3 of the photoelectric conversion elements S11 to S1n are uniformly set to the ground potential Vc as described above, and the initial middle potential is set by the refresh operation in the periods T3 and T4. Return, period T
At 4, the npn transistor is turned on to ground the electric charge in the p base region through the emitter, and at time t8, a ternary pulse φ
d becomes the medium potential, and the accumulation operation is started.

When the operation of the first line is completed in this way,
At time t9, the vertical pulse φv1 falls and the switch SW
Turn 1 off. Then, the transfer pulse .phi.t rises to turn on the transistors Qa1 to Qan. As a result, carriers remaining in the capacitors C1 to Cn are transferred to the vertical lines VL1 to VLn and the transistor Qb.
Remove through 1-Qbn. At time t10, the reset pulse φr falls, and the operation on the first line is terminated. At time t11, the horizontal pulse φv2 that activates the second horizontal line becomes high level, and the charges on the second horizontal line are read out. Be done.

Hereinafter, the same operation is performed for each horizontal line,
The read signals of the second to m-th horizontal lines are sequentially output. It should be noted that one horizontal scanning period is a period from time t1 to time t11 and is expressed as 1H below.

Thus, the ternary pulse φd of the ternary level is generated.
If the photoelectric conversion elements S11 to S1n driven by
The base potential of the elements on each line is set to a constant potential in the period T2, and then the refresh operation is performed in the periods T3 and T4.
It is possible to obtain a solid-state imaging device having good linearity of photoelectric conversion characteristics. Moreover, since no element isolation region is required in the horizontal line direction, it is possible to obtain a solid-state image pickup device which is suitable for miniaturization of elements and can easily cope with high resolution.

[0031]

However, in the above-mentioned conventional example, the signal read, transfer, and reset of the same horizontal line pixel are performed for 1H period (63.5 μ in the NTSC system).
Since it has to be performed within s), there is a drawback that the reset does not end within the 1H period when the number of pixels of the area sensor increases (for example, if the number of horizontal pixels is 1560, the reset time is about 100 μs). Yes,
As the number of pixels increases, it becomes particularly difficult to shoot moving images.

An object of the first invention of the present application is to enable moving image shooting even in a sensor requiring a reset time of 1H period or more.

[0033]

In order to achieve the above object, the first aspect of the present invention provides a means for reading out pixels on a horizontal line every 1H period and a reset means for performing reset for 2H periods or more. It is characterized by being provided.
Here, a unit including a reading unit, a transfer unit, and a reset unit is shown as a driving unit.

As the above means, a vertical scanning circuit that generates a pulse every 1H period and a latch circuit that latches the pulse are provided, or two sets of vertical scanning circuits that generate a pulse every 2H period are provided. Can be achieved with.

In the present invention, unlike the prior art, horizontal pixels can be driven for a 2H period, so that the reset time will not run short even if the number of pixels increases. Since the next horizontal line is read out while the read horizontal line is being reset, the output can be easily adapted to the TV operation (NTSC, PAL, etc.) format.

[0036]

【Example】

(1) Embodiment 1 FIG. 1 is a circuit diagram of a photoelectric conversion device showing an embodiment according to the present invention. In the figure, 20 and 25 are ternary pulse terminals of ternary voltage supplied to control the operation of each photoelectric conversion pixel, 21 is a vertical scanning circuit for scanning a horizontal drive line for each horizontal output, and 22 is a storage. An output line that sequentially outputs electric charges,
23 is a horizontal scanning circuit for scanning each vertical output line, 24 is an output amplifier for amplifying the signal of the output line 22, 26 is a reset pMOS transistor for resetting the photoelectric conversion element,
27 is an npn phototransistor which is a photoelectric conversion element,
Reference numeral 28 is a capacitor C _ox for controlling the base potential of the npn phototransistor, VL1 to VLn are vertical output lines, and HL1 to HL.
Reference numeral n is a horizontal drive line, and 29 is a latch circuit for latching the signal of the vertical scanning circuit 21. SWa1 to SWan are transfer switches for transferring the output signal to the storage capacitors C1 to Cn, S
Wb1 to SWbn are horizontal transfer switches for transferring signals from the storage capacitors C1 to Cn to the outside via the output line 22, and S
Wc1 to SW1n are reset switches for grounding and resetting the vertical output lines VL1 to VLn, and SWd1 to SWdn are horizontal selection switches for selecting the horizontal drive lines HL1 to HLn.

The electrodes 6 of the photoelectric conversion elements in each line are commonly connected to each of the horizontal lines HL1 to HLn, and the odd horizontal lines are connected to the ternary pulse terminal 20 and the even horizontal lines via the horizontal selection switches SWd1 to SWdn, respectively. The line is connected to the ternary pulse terminal 25. Also,
Odd ternary pulse φR1 is input to ternary pulse terminal 20,
An even ternary pulse φR2 is input to the ternary pulse terminal 25. The output terminals of the latch circuit 29 are connected to the gate terminals of the horizontal selection switches SWd1 to SWdn, and controlled by the output pulses φV′1 to φV′n of the latch circuit 29. The odd number control pulse φL1 is applied to the latch circuit 29 of the odd number horizontal line.
And the odd output φV (2n-1) of the vertical scanning circuit 21 is latched by the odd control pulse φL1. The even control pulse φL2 is input to the latch circuit 29 of the even horizontal line,
Even control pulse φL2 outputs even output of vertical scanning circuit φ
Latch V (2n).

The vertical scanning circuit 21 has a vertical scanning pulse φVS.
Controlled by R _s , φVSR ₁ and φVSR ₂ , the operation starts when a positive pulse is input to the vertical scan start pulse φVSR _s . The output of the vertical scanning circuit 21 is sequentially output in synchronization with the high level period of the vertical scanning synchronization φVSR ₁ .

Next, the operation will be described with reference to the timing chart of FIG.

First, the vertical scanning circuit 21 is scanned to set the vertical pulse φV1 and the odd control pulse φL1 to high level,
The switch SWd1 is turned on. Transfer pulse φT
Is set to a high level to turn on the transistors SWa1 to SWan.

Next, when the ternary pulse φR1 is set to the high level for the period T1, a positive voltage is applied to the electrodes 6 of the elements S11 to S1n on the first line through the horizontal selection switch SWd1. As a result, the read operation of the first line is performed, and the read signal of the first line passes through the vertical lines VL1 to VLn and the transistors SWa1 to SWan and the storage capacitance C1.
To Cn are stored respectively.

Next, the transfer pulse φT goes low, turning off the transistors SWa1 to SWan. Then, the horizontal scanning circuit 21 sequentially outputs the pulses φh1 to φhn, and the read signals stored in the storage capacitors C1 to Cn are sequentially taken out to the output line 22 via the transistors SWb1 to SWbn, and the output amplifier 24
Is output serially to the outside as an output signal V _out . The horizontal reset pulse φrh rises every time each read signal is output, and the transistor Qrh is turned on to remove the residual carriers in the output line.

In parallel with this signal output operation, the odd-numbered three-valued pulse φR1 is set to low level to turn on the pMOS transistor of the first line (first reset).

After the reading of the first line is completed, the vertical pulse φV2 of the vertical scanning circuit becomes high level in the next horizontal period. Here, the vertical pulse φV1 becomes low level, but since the high level is held by the latch circuit 29 of the first line, the switch SWd1 continues to be in the ON state, and the first line is being read during the signal reading of the second line. It is possible to perform the first reset of. The reading operation of the second line is performed by the even-numbered three-valued pulse φR2, and when the signal output operation of the second line is completed and the blanking period is started, the emitter of the first line is grounded and the odd-numbered three-valued pulse φR1 is set high. Set to level and perform second reset. As a result, the elements on the first line are returned to the initial state and the accumulation operation is started.

Thereafter, the same operation is performed for each line, and the third to
The read signal of the m-th line is sequentially output.

As described above, by controlling the elements of each line by the latch circuit 29 for holding the output of the vertical scanning circuit on each line and the two or more ternary level pulses φR1 and φR2, it takes more than 2H period. As a result, it becomes possible to perform signal reading, first reset, and second reset. The signal output is every 1H period (63.5μ in NTSC system).
s) is output to each video format (NTSC, PA
It is now possible to realize an area sensor compatible with L, HD, etc.) without being restricted by the reset time.

In this embodiment, the amplification type photoelectric conversion device B is used.
Although it has been described with respect to ASIS (Base Stored Image Sensor), it can be realized by an SIT or MOS photoelectric conversion device.
Also, in the writing method of a liquid crystal display device or the like, the method of the present invention is effective by using the latch circuit for sequential scanning and resetting the liquid crystal display element at the latch time.

(2) Second Embodiment FIG. 3 shows a schematic circuit diagram of an area sensor according to a second embodiment of the present invention. Although the circuit diagram of the non-interlace drive is shown in the first embodiment, this embodiment is a case where the interlace drive is supported. In addition, the same reference numerals as those in FIG.
Detailed description will be omitted as the operation is performed.

In the case of interlace driving, since the third line is read after the first line is read,
K-th line (k = 1, 2 ...) And k + 2nd line (k =
1,2 ...) is another odd / even ternary pulse (φR1, φR2)
Have to drive in. Therefore, in this embodiment, the output from the vertical scanning circuit 21 is different from that in the first embodiment, and therefore, the odd ternary pulse φR1 is applied to the first and second lines.
Driven by, the third and fourth lines are even ternary pulse φR2
The circuit is driven by.

Therefore, as compared with the case shown in the first embodiment, the vertical output φV1 from the vertical scanning circuit becomes high and a horizontal signal is output immediately after the vertical output φV3 becomes high, and the horizontal of the third line becomes horizontal. Although a signal is output, the first line is reset during the third line output period, and then the third line is reset during the output of the fifth line. Then, the fourth line is output after the second line of the even lines is output, but the second line is reset during the output.

In the present embodiment, an XY address type area sensor capable of interlacing by interlaced scanning is enabled for vertical / horizontal scanning of an area sensor having pixels for one frame.

(3) Third Embodiment FIG. 4 shows a schematic circuit diagram of an area sensor of a third embodiment according to the present invention. In the first and second embodiments, the horizontal output terminal is 1
Although only one single-line output is provided, the present embodiment is characteristic in that two-line output is provided. FIG.
Those having the same reference numerals as those in FIG.

In the case of 2-line output, the effective output speed is doubled as compared with the 1-line output, so that it is effective in a high pixel count area sensor. Also in the present embodiment, the XY address area sensor which is not restricted by the reset time becomes possible by the method in which the signal is read out every horizontal scanning period and the read-out pixels are reset for several H periods. In this case, .phi.v1, .phi.v2, ... Of the vertical scanning circuit 21 in the circuit diagram of FIG. 1 shown in the first embodiment are output, and the three-valued pulses .phi.R1, .phi.R2 switch the three-valued voltage according to the timing via the latch circuit 29. By turning on / off SWd1, SWd2, ..., Photoelectric charges are applied to the respective horizontal lines HL1, HL2 ... And accumulated in the storage capacitors C1, C2, ... Via the switches SWa1, SWa2 ,.
The odd-numbered charges of C2, ... Are output to the output line 22 and output from the amplifier 24. Similarly, the storage capacities C1, C2,
The even-numbered charges of ... Are output to the output line 22 'and the amplifier 2
It is output from 4 '. At this time, by the latch circuit 29,
It is possible to reset each horizontal line with a margin of 1H.

(4) Fourth Embodiment FIG. 5 shows a schematic circuit diagram of an area sensor of a fourth embodiment according to the present invention. Further, FIG. 6 shows a drive timing chart of the circuit shown in FIG. In this embodiment, two lines simultaneously 4
This is a case where the present invention is applied to an area sensor in the case of line output. In the case of the present embodiment, since two lines are simultaneously output with four lines and the effective read speed is four times, a high speed drive sensor compatible with HD can be realized.

In the present embodiment, the driving timing chart of the circuit shown in FIG. 6 is basically the same as that in the case of FIG. 2, and four kinds of three-valued pulses φR1 to φR4 are supplied by the horizontal line driving means. However, since the odd-numbered vertical lines and the even-numbered vertical lines are connected to the readout circuits 30 and 31 each having the horizontal scanning circuit, the substantial operation is not significantly different from that of the first embodiment.

Therefore, the vertical scanning circuit 21 first starts by the input of the vertical start pulse φVSRs, and outputs the vertical output pulse φv1 in synchronization with the clock of the vertical pulse φVSR1. When the vertical output pulse φv1 becomes high level, the latch circuit 29 is operated by the control pulse φL1,
Latch the vertical output pulse φv1. As a result, the switches SWd1 and SWd2 are turned on, and two rows of the horizontal lines HL1 and HL2 can be simultaneously driven. Switch S
Since the ternary pulse φR1 is input to Wd1 and the ternary pulse φR2 is input to the switch SWd2, when the ternary pulse φR1 is set to the high state, the pixels on the horizontal line HL1 can be read and the ternary pulse φR2 can be read. When in the high state, the pixels on the horizontal line HL2 can be read out within the same horizontal period. By the read operation, the outputs of the pixels S11 and S21 are stored in the upper storage capacitors C1 and C2 via the vertical line VL1, and the outputs of the pixels S12 and S22 are output to the vertical line VL.
It is stored in the lower storage capacitors C1 'and C2' via 2.
After that, the horizontal scanning circuit 23 is scanned, and the charges of the storage capacitors C1 and C3 ... Are stored in the output line 22, and the storage capacitors C2 and C4 ...
Output to the output line 22 'and output amplifier 24,
Output to the outside via 24 '. At this time, the lower read circuit 31 is also operated in the same manner. Further, during this horizontal transfer period, the three-valued pulses φR1, φR2 are set to the low level state, and the first reset of the pixels on the horizontal lines HL1, HL2 ... Is performed.

After the end of the horizontal synchronization 1H period, the vertical pulse φVSR is shifted, the vertical output pulse φv2 is set to the high level state, and the horizontal lines HL3 and HL4 are driven.
In this case, as shown in FIG. 5, since the latch pulse φL2 and the driving pulses φR3 and φR4 are used, the operation can be performed regardless of the driving of the horizontal lines HL1 and HL2 of the driving lines.

Thereafter, the latch pulse φL2 and the drive pulse φR
3 and φR4 are driven in the same manner as above, and horizontal lines HL3 and H
After output of the pixel on L4 is completed, ternary pulse φR1, φR
By setting 2 to the middle level and further to the high level, the second reset of the pixels of the previous horizontal lines HL1 and HL2 is performed, and the reset is completed.

By repeating the above operation, it is possible to output four lines simultaneously for four lines at a TV scanning speed.

In this way, two-line outputs are obtained from the read circuits 30 and 31, respectively, and four-line outputs are obtained, so that it is possible to increase the vertical scanning speed and horizontal scanning speed to four times the effective reading speed. Therefore, an HD compatible sensor can be realized.

(5) Fifth Embodiment FIG. 7 shows a fifth embodiment of the present invention. It is to be noted that those having the same reference numerals as those in FIG.

In Embodiments 1 to 4, the latch circuit is provided in the horizontal drive line to enable resetting for a period of 2H or more. However, in the present embodiment, two vertical scanning circuits are used without using the latch circuit. By being provided, it is possible to perform reset for a period of 2H or more depending on the output timing of the vertical scanning circuit.

In FIG. 7, a second vertical scanning circuit 32 scans an even number of horizontal lines facing the first vertical scanning circuit and outputs vertical pulses φv2, φv4, ... And ternary pulse φR2. The switches SWd2, SWd4, ...

In the present embodiment, each vertical scanning circuit generates a scanning pulse every 2H and shifts the scanning start timing by 1H to obtain the same effects as those of the first to fourth embodiments.

[0065]

As described above, according to the present invention,
Even when the reset time is longer than 1H period such that the number of pixels increases and the circuit operation in which the charge of the pixels cannot be reset in a short time is required, a latch circuit is added, the number of read circuits is two or more, and a read circuit is used. Or a vertical scanning circuit can be added to realize a photoelectric conversion device for moving image shooting, which requires particularly high-speed reading, high-speed transfer, and high-speed reset.

[Brief description of drawings]

FIG. 1 is a schematic circuit configuration diagram of an embodiment according to the present invention.

FIG. 2 is a drive timing chart of an embodiment according to the present invention.

FIG. 3 is a schematic circuit configuration diagram of an embodiment according to the present invention.

FIG. 4 is a schematic circuit configuration diagram of an embodiment according to the present invention.

FIG. 5 is a schematic circuit configuration diagram of an embodiment according to the present invention.

FIG. 6 is a drive timing chart of an embodiment according to the present invention.

FIG. 7 is a schematic circuit configuration diagram of an embodiment according to the present invention.

FIG. 8 is a schematic circuit cross-sectional view near a photoelectric conversion element shown in a conventional example.

FIG. 9 is a schematic circuit diagram of a photoelectric conversion unit shown in a conventional example.

FIG. 10 is a schematic circuit diagram of a photoelectric conversion device shown in a conventional example.

FIG. 11 is a drive timing chart of the photoelectric conversion device shown in the conventional example.

[Description of Reference Signs] 1 n-type Si substrate 2 n-type epitaxial layer 3 p-type base doping layer 4 n ⁺ type emitter layer 5 oxide film 6 capacitor region C _ox 7 emitter electrode 8 protective film 9 n ⁺ high concentration layer 10 collector electrode 20, 25 Tri-level pulse terminals 21, 32 Vertical scanning circuit 22 Horizontal output line 23 Horizontal scanning circuit 24 Output amplifier 26 Pixel separation MOS 27 Phototransistor 28 Capacitor C _ox 29 Latch circuit 30, 31 Readout circuit

Claims (8)

[Claims] 1. A photoelectric conversion device in which photoelectric conversion elements are two-dimensionally arranged, comprising driving means for driving a horizontal drive line for performing horizontal scanning for driving the photoelectric conversion elements for 2 × horizontal scanning periods or more. And a photoelectric conversion device. 2. The photoelectric conversion device according to claim 1, wherein the driving means for driving for 2 × horizontal scanning periods or more,
A photoelectric conversion device comprising: a scanning circuit that generates a drive pulse for each horizontal scanning period; and a latch circuit that latches the pulse for a predetermined period. 3. The photoelectric conversion device according to claim 1, wherein the driving unit has two scanning circuits that generate a driving pulse every two horizontal scanning periods. 4. The photoelectric conversion device according to claim 1, wherein the photoelectric conversion element is formed of a bipolar phototransistor. 5. The photoelectric conversion device according to claim 1, wherein the driving means includes a ternary pulse supply terminal for odd horizontal lines and a ternary pulse supply terminal for even horizontal lines. Photoelectric conversion device. 6. The photoelectric conversion device according to claim 1, further comprising, in addition to the driving means, two output terminals provided by a scanning means of a horizontal scanning circuit from a storage capacitor provided in each vertical line. Photoelectric conversion device. 7. The photoelectric conversion device according to claim 1, wherein, in addition to the driving means, a read circuit is provided for each of odd vertical lines and even vertical lines for reading vertical lines. Converter. 8. The photoelectric conversion device according to claim 1, wherein the driving means includes a vertical scanning circuit that drives each of the odd horizontal lines and the even horizontal lines.