JP2753895B2 - Solid-state imaging device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a charge-coupled solid-state imaging device having an electronic shutter function and high vertical resolution.

[Conventional technology]

2. Description of the Related Art Conventionally, as charge-coupled solid-state imaging devices, there are known a charge-coupled solid-state imaging device of a frame transfer system (FT system) and a charge-coupled solid-state imaging device of a frame interline transfer system (FIT system). The FT charge-coupled solid-state imaging device includes a group of vertical charge transfer paths shared by a light receiving unit and a storage unit, and a horizontal charge transfer path connected to these vertical charge transfer paths at the end of the storage unit.

At the time of imaging, a potential well (transfer pixel) corresponding to a pixel is formed in the vertical charge transfer path group in the light receiving area by applying a drive signal of a unique voltage to the transfer gate electrode group in the light receiving area. Generates and accumulates the charges corresponding to the subject optical image, and after completion of the charge accumulation, causes the vertical charge transfer paths in both the light receiving section and the accumulation section to perform a charge transfer operation, thereby receiving all charges. Unit to the storage unit at high speed. Then, for example, in synchronization with the scanning cycle of the standard television system, the charge in the storage section is transferred to the horizontal charge transfer path, and the horizontal charge transfer path reads out the charge at the timing of line-sequential scanning, so that the pixel signal is Output in the order corresponding to the array.

On the other hand, in an IT-type charge-coupled solid-state imaging device, a light receiving cell corresponding to a pixel and a vertical charge transfer path for reading out a charge generated in the light receiving cell are formed separately. At the time of imaging, an optical image of a subject is received by a light receiving cell to accumulate electric charges corresponding to pixel signals, and at the same time as the completion of the electric charge accumulation, a charge is transferred to a transfer gate (a gate formed between the light receiving cell and a vertical charge transfer path). To the side of the vertical charge transfer path. Then, for example, in synchronization with the scanning cycle of the standard television system, the vertical charge transfer path transfers the charge to the horizontal charge transfer path, and the horizontal charge transfer path reads out the charge at the line-sequential scanning timing, so that the pixel signal is output. Output in order corresponding to the pixel array. Further, the FIT charge-coupled solid-state imaging device is a fusion of the FT method and the IT method, and has a considerably smaller smear reduction ability than the two types of charge-coupled solid-state imaging devices.

[Problems to be solved by the invention]

In such a conventional charge-coupled solid-state imaging device, first, the FT-type charge-coupled solid-state imaging device has a function as a pixel in a vertical charge transfer path, so that it has an electronic shutter function. Then, since the smear component is large, it is not feasible, and as a result, when applied to video equipment such as an electronic camera, a mechanical shutter is indispensable, which leads to an increase in size and complexity of the video equipment. There's a problem.

Further, in the FT system, reading is a frame image, and in the IT system, frame image reading is possible, but the exposure time is shifted by one vertical scanning period between fields. Also, in the FIT method, the shift of the exposure time is smaller than that of the FT method and the IT method, but is shifted by the time of the high-speed transfer of the first field.

This is a problem common to conventional FT, IT, and FIT charge-coupled solid-state imaging devices.When charge transfer paths transfer charges, pixel signals that are adjacent to each other are mixed. In order to perform transfer without charge, it is necessary to generate a potential well (transfer pixel) for holding electric charges and a potential barrier for separating the transfer pixels from each other. In such a case, it is necessary to control so as to transfer one set of charge signals by combining four or more transfer gate electrodes. As a result, it has been difficult to realize a frame electronic shutter function for improving the vertical resolution.

The present invention has been made in view of such a conventional problem, and has as its object to provide a charge-coupled solid-state imaging device having an electronic shutter function and a structure capable of improving vertical resolution.

Further, in the FIT system, many structures having a frame storage unit for improving the vertical resolution have been proposed, but there is a problem that the chip area increases and the yield decreases.

[Means for solving the problem]

In order to achieve such an object, the present invention forms a plurality of photoelectric conversion elements corresponding to pixels in a matrix in a row direction and a column direction, and adjoins each photoelectric conversion element group arranged in a column direction. A light-receiving unit that forms a vertical charge transfer path;
A storage section having a vertical charge transfer path connected to these vertical charge transfer paths of the light receiving section, and transferring a pixel signal generated in a pixel to the vertical charge transfer path of the light receiving section; By applying a gate signal at a predetermined timing to the transfer gate electrode of the vertical charge transfer path of the storage section, all pixel signals are transferred at high speed to the vertical charge transfer path of the storage section, and further, the vertical charge transfer path of the storage section is further transferred. In a charge-coupled solid-state imaging device in which a gate signal at a predetermined timing is applied to a transfer gate electrode of the same type and a pixel signal for each row is scanned and read out by a horizontal charge transfer path, the transfer gate electrode of the light receiving section is subjected to photoelectric conversion of each column The number of transfer gate electrodes of the storage section is formed to be half the number of transfer gate electrodes of the light receiving section, and two transfer gate electrodes adjacent to each other in the light receiving section are provided during the high-speed transfer. And a gate signal at a predetermined timing is applied to a set of the predetermined number of transfer electrodes, and the transfer gate electrodes adjacent to each other in the storage section are set to the same number as each set of transfer gate electrodes in the light receiving section. The application of the gate signal is stopped from the pair near the horizontal charge transfer path, the high-speed transfer is performed, and at the time of the scanning readout, a predetermined number of transfer gate electrodes adjacent to each other in the storage unit are grouped, Scan reading is performed by sequentially applying gate signals at a predetermined timing from the set of transfer gate electrodes closest to the horizontal charge transfer path side.

[Action]

According to the present invention having such a configuration, the photoelectric conversion element and the vertical charge transfer path in the light receiving unit are formed separately, and after the exposure, the photoelectric conversion element is transferred from the photoelectric conversion element to the vertical charge transfer path before scanning and reading are performed. Therefore, it has an electronic shutter function, and transfers pixel signals in the vertical charge transfer path in the order of dominoes from those located on the horizontal charge transfer path side, so that the number of transfer gate electrodes is reduced. And the vertical resolution can be improved. In addition, field storage can be performed in half the area of the conventional field storage unit, and the size of the semiconductor chip can be reduced.

〔Example〕

Hereinafter, a charge-coupled solid-state imaging device according to the present invention will be described. However, in order to understand the charge-coupled solid-state imaging device according to the present invention, it is necessary to describe a precedent embodiment of the present invention, which is a prerequisite thereof. A case where the present invention is applied to an electronic still camera that captures a still image will be described.

The overall structure of the electronic still camera will be described with reference to FIG.
In FIG. 1, reference numeral 1 denotes an imaging optical system including an imaging lens and the like, reference numeral 2 denotes a mechanical diaphragm mechanism, and reference numeral 3 denotes a charge-coupled solid-state imaging device to which the present invention is applied. In addition, they are arranged in order and the optical image of the subject is incident on the light receiving region of the charge-coupled solid-state imaging device 3. Reference numeral 4 denotes a signal processing circuit, and 5 denotes a recording mechanism. The signal processing circuit 4 performs color separation, γ correction, white balance adjustment, and the like on the pixel signal output from the charge-coupled solid-state imaging device 3, and outputs a luminance signal and a color difference. A signal is formed, and the luminance signal and the color difference signal are subjected to recordable modulation processing in the recording mechanism 5 and then recorded on a magnetic recording medium or the like. The synchronization control circuit 6 processes a series of operations from imaging to recording by synchronously controlling the readout timing of the aperture mechanism 2, the charge-coupled solid-state imaging device 3, and the operations of the signal processing circuit 4 and the recording mechanism 5.

The overall schematic structure of the charge-coupled solid-state imaging device 3 is as follows.
It is as shown in the figure. The light receiving unit 7 for receiving the subject optical image includes a plurality of pixels corresponding to n pixels arranged in a matrix of n in the column direction Y and m in the row direction X. M vertical charge transfer paths L _{1 to} L _m are formed adjacent to the photodiode (portion indicated by P in the drawing) and each photodiode group arranged in the column direction Y. A storage unit 8 having a group of vertical charge transfer paths extending from the vertical charge transfer paths L _{1 to} L _m is provided below the light receiving unit 7. At the end of each of these vertical charge transfer paths L ₁ ~L _m accumulation unit 8, a horizontal charge transfer path 10 is formed, output amplifier 11 at the end of the horizontal charge transfer path 10 is formed. The vertical charge transfer path L ₁ ~L _m, the gate electrode of the predetermined arrangement is provided as will be described later, it is further laminated shielding layer for preventing incidence of light on their upper surface. These gate electrodes, a drive signal for causing a charge transfer operation in synchronism with a predetermined timing in the vertical charge transfer paths L ₁ ~L _m first,
It is supplied from the second and third drive circuits 12, 13, and 14. still,
Timing signals φ _H , V _L , φ _G , φ _FS , V _S , φ ₁ , φ ₂ , φ ₃ , φ ₄ , supplied to the respective drive circuits 12, 13, 14
The synchronous control circuit 6 generates φ _IN , φ _RS , φ _A , and φ _B.

Moreover, the horizontal charge transfer path 10 receives the forwarded come signal charges from the vertical charge transfer paths L ₁ ~L _m, and further a gate electrode for horizontal transfer is provided to the output amplifier 11 side, of Gate signals α ₁ and α ₂ applied to each gate electrode for performing the operation are supplied from the synchronization control circuit 6.

Next, the structure of the charge-coupled solid-state imaging device will be described in detail with reference to FIGS. FIG. 3 shows an enlarged view of a main structure of the light receiving section 7 and the storage section 8, FIG. 4 shows a circuit of the third drive circuit 14, and FIG. 7 shows a vertical section of the charge-coupled solid-state imaging device. The structure is shown. First, in FIG. 3, this charge-coupled solid-state imaging device has an appropriate type and impurity concentration layer embedded in a semiconductor substrate by a semiconductor integrated circuit manufacturing technique, and an electrode layer and the like are laminated on the semiconductor substrate. It is formed by this.

The light receiving section 7 is a p-well layer (not shown) in the semiconductor substrate.
By forming a plurality of impurity layers made of n ^{+ -type} impurities in a matrix along the column direction Y and the row direction X, a photodiode group indicated by P in FIG. 2 (in FIG. 3, P ₁ , P ₂ , P ₃ , P ₄ , P _5, ...) Are provided, and an n-type impurity layer is formed adjacent to each photodiode group arranged in the column direction Y. The vertical charge transfer paths L _{1 to} L _{m in} the figure (in FIG. 3, some of the vertical charge transfer paths L _i−1 ,
L _i , L _{i + 1} and L _{i + 2} are formed. Further, as shown in the figure, a pair of transfer gate electrodes G ₁₁ , G ₂₁ , G
_{31, G 41, G 12,} G 22, G 32, G 42 ~G 1n / 2, G 2n / 2, G
_{3n / 2} and G _{4n / 2} are stacked.

Incidentally, since the photodiodes P _{1 to} P _n of n rows are formed in the Y column direction, the total number of transfer gate electrodes is 2 × n.
For convenience of explanation, the transfer gate electrode is generally _{denoted by Gik}
The subscript k indicates the order of each set with four transfer gate electrodes as one set, and the subscript j indicates the order of the four transfer gate electrodes in each set. Therefore, the transfer gate electrodes of the first set (k = 1) are denoted by G ₁₁ , G ₂₁ , G ₃₁ and G ₄₁ , and the final set (k
= N / 2) are G _{1n / 2} , G _{2n / 2} , G _{3n / 2} ,
Shown as G _{4n / 2} .

Then, a channel stopper (consisting of only one portion) indicated by Tg in FIG. 3 and including a p ^{+ -type} impurity layer around a portion excluding a portion serving as a transfer gate, a photodiode portion, and a vertical charge transfer path portion is provided. A hatched portion surrounded by a dotted line in FIG. 3) is formed. The upper surface of the vertical charge transfer paths extending to the storage unit 8 also, the transfer gate electrodes g ₁₁ for realizing the charge _{transfer, g 21, g 31, g} 41, g 12, g 22, g 32, g 42
~ G _{1n / 2} , g _{2n / 2} , g _{3n / 2} , g _{4n / 2} are laminated,
Further, the vertical charge transfer path is surrounded by a channel stopper (hatched portion surrounded by a dotted line). It should be noted that the total number of transfer gate electrodes corresponding to the area of the storage section 8 is also 2 × n, and for convenience of explanation, four transfer gate electrodes are shown as one set. A horizontal charge transfer path 10 is formed at the end of the group of vertical charge transfer paths in the storage section 8 in the same manner as shown in FIG. Since the horizontal charge transfer path 10 has a well-known structure, details thereof are omitted, but charge transfer is performed by a two-phase driving method, a four-phase driving method, or other methods using timing signals α ₁ and α ₂ . At an end of the vertical charge transfer path on the light receiving section 7 side, a drain section 15 for discarding unnecessary charges is formed.

Next, the configuration of the first, second, and third drive circuits 12, 13, and 14 will be described.

First, referring to the first driving circuit 12, when the nearest gate electrode g ₁₁ to the horizontal charge transfer path 10 of the storage portion 8 and the first gate electrode, the odd-numbered gate electrodes g _11, g _31,
g ₁₂ , g ₃₂ , g ₁₃ , g _{33 to} g _{1n / 2} , g _{3n / 2} each tip is NMOS
Transistor _{D 11, D 31, D 12} , D 32, D 13, D 33 ~D 1n / 2,
D _{3n / 2,} and is connected to the signal line of the signal _VL , and the even-numbered gate electrodes g ₂₁ , g ₄₁ , g ₂₂ , g ₄₂ , g ₂₃ , g _{43 to} g _{2n / 2} , g
_{4n /} each tip of the ₂ NMOS transistors _{D 21, D 41, D 22} ,
Through _{D 42, D 23, D 43} ~D 2n / 2, D 4n / 2, driving signal φ
_H signal line. Further, the gate contact of these transistors, the driving signal phi _G is supplied. Incidentally, for convenience of explanation, it is also shown to correspond to the transfer gate electrodes g ₁₁ ~g _{4n / 2} these NMOS transistors.

In the transfer gate electrode of the light receiving section 7, the transfer gate electrode G adjacent to the transfer gate electrode g _{4n / 2} on the last side of the storage section 8
_Assuming that ₁₁ is a first transfer gate electrode, odd-numbered gate electrodes G ₁₁ , G ₃₁ , G ₁₂ , G ₃₂ , G ₁₃ , G _{33 to} G _{1n / 2} , G
_{3n /} each tip of the ₂ NMOS transistors _{M 11, M 31, M 12} ,
Through _{M 32, M 13, M 33} ~M 1n / 2, M 3n / 2, connected to the signal line of the signal V _L, even-numbered gate electrodes _{G 21, G 41, G 22} , G
₄₂ , G ₂₃ , G _{43 to} G _{2n / 2} , and G _{4n / 2} have NMOS transistors M ₂₁ , M ₄₁ , M ₂₂ , M ₄₂ , M ₂₃ , M _{43 to} M _{2n / 2} , M _{4n / Two}
Through, are connected to the signal line of the driving signal phi _H. or,
A drive signal φ _G is connected to the gate contacts of these transistors.
Is supplied.

Further, even-numbered gate electrodes G ₂₁ , G ₄₁ , G ₂₂ , G ₄₂ , G
_23, G ₄₃ ~G _{4n /} Each tip of the _2, npn transistors
_{Q 21, Q 41, Q 22} , Q 42, G 23, Q 43 ~G 4n / each emitter contact ₂ is connected, the drive signal phi _FS the base contacts of each npn transistor, the voltage V _S to the collector contact Is applied. still,
For convenience of explanation, it is also shown to correspond to the transfer gate electrode G ₁₁ ~G _{4n / 2} these npn transistors.

Next, the second drive circuit 13 converts the timing signals φ _{1 to} φ ₄ supplied from the synchronization control circuit 6 into the drive signals S _S1 , S _{S2 to} S _{Sn / 2} , and S _Sn from the third drive circuit 14. NMOS transistors d ₁₁ , d ₂₁ , which perform switching operation in synchronization with _{/ 2 + 1 to} S _Sn
consist _{d 31, d 41 ~d 4n /} 2 and _{m 11, m 21, m 31} , m 41 ~m 4n / 2 Prefecture, 2 × n pieces of NMOS transistors _{d 11, d 21, d 31} , d 41
To d _{4n / 2} are transfer gate electrodes g ₁₁ , g ₂₁ , g ₃₁ , and g of the storage section 8.
_{41 to} g _{4n / 2} , and the remaining 2 × n NMOS transistors m ₁₁ , m ₂₁ , m ₃₁ , and m _{41 to} m _{4n / 2} are connected to the transfer gate electrodes G ₁₁ , G _{21 of the} light receiving section 8. , G ₃₁ , and G _{41 to} G _{4n / 2} . Incidentally, for convenience of explanation, the NMOS transistors d _{41 to} d _{41
4n / 2} and m _{41 to} m _{4n / 2} are transferred to gate electrodes g _{41 to} g _{4n / 2} and G ₄₁
ＧG _{4n / 2} .

Further, these NMOS transistors of the storage section 8 are grouped in groups of four, and drive signals S _S1 , S _{S2 to} S _{Sn / 2} , S _{Sn /} of the third drive circuit 14 are sequentially connected to their gate contacts. _{2 + 1} to
S _Sn is applied and the first NMOS transistor in each set
The timing signal φ ₁ and the second NMOS transistors d ₂₁ , d ₂₂ , d ₂₂ are connected to the drain contacts of d ₁₁ , d ₁₂ , D ₁₃ , d _{14 to} d _{1n / 2.
23,} d _{24 ~d 2n / 2} of the timing signal phi ₂ to the drain _contact, the third NMOS transistor _{d 31, d 32, d 33} , d 34
The timing signal φ ₃ is supplied to the drain contacts of 〜d _{3n / 2} , and the timing signal φ ₄ is supplied to the drain contacts of the fourth NMOS transistors d ₄₁ , d ₄₂ , d ₄₃ , and d _{44 to} d _{4n / 2} .

Similarly, these NMOS transistors of the light receiving unit 7 also
Each of them is a set, and the third
Drive signals S _{Sn / 2 + 1} , S _{Sn / 2 + 2 to} S _Sn of the drive circuit 14 of FIG.
Is applied, and the first NMOS transistor m _{11 of each set} ,
A timing signal φ ₁ , a second NMOS transistor m ₂₁ , m ₂₂ , m ₂₃ , m is connected to the drain contact of m ₁₂ , m ₁₃ , m _{14 to} m _{1n / 2.
The} timing signal φ _{2 is connected} to the drain contact of _{24 to} m _{2n / 2} ,
Th NMOS transistors _{m 31, m 32, m 33} , m 34 ~m 3n / 2 of the timing signal phi ₃ to the drain contact, the fourth NMOS transistor _{m 41, m 42, m 43} , m 44 ~m 4n / _The timing signal φ ₄ is supplied to the drain contact ₂ . Signal S in FIG.
_{11, S 21, S 31,} S 41 ~S 4n / 2 and _{I 11, I 21, I 31} , I 41 ~I
_{4n / 2} is a signal supplied to each transfer gate electrode.

As shown in FIG. 4, the third drive circuit 14 generates drive signals S _S1 , S _S2 , S _S3 , S _{S4 to} S _{Sn / 2} , S S at predetermined timing.
It is formed of an n-bit output type shift register that outputs _{Sn / 2 + 1 to Sn} . That is, this shift register
As shown in the timing chart of FIG. 5, by transferring the start palace signal φ _IN from the lower output bit to the upper output bit in synchronization with the two-phase timing signals φ _A and φ _B , the logical values are sequentially changed. It is configured to generate a drive signal of “M”. That is, first, only the lowest drive signal S _S1 is at the “M” level, the other upper bit outputs are at the “L” level,
In the next cycle, the lower two bits of the drive signals S _S1 and S _S2 are at the “M” level, the remaining upper bit outputs are at the “L” level, and in the next cycle, the lower two bits of the drive signals S _S1 and S _{S1 S2} and S
_The output of the drive signal at the "M" level changes sequentially from the lower bits to the upper bits, such that _S3 is at the "M" level and the remaining upper bit outputs are at the "L" level.

As shown in FIG. 4, the circuit for each bit has a cell structure, and a 4 × n circuit having a cell structure is connected to form a shift register. Therefore, when described as a representative circuit of the first bit, between the signal line and the ground terminal of one of the timing signal phi _B, MOS transistors u _11, u ₁₂ connects the drain-source path as a serial, MOS transistors the gate contact of u ₁₁ is connected to the input contact theta _iN, the gate contact of the MOS transistor u ₁₂ is connected to the signal line of the other timing signal phi _a. Between MOS transistor gate-drain contact of the u _11, the bootstrap capacitor epsilon ₁₁ utilizing the gate oxide film is connected, further, between the drain contacts of the MOS transistor u ₁₁ is MOS
It is connected to the intermediate contact theta _X via the source-drain path of the transistor u _13. Also, MOS transistor u _14, u ₁₅ between the signal line of the signal line and the signal V _L of the signal V _M is connected to the drain-source path as a serial signal V _M is applied to the gate contact of the MOS transistor u ₁₄ the gate contact of the MOS transistor u ₁₅ is connected to the input contact theta _iN. Also, the intermediate contact θ
With MOS transistors u ₁₇ between the signal lines _X and the signal V _L is connected, MOS transistor u ₁₆ between gate contact of the MOS transistor u ₁₄ and u connection contacts ₁₅ and MOS transistor u ₁₇ is connected, MOS transistor signal phi _B is applied to the gate contact of u _16. Also, MOS transistor u ₁₁ ~u ₁₇ and subsequent circuits of the same configuration as the previous stage circuit including a capacitor epsilon ₁₁ is MOS
It comprises transistors u _{21 to} u ₂₇ and a capacitor ε ₂₁ . However, a transistor u ₂₁ corresponding to the MOS transistor u ₁₁ and a transistor corresponding to the MOS transistor u ₁₂
u ₂₂ , the signals φ _A and φ _B applied to the respective gate contacts of the transistor u ₂₆ corresponding to the MOS transistor u ₁₆ are set so as to be applied to signals opposite to each other. connect to theta _X, the output side contacts of the transistor u ₂₃ is an output contact theta _O of the first bit. The first bit of the driving signal S _S1 is generated at the drain contact of the MOS transistor u ₂₁ of the subsequent circuit, first shown in FIG. 3 2
It is wired so as to supply to the drive circuit 13. And
By connecting the input contact θ _IN and the output contact θ _O of the other circuits having the same cell structure in a subordinate manner, a circuit of the upper bit is also formed. The input contacts theta _IN of the first bit, the signal phi _IN start pulse supplied through the MOS transistor u ₀₀ the timing signal phi _A is applied to the gate contact. Signal V ₁ ~V ₁₇ generated in each contact in Fig. 4 becomes a timing shown in FIG. 5, in particular the shift register, the bootstrap capacitor epsilon _11, the boosting effect of the epsilon _21, propagates inside This has the effect of shaping the waveform of each signal.

Next, a longitudinal sectional structure will be described with reference to FIG. still,
FIG. 7 shows a vertical sectional structure taken along the line BB 'extending over the light receiving region 7 and the first, second and third drive circuits 12, 13 and 14 in FIG. First, a p-well layer 16 for forming a light receiving region 7 in a semiconductor substrate made of an n-type impurity, and a first driving circuit
A p-well layer 17 for forming 12 and a p-well layer 18 for forming the second and third drive circuits 13 and 14 are buried, and predetermined p-well layers 16, 17 and 18 are respectively provided. Are formed. First, in the light receiving region 7, a photodiode serving as a pixel is formed by forming a plurality of impurity layers 19 made of n ^{+ -type} impurities in a p-well layer 16 in a matrix along the column direction Y and the row direction X. Further, an n-type impurity layer (portion shown by a dotted line in FIG. 7) 20 is formed adjacent to each of the impurity layers 19 arranged in the column direction Y, so that the vertical charge transfer paths L _{1 to} L _m is formed. The third
The channel stopper is formed by forming ap ^{+ -type} impurity layer 21 around a portion to be a transfer gate indicated by Tg (only one portion is shown), a photodiode portion, and a vertical charge transfer path portion. Forming an area. Then, gate electrodes are stacked on the surface of the semiconductor substrate in an arrangement as shown in FIG.

The NMOS transistor in the first drive circuit 12 has a pair of n ^{+ -type} impurity layers 22, 23 as shown in the structure in the p-well layer 17.
When composed of the gate electrode on the surface portion of the structure stack, the drive signal phi _H is applied to the n ⁺ type impurity layer 22 serving as a drain contact, the n ⁺ -type impurity layer 23 serving as the source contact of the vertical charge transfer path gate Connected to electrodes. The signal _VL is applied to the p ^{+ -type} impurity layer 24 embedded in the p-well layer 17. npn
The transistor includes ap ^{+ -type} impurity layer 25 buried in a p-well layer 17, an n ^{+ -type} impurity layer 26, and an n-type semiconductor substrate 13, and an n ^{+ -type} impurity layer 26 serving as an emitter contact is connected to each gate electrode. and the timing signal phi _FS is applied to the p-well layer 17 and the p ⁺ -type impurity layer 25 serving as a base contact, the bias voltage V _S is applied to the semiconductor substrate 15 of n-type as a collector contact.

The MOS transistors in the second drive circuit 13 are composed of n ^{+ -type} impurity layers 27 and 28 formed in the p-well layer 18 and a group of MOS transistors as shown formed by gate electrodes provided thereon. The third drive circuit 14 is also formed of a similar MOS transistor group and the like.
Next, a case where the operation of the charge-coupled solid-state imaging device having such a structure is applied to an electronic still camera that captures a still image will be described.

First, a schematic operation for photographing a still image for one frame will be described with reference to a timing chart of FIG. Period in figure
_Assuming that TVB corresponds to a vertical blanking period of a standard television system such as NTSC, a so-called field for transferring all pixel signals from the photodiode to the vertical charge transfer path of the light receiving unit 7 at a predetermined time during this period _TVB. Perform shift operation,
Further, all the pixel signals transferred to the light receiving section 7 are transferred at high speed to the vertical charge transfer path of the storage section 8 at a predetermined transfer timing described later.

According to the electronic shutter function, the time point of the field shift operation corresponds to the time point at which the shutter is closed and the time point at which the exposure is completed. Therefore, the exposure operation starts from this point in time to an earlier point in time, and a period from the start of the field shift operation to the exposure period (ie, the light receiving period) by the photodiode. Further, the vertical charge transfer path L ₁
~L _m and unnecessary charges such that smear component and a dark current component in the horizontal charge transfer path 10 is swept out to the drain section 15 and the outside by a predetermined charge transfer operation before the end of the exposure operation.

Next, in a period _THB corresponding to a horizontal blanking period of a standard television system such as NTSC, a pixel signal of a transfer pixel closest to the horizontal charge transfer path 10 in the accumulation unit 8 is transferred to the horizontal charge transfer path 10. Then, in a period T _1H corresponding to a horizontal scanning period (a so-called 1H period), the horizontal charge transfer path 10 horizontally transfers pixel signals for one row at the timing of dot-sequential scanning, thereby forming a first row. The pixel signal of the eye is read.

Then, a period T corresponding to the next horizontal blanking period
In _HB, the vertical charge transfer paths L ₁ ~L _m accumulation unit 8 transfers the pixel signal of the next line to the horizontal charge transfer path 10, further horizontal charge transfer in the period T _IH corresponding to the next horizontal scanning period Road 1
The pixel signals in the second row are read by horizontal transfer of 0.

Further, it reads the pixel signal of the third row in each period T _HB and T _IH corresponding to the next horizontal blanking period and the horizontal scanning period. Then, the pixel signals in the remaining rows are sequentially read out by repeating the same processing, and finally all the pixel signals corresponding to one frame image are read out. That is, this embodiment has an electronic shutter function and performs non-interlaced frame scanning readout.

Hereinafter, the imaging operation of FIG. 8 will be described in detail with reference to timing charts of each drive signal and timing signal shown in FIGS. 9 to 12. Note that the horizontal axes in FIGS. 9 and 10 are shown on the same time scale, where the period _TVB is the vertical blanking period, the period _HB is the horizontal blanking period, and the period _T1H is the horizontal scanning period. Yes, it is. Furthermore, the first
1 drawing shows an enlarged main portion timing in the high-speed transfer period T _VBF in FIG. 9 and FIG. 10, further, FIG. 12 signal S ₁₁ to S ₄₁ in FIG. 11, S ₁₂ ~ shows an enlarged timing portion of each enclosed by a dotted line S _42, S _1n ~S _4n.

In these figures, "H" indicates 12 volts, "M" indicates 0 volts, "L" indicates -8 volts, and "HH" indicates a voltage level of about 15 to 25 volts which is equal to the voltage of the semiconductor substrate. .

First, the operation of the vertical blanking period _TVB will be described.
As shown in FIGS. 9 and 10, the vertical blanking period
Performing field shift operation at time t ₂ early in T _VB. That is, the signals φ _G and φ _H and the field shift signal φ _FS
By but the "H" level, all the npn transistors _{Q 21, G 41, G 22} , G 42 ~ becomes conductive, the even-numbered transfer gate electrode G ₂₁ in the light receiving section 7, G _41, G ₂₂ , G ₄₂ ~G
_{2n / 2} and G _{4n / 2 output} “H” level signals I ₂₁ , I ₄₁ , I ₂₂ , I ₄₂ .
I _{2n / 2} and I _{4n / 2} are applied, and the odd-numbered transfer gate electrodes
_{G 11, G 31, G 12} , G 32 ~G 3n / 2, G 3n / 2 equal to the signal V _L to "L" level signal _{I 11, I 31, I 12} , I 31 ~I 1n / 2, I _{3n / 2}
Is applied. Furthermore, in the time t _2, a third drive circuit
Since all the 14 output signals S _{S1 to} S _Sn become “L” level,
The transistors d _{11 to} d _{4n / 2} and m ₁₁ to
m _{4n / 2} becomes non-conductive, and the transfer gate electrodes g _{11 to} g
_{4n / 2} and G ₁₁ ~G _{4n / 2} and the third drive circuit 14 becomes electrically disconnected state.

Therefore, the even at the time point t ₂ th transfer gate electrode G
_{21, G 41, G 22,} G 42 ~G 2n / 2, G 4n / 2 potential well in correspondence to all the photodiodes under at the same time (transfer pixels) is generated, the odd-numbered transfer gate electrode G
₁₁ , G ₃₁ , G ₁₂ , G _{32 to} G _{1n / 2} , G _{3n / 2} , a potential barrier is generated, so that all the pixel signals do not mix with each other, and these potentials are transferred via the transfer gate Tg. Transferred to the well (transfer pixel). And
When the field shift signal _φFS goes to “L” level, the transfer gate Tg is cut off again.

Then, during a predetermined time period T _VBF following the time point t _2, and transfers all the pixel signals at high speed from the light receiving unit 7 to the storage section 8.

That is, as shown in FIG. 9, during this period _TVBF , the signal φ _FS is always set to the “L” level, the signal φ _H is always set to the “M” level, and the signal φ _G is the inverted signal of the signal φ _A. The signal has the same timing as the signal. Then, as shown in FIG. 11, when a start palace signal φ _IN is applied to the shift register constituting the third drive circuit 14, the signals S _{S1 to} S S are synchronized with the synchronization signals φ _A and φ _{B. Sn} sequentially inverts from “L” level to “M” level, and in synchronization with this, the second drive circuit 13
The transistors d _{11 to} d _{4n / 2} and m _{11 to} m _{4n / 2 in the} middle are turned on sequentially in groups of four. As a result, the signals φ ₁ to φ ₄ are transferred to the transfer gate electrodes g _{11 to} g _{4n / 2} via the transistors that are turned on among the transistors d _{11 to} d _{4n / 2} and m _{11 to} m _{4n / 2.} is transferred to G ₁₁ ~G _{4n / 2,}
A transfer gate signal S ₁₁ ~S _{4n / 2} and I ₁₁ ~I _{4n / 2.}

That is, the signals φ ₁ to φ ₁ are set within the rectangular ranges indicated by the dotted lines in FIG.
transfer gate signal synchronized with phi ₄ is generated, a waveform as Figure 12 showing a representative timing within the rectangular area of the dotted line of the transfer gate signals S ₁₁ to S _41.

Doing charge transfer at such a timing, the range of the transfer pixels as defeat so-called domino will change, the signal charges of the first line of the light receiving portion 7 (the 3 P ₁ row in the figure) the second row from the (third row of P ₂ in the figure), is transferred to the third row of the (third row of P ₃ in the figure) storage unit 8 side in the order of ....

Further, this charge transfer operation will be described with reference to a typical example shown in FIG. FIG. 3 shows the operation of one vertical charge transfer path as a representative, and four signal charges q ₁ , q ₂ , q ₃ , q ₄ generated by four photodiodes are stored in the storage unit 8. Shows the case of transfer. It is also assumed that a hatched square portion is each signal charge in the transfer pixel, and a white square portion is a potential barrier or an empty transfer pixel.

First, the signal charge q ₁ at time _{t 2, q 2, q 3} , q 4 is transferred pixel field shift, the timing of "1" of the sign of the signal charge q ₁ transfer starts, the timing of "3" The transfer of the signal charge q ₂ starts, and the signal charge starts from the timing “9”.
Transfer of q ₃ starts, "11" signal charge q ₄ from timing
Transfer starts. As described above, the signal charges are sequentially transferred from the signal charge located on the storage unit 8 side. Because it expands like defeat. Then, at the timing of “28”, “0”
At the timing, the signal charge q ₁ existing in the light receiving section 7,
q ₂ , q ₃ , and q ₄ are accommodated in the transfer elements of the storage unit 8 in the same arrangement.

As described above, when all the signal charges are transferred to the storage unit 8,
Next, after resetting the contents of the third drive circuit 14, the signal charge reading operation is started in synchronization with the horizontal scanning timing. That is, when described with reference to Figure 9 and Figure 10 again, the first horizontal blanking period T _HB (period from time t ₃ ~t _4), the signal phi _G becomes always "L" level, the All the NMOS transistors in one drive circuit 12 are turned off, and are electrically disconnected from all the transfer gate electrodes. The third drive circuit 14 outputs the signal φ of the first cycle.
_A, phi since _B is the total output is still "L" level is applied, the transfer operation of signal charges is not performed.

Next, a first horizontal scanning period T _HB (period from time t ₄ ~t ₅₎
In addition, the horizontal charge transfer path 10 performs horizontal transfer in synchronization with the gate signals α _{1 to} α ₄ at predetermined timings according to the four-phase drive method or the two-phase drive method, so that unnecessary charges in the horizontal charge transfer path 10 are reduced. Discard outside.

Next, the second horizontal blanking period T _HB (time t ₅
In ~t period _6), the third by the drive signal S _S1 of the first output terminal of the drive circuit 14 is the signal phi _A, in synchronization with the phi _B "M" level, other drive signals S _S2 to S _Sn Becomes “L” level, the first signal related to the drive signal S _S1 in the second drive circuit 13
Only the NMOS transistors d ₁₁ , d ₂₁ , d ₃₁ , and d ₄₁ of the set become conductive.

Then, four-phase timing signals φ ₁ , φ ₂ , φ ₃ , φ ₄ for performing the vertical charge transfer during a period in which only the drive signal S _S1 is at the “M” level are input to the second drive circuit 13. Therefore, the first to fourth first set of gate signals S ₁₁ ,
Only the timing signals φ ₁ , φ ₂ , S ₂₁ , S ₃₁ , S ₄₁
It becomes equal to φ ₃ and φ _4, and the charge transfer operation is performed by the first to fourth gate electrodes g ₁₁ , g ₂₁ , g ₃₁ , and g ₄₁ of the first set. Incidentally, the period T _HB (the period up to the time t ₅ ~t ₆₎
FIG. 14 is an enlarged view of each signal waveform of FIG. FIG. 14 shows only the signals S _{11 to} S _{4n / 2} related to the storage unit 8.

As a result, the signal charge becomes the gate signal S _{11 in} FIG. 14,
S _21, S _31, the timing of S ₄₁ (reference numerals 1, 2, 3, 4,
5, 6 and 7), the horizontal charge transfer path 10
Are transferred to the horizontal charge transfer path 10, and the pixel signals of the second row move to the position of the first row. Next, the second horizontal scanning period T _1H (time t _{6 to} t
In ₇ periods), changes the stop signal to the transfer gate electrodes g ₁₁ to g _{4n / 2,} whereas a predetermined timing gate signal which the horizontal charge transfer path 10 pursuant to the four-phase drive method or the two-phase driving mode By performing horizontal transfer in synchronization with α ₁ and α ₂ , the pixel signals of the first row are read out at the timing of dot sequential scanning. Next, in a period of time t ₇ ~t _8, by repeating the same operation as the time t ₅ ~t _6, reading out pixel signals of the next line. However, the horizontal blanking period of time t ₇ ~t ₈
In _THB , the drive signals S _S1 and S _{S2 of} the third drive circuit 14 are simultaneously at “M” level, and the remaining drive signals S _{S3 to} S _Sn are at “L” level. The waveform of each gate signal during this period _THB is shown in FIG.
It is shown enlarged in the figure.

As a result, the first to fourth first set of gate electrodes g ₁₁
A to g _41, fifth to eighth second set of gate electrodes g ₁₂ to g
₄₂ is a gate signal S equal to the timing signals φ _{1 to} φ _4
11 to S ₄₁ and S ₁₂ to S becomes ₄₂ to be driven by the pixel signals under these gate electrodes are vertically transferred.

That is, according to the timing shown in FIG. 15, the pixel signals of the second row are transferred to the horizontal charge transfer path 8, the pixel signals of the third row are for two rows, and the pixel signals of the fourth row are for one row. Are transferred to the horizontal charge transfer path 8 side. Then, in the next horizontal scanning period T _IH from time t _8, reads the horizontal charge transfer path 8 pixel signals of the second row in the dot sequential timing. Then, by repeating the same charge transfer operation, the output of the third drive circuit 14 gradually expands to the “M” level, so that the signal charges in the remaining rows are also read.

Then, the signal charges of the last row (the side closest line to the light-receiving unit 7), Figure 9 and Figure 10 period from time t ₉ ~t ₁₀ of (16
Figure vertically transferred to the horizontal charge transfer path 10 shows the timing) obtained by enlarging a further read out to the horizontal transfer period of time t ₁₀ ~t ₁₁ by the horizontal charge transfer path 10, the first frame of all the signal charges Reading is completed.

Thus, according to the preceding embodiment of the present invention, it is possible to provide an electronic shutter function and read out a pixel signal corresponding to one frame image by one frame scanning readout. Further, the vertical charge transfer path transfers the signal charges located in the row on the most output side in a so-called domino manner, so that the number of transfer gate electrodes can be reduced. In this embodiment, although to perform the charge transfer in synchronization with the period T _HB in 4-phase timing signal phi ₁ to [phi] ₄ of which corresponds to each horizontal blanking period, a suitable number of four or more phases The timing signal may be used to drive the gate electrode according to the number of phases. However, according to the preceding embodiment, there is a disadvantage that the area of the field storage unit cannot be reduced.

According to the present invention, field storage can be performed in half the area of a conventional field storage unit, and the size of a semiconductor chip can be reduced.

Next, an embodiment of the charge-coupled solid-state imaging device of the present invention will be described with reference to the drawings. A case where the present invention is applied to an electronic still camera for capturing a still image shown in FIG. 1 will be described. Also,
In FIGS. 17 and 18, parts that are the same as or correspond to the parts that are indicated by the reference numerals in FIGS. 1 to 7 are indicated by the same reference numerals.

First, the overall schematic structure of the charge-coupled solid-state imaging device will be described with reference to FIG. In FIG. 17, a light receiving unit 7 for receiving an optical image of a subject has the same configuration as the light receiving unit shown in FIG.
It has a configuration having half the charge storage capacity of the storage section shown in FIG. That is, assuming that the photodiodes P of the light receiving unit 7 are arranged in n rows (vertical resolution is n) in the Y direction, the accumulation unit 8 has n / 2 rows of pixel signals only for holding n / 2 rows of pixel signals.
Generate row transfer pixels. Therefore, the number of transfer gate electrodes for generating transfer pixels is also half that in the case shown in FIG. A horizontal charge transfer path 10 is formed at the end of the storage section 8.

The first drive circuit 12 has the same configuration as that of the first drive circuit in FIG. 1, but has only the number of transfer gate electrodes of the storage section 8 and the internal circuit is small. The second drive circuit 13 has the same configuration as the second drive circuit in FIG. 1, but is configured to control only the transfer gate electrode of the storage section 8. The third drive circuit includes a shift register 14 that operates at a predetermined timing, and controls the transfer gate electrode of the storage unit by a drive signal output from the shift register 14. The shift register 14 comprises the circuit shown in FIG. 4, and the shift register 14 has an n / 4 bit output configuration. The timing signal φ _SIN applied to the shift register 14 in FIG. 17 is a start pulse signal,
The signals φ _SA and φ _SB are two-phase timing signals for the shift operation.

FIG. 18 is a diagram showing the main structure of FIG. 17 in more detail. When FIG. 18 is compared with FIG. 3, it is apparent that the light receiving section has the same configuration as that of the normal interline system (IT system). Only the storage unit is controlled by the three driving circuits, and the shift register 14 controls the light receiving unit 7 and the storage unit 8.
The storage unit 8 is controlled by the second drive circuit 13 with the storage unit 8 as a set of four transfer gate electrodes.

Next, a case where the operation of the charge-coupled solid-state imaging device having such a structure is applied to an electronic still camera that captures a still image will be described.

In this embodiment, a pixel signal necessary for reproducing one frame of a still image is output by interlaced field scanning reading. That is, P ₁ , P ₂ ,
The pixel signals generated in the photodiodes in the columns indicated by P ₃ , P ₄ , P _5, ... Are read in the first and second rows, the third and fourth rows, and the fifth and fifth rows during odd-field scanning readout. Line 6 ...
・ Pixel signals that are adjacent to each other are mixed together (P ₁
+ P ₂ ), (P ₃ + P ₄ ), (P ₅ + P ₆ )... Are output as mixed pixel signals. In the case of even field scanning readout, the second and third rows and the third row are output. Pixel signals adjacent to each other in the fourth and fifth rows, the sixth and seventh rows... Are mixed, and (P ₂ + P ₃ ), (P ₄ + P ₅ ), (P ₆ ＋ P ₇ )
And output as a mixed pixel signal.

First, the schematic operation will be described with reference to FIG. Vertical blanking period of the standard television system such as the period T _VB of Fig. 19 is NTSC, the period T _A is an odd field scanning period, the period
T _B is the even field scanning period, the period T _HB horizontal blanking period, the period T _IH corresponds to one horizontal scanning period.

Then, field shift all pixel signals to the vertical charge transfer path of the light receiving section 7 from the photodiode at a predetermined time t ₂ of the vertical blanking period T _VB in the odd field scanning period T _A, further, in the period T _VBF, total The pixel signal is transferred at high speed from the light receiving unit 7 to the storage unit 8 at a predetermined transfer timing described later. In this high-speed transfer, the pixel signals corresponding to the odd-numbered fields are formed by simultaneously performing the above-described pixel signal mixing processing.

Further, the time t ₂ of the field shift operation corresponds to the time of closing the shutter, the exposure completion.
Therefore, the exposure operation from the time t ₂ in the preceding time starts and until the start time t ₂ of the field shift operation photodiode by the exposure period (i.e., the light receiving period) becomes.

Horizontal the vertical blanking period T _VB ends at time t _3, then, in the period T _HB corresponding to the horizontal blanking period, the closest transfer pixel pixel signals to the horizontal charge transfer path 10 in the storage portion 8 Transfer to the charge transfer path 10, then
In a period T _1H corresponding to a horizontal scanning period (a so-called 1H period), the horizontal charge transfer path 10 mixes one row of mixed pixel signals (that is, two rows of pixel signals of the light receiving unit into one row). The pixel signals of the first row of the storage unit are read out by horizontally transferring the pixel signals of the storage unit at the timing of the dot sequential scanning.

Then, a period T corresponding to the next horizontal blanking period
In _HB, the vertical charge transfer paths L ₁ ~L _m accumulation unit 8 forwards mixed pixel signal of the next line to the horizontal charge transfer path 10, further horizontal charge in the period T _IH corresponding to the next horizontal scanning period The mixed pixel signal in the second row is read by the horizontal transfer by the transfer path 10. Further, it reads the mixed pixel signals of the third row in each period T _HB and T _IH corresponding to the next horizontal blanking period and the horizontal scanning period. Then, the mixed pixel signals of the remaining rows are sequentially read out by repeating the same process, and finally all the mixed pixel signals corresponding to the odd-numbered field images are read out.

Next, the even field scanning read in the period T _B. However, since the predetermined time t ₄ during the vertical blanking interval T _VB becomes high-speed transfer period T _VBF, perform exposure for the even field image from this point t ₄ previously. That is, the period from the time t ₃ when the high-speed transfer processing of the odd field is completed up to the time t ₄ is the exposure period of the even field, the less the exposure period, after discarding the unnecessary charges in the photodiode, the total A period until a field shift operation is performed on the pixel signal to the vertical charge transfer path is defined as an exposure period (light receiving period).

Then, when the high-speed transfer of the even field is completed, t ₅
, The horizontal scanning readout of the pixel signals of the storage section 8 in synchronization with a predetermined timing, thereby reading out all the pixel signals corresponding to the even-numbered field images. Further, the operation of the field scan readout shown in FIG. 19 will be described in detail based on the timing charts of FIGS. 20 to 25.

20 and FIG. 21 are shown on the same time scale, and show the timing of scanning and reading of both the odd field and the even field. 22 and 23 are both shown on the same time scale, and show the timing of the odd-numbered field high-speed transfer period _TVBF . In addition, the 24th
FIG. 25 and FIG. 25 are both shown on the same time scale, and show the timing of the high-speed transfer period _TVBF of the even field.

First, the operation of the vertical blanking period T _VB in the odd field scanning read. As shown in FIG. 20 and FIG. 21, the initial time t ₂ of the vertical blanking period _TVB
Perform a field shift operation. That is, the signal φ ₂
And phi ₄ by becomes "H" level, the even-numbered transfer gate electrode G ₂₁ in the light receiving section _{7, G 41, G 22,} G 42 ~G 2n / 2,
G _{4n / 2} outputs “H” level signals I ₂₁ , I ₄₁ , I ₂₂ , I ₄₂ ,.
_{2n / 2} and I _{4n / 2} are applied, and the odd-numbered transfer gate electrodes G
₁₁ , G ₃₁ , G ₁₂ , G _{32 to} G _{1n / 2} , G _{3n / 2 output} signals φ ₁ , φ ₃
When equal "L" level signal _{I 11, I 31, I 12} , I 32 ~
I _{1n / 2} and I _{3n / 2} are applied.

Further, at the time point t _2, all of the output S of the shift register 14
_S1 to S _{Sn / 4} is "M" level, the transistor d ₁₁ in the drive circuit 13 to d _{4n / 4} is rendered conductive, transfer gate electrodes g
_{11 to} g _{4n / 4} even-numbered transfer gate electrodes g ₂₁ , g ₄₁ ,
_{g 22, g 42 ~g 2n /} 4, g 4n / 4 in the "M" level, the odd-numbered transfer gate electrodes _{g 11, g 31, g 12} , g 32 ~g 1n / 4, g 3n / 4 Is applied with an "L" level signal. Thus, at time t ₂
In the even-numbered transfer gate electrodes _{G 21, G 41, G 22} , G 42 ~
Potential wells (transfer pixels) are generated below G _{2n / 2} and G _{4n / 2} corresponding to all the photodiodes, and at the same time, odd-numbered transfer gate electrodes G ₁₁ , G ₃₁ , G ₁₂ , and G _{32 to} G _{32.
Since a} potential barrier occurs below _{1n / 2} and G _{3n / 2} ,
All pixel signals are transferred to these potential wells (transfer pixels) via the transfer gate Tg without being mixed with each other. Then, the field shift signal φ
_The transfer gate Tg is cut off again when _FS goes low again.

Then, during subsequent time t ₂ fast charge transfer period T _VBF, transfers all of the pixel signals at high speed from the light receiving unit 7 to the storage section 8.
Then, the pixel signals of two rows are mixed before the high-speed transfer, and then transferred to the storage unit 8.

That is, as shown in FIG. 22 and FIG. 23, in the high-speed charge transfer period T _VBF, set signal phi _H is always "M" level, the signal phi _G timing is equal to inverted signal of the signal phi _A Signal. Then, as shown in FIG. 22, in advance before performing the high-speed transfer, P ₁ and P _2, P ₃ and P _4, P ₅ and P ₆ · · · ·
The signals from the photodiodes are mixed. In the storage section, the shift register 14 applies a signal of "M" level to the signal φ _SIN by the read operation of the previous field, and the signals S _{S1 to} S S are synchronized with the synchronization signal φ _{SA.
Sn /} All output ₄ has output the "M" level, the transistor d ₁₁ to d _{4n / 4} is turned on in the second driving circuit 13 in synchronism with the signal S _S1 to S _{Sn / 4} It has become.

As a result, the signal φ is output via the transistors d _{11 to} d _{4n / 4.
1} to [phi] ₄ is applied to the transfer gate electrodes g ₁₁ ~g _{4n / 4,} the transfer gate signal S ₁₁ ~S _{4n / 4.} Further, signals φ _{1 to} φ ₄ are directly applied to the transfer gate electrodes I _{11 to} I _{4n / 2 of} the light receiving section, and high-speed transfer is performed at a timing according to normal four-phase driving.

Then, as shown in FIG. 22 and FIG. 23, before the pixel signal is transferred to the row closest to the horizontal load transfer path 10 in the accumulation unit 8, the input of the signal φ _S1N of the shift register 14 is When an L "level signal is applied, the signals S _{S1 to} S S from the timing of the synchronization signal φ _SA immediately after the pixel signal is transferred to the row closest to the horizontal charge transfer path 10 in the storage section.
_{Sn / 4} sequentially inverts from the “M” level to the “L” level, and the transistors d _{11 to} d _{4n / 4 in} the second drive circuit 13 are synchronized with these signals S _{1 to} S _{Sn / 4.} Are turned off sequentially in groups of four. As a result, the signals φ ₁ to φ ₄ are not sequentially applied to the transfer gate electrodes g _{11 to} g _{44 / n of} the storage unit 8 in groups of _four, so that the storage units 8 are not applied.
The operation of the vertical charge transfer path is stopped from the side close to the horizontal load transfer path 10, and one signal charge is accumulated in two electrodes.

Further, the high-speed charge transfer operation at the time of the odd-field scanning reading will be described with reference to a typical example shown in FIG. FIG. 3 shows the operation of a certain vertical charge transfer path, and
In the case where there are eight rows of photodiodes inside, and the transfer operation of the vertical charge transfer path is performed by 16 transfer gate electrodes, and the vertical charge transfer path of the storage section 8 is provided with 8 transfer gate electrodes Is shown. or, Is a signal charge in the transfer pixel, and □ is a potential barrier or an empty transfer pixel.

First, the signal charge q ₁ to q ₈ at time t ₂ is field shift to the transfer pixels, at time t _2a, q ₁ and q _2, q ₃ and q _4, q ₅ and q
_6, a combination of q ₇ and q ₈ are pixel mixture signal charge at time t _2a is stored under one of the electrodes of the vertical transfer gate electrode. Then, the signal charges (q ₁ + q ₂ ), (q ₃ + q ₄ ), (q ₅ + q ₆ ), (q ₇ +
Transfer q ₈₎ starts, "20" output S _S1 of the shift register 14 at the timing of the "L" level, the transfer gate electrodes g
₁₁ to g ₄₁ is stopped, mixed signal charge (q ₁ + q ₂₎ is held under the transfer gate electrodes g _21.

Then, "28" signal S _S2 at the timing of the "L" level, the gate electrode g ₁₂ to g ₄₂ is stopped, mixed pixel signal (q ₃ +
q ₄₎ is the gate electrode g _41, mixed pixel signal (q ₅ + q ₆₎ is held under the gate electrode g _22, "35" mixed pixel signal at a timing of (q ₇ + q ₈₎ a gate electrode g ₄₂ And the transfer operation is completed.

In this way the accumulation unit 8, by the transfer gate electrode is gradually stopped from the side near to the horizontal transfer path 10 in this order, mixed pixel signal _{(q 1 + q 2),} (q 3 + q 4), (q 5 + q 6 ), (Q ₇ +
q ₈ ) is accommodated in the transfer element of the storage unit 8. Next, referring again to FIGS. 20 and 21,
After the elapse of the vertical blanking period _TVB , the read operation of the mixed pixel signal is started in synchronization with the horizontal scanning timing.

That is, the first horizontal blanking period T _HB (time t _{3 to} t ₄
), The signal φ _G is always at the “L” level.
All the NMOS transistors in the first drive circuit 10 are turned off, and are electrically disconnected from all the transfer gate electrodes. Further, although the start pulse signal φ _IN is not applied to the shift register 14, the signals φ _SA , φ _SB
Yet all the output signals S ₁₁ ~S _{1n / 4} is "L" but be applied
The level remains, and the signal charge transfer operation is not performed in the vertical charge transfer path in the light receiving section 8.

Next, a first horizontal scanning period T _HB (period from time t ₄ ~t ₅₎
In addition, the horizontal charge transfer path 10 performs horizontal transfer in synchronization with the gate signals α _{1 to} α ₄ at predetermined timings according to the four-phase drive method or the two-phase drive method, so that unnecessary charges in the horizontal charge transfer path 10 are reduced. Discard outside.

Next, the second horizontal blanking period T _HB (time t ₅
In ~t period _6), the first driving signal S _S1 only signal phi _A of the output terminals of the shift register _14, in synchronism with the phi _B by "M" level, other drive signals S _S2 to S _S2n is "L When the level becomes “level”, only the first set of NMOS transistors d ₁₁ , d ₂₁ , d ₃₁ and d ₄₁ related to the drive signal S _S1 in the second drive circuit 13 become conductive.

Then, four-phase timing signals φ ₁ , φ ₂ , φ ₃ , φ ₄ for performing the vertical charge transfer during a period in which only the drive signal S _S1 is at the “M” level are input to the second drive circuit 13. Therefore, the first to fourth first set of gate signals S ₁₁ ,
Only the timing signals φ ₁ , φ ₂ , S ₂₁ , S ₃₁ , S ₄₁
It becomes equal to φ ₃ and φ _4, and the charge transfer operation is performed by the first to fourth gate electrodes g ₁₁ , g ₂₁ , g ₃₁ , and g ₄₁ of the first set. As a result, the first closest to the horizontal charge transfer path 10
The pixel signals in the second row are transferred to the horizontal charge transfer path 10, and the pixel signals in the second row move to the position in the first row.

Next, in the second horizontal scanning period T _1H (time period from t _{6 to} t ₇ ), the signal change to the transfer gate electrodes g _{11 to} g _{4n / 4} stops, while the horizontal charge transfer path 10 Is a gate signal α _{1 at} a predetermined timing according to the four-phase driving method or the two-phase driving method.
By performing horizontal transfer in synchronism with to? _4, the first one
The pixel signals for the rows are read at the timing of the dot sequential scanning.
Next, in a period of time t ₇ ~t _8, by repeating the same operation as the time t ₅ ~t _6, reading out pixel signals of the next line. However, the horizontal blanking period T _{HB from} time t _{7 to} t ₈
Then, the drive signals S _S1 and S _{S2 of} the shift register 14 are simultaneously at “M” level, and the remaining drive signals S _{S3 to} S _{Sn / 4} are at “L” level. As a result, the first to fourth first set of gate electrodes g _{11 to} g ₄₁ and the fifth to eighth second set of gate electrodes g 11
₁₂ to g ₄₂ becomes a to be driven by the gate signals S ₁₁ to S ₄₁ and S ₁₂ to S ₄₂ is equal to the timing signal phi ₁ to [phi] _4, the pixel signals under these gate electrodes are vertically transferred.

Then, in the next horizontal scanning period T _IH from time t _8, reads the horizontal charge transfer path 10 pixel signals of the second row in the dot sequential timing.

Then, by repeating the same charge transfer operation, the output of the shift register 14 gradually expands to the “M” level, so that the signal charges in the remaining rows are also read.

Then, the signal charges of the last row (the side closest line to the light-receiving unit 7), the horizontal charge transfer in Fig. 20 and the duration of the 21 time t ₉ ~t ₁₀ (shown a timing enlarged in FIG. 15) to road 10 are vertically transferred, further read out by the horizontal charge transfer path 10 to the horizontal transfer period of time t ₁₀ ~t _11, all the signal charges read in the odd field thus completing.

When the scanning and reading of the odd field are completed, the scanning and reading of the even field are performed. In addition,
As described with reference to FIG. 19, the operation for exposing the image of the even field is almost completed during the period of scanning and reading out the pixel signal of the odd field.

Timing of the scanning reading of the even field in the timing of the high-speed transfer period T _VBF only slightly different from the timing of the scanning reading of the odd field, the timing of horizontal scanning blanking period T _HB and a horizontal scanning period T _IH is the 20
It is almost the same as the timing shown in FIG. 21 and FIG. That is, each time point for explaining the operation of the odd field scan readout.
Time points (t ₁₂ ) to (t ₂₁ ) corresponding to t _{2 to} t ₁₁ indicate the timing of the even-numbered field scanning readout.

If Assuming that shall complete the exposure of even fields at the time (t _12), by performing the time (t ₁₂₎ the same operation as the time t ₂ in the even-numbered transfer gate electrode G
_{21, G 41, G 22,} G 42 ~G 2n / 2, G 4n / 2 potential well in correspondence to all the photodiodes under at the same time (transfer pixels) is generated, the odd-numbered transfer gate electrode G
₁₁ , G ₃₁ , G ₁₂ , G _{32 to} G _{1n / 2} , a potential barrier is generated under G _{3n / 2} , and all the pixel signals are not mixed with each other, and these potential wells are transferred through the transfer gate Tg. (Transfer pixel). Signals φ ₂ , φ ₄
Becomes "M" level again, so that the transfer gate Tg is shut off again.

Next, as shown in FIG. 25 and FIG. 26, at the time point (t ₁₂₎ followed by high-speed charge transfer period T _VBF, signal phi _H is always set to "M" level, the signal phi _G signal phi _A Is a signal having the same timing as the inverted signal of.

Then, as shown in FIG. 25, before performing high-speed transfer (time points t _2a , t _2b , t _2c , t _2d ), P ₂ and P ₃ , P ₄ and P ₅ , P ₆ and P ₇
The signals from the photodiodes are mixed. Then, in the shift register 14, an “M” level signal is applied to φ _SIN by a read operation of the previous field.
All the signals S _{S1 to} S _{Sn / 4} output “M” level in synchronization with the synchronization signals φ _SA and φ _SB , and these signals S _S1
To the transistor in the second drive circuit 13 in synchronization with S _{Sn / 4}
d _{11 to} d _{4n / 4} are on. As a result, the signal phi ₁ to [phi] ₄ via the transistor d ₁₁ ~d _{4n / 4} is applied to the transfer gate electrodes g ₁₁ ~g _{4n / 4,} the transfer gate signal S ₁₁ ~
S _{4n / 4} . Further, the transfer gate electrodes I _{11 to} I
_{4n / 2} In the signal phi ₁ to [phi] ₄ is applied directly, performs high-speed transfer at a timing similar to that for ordinary four-phase drive.

Then, as shown in FIG. 25 and FIG. 26, before the pixel signal is transferred to the row closest to the horizontal charge transfer path 10 in the storage section 8, the input of φ _S1N of the shift register 14 becomes “L”. "
When the level signal is applied, the pixel signals are stored in the storage unit 8 and the signals S _{S1 to} S _{Sn / 4 start} from the timing of the synchronization signal φ _SA immediately after being transferred to the row closest to the horizontal charge transfer path 10.
Are sequentially inverted from the “M” level to the “L” level, and the transistors d _{11 to} d _{4n / 4 in} the second drive circuit 13 are driven to ₄ in synchronization with the signals S _{S1 to} S _{Sn /} 4. Each set is turned off sequentially.

As a result, in the pair of four-by-four to the transfer gate electrodes g ₁₁ ~g _{44 / n} of the storage portion 8, sequential signals phi ₁ to [phi] ₄ is no longer applied, the vertical charge transfer path of the storage section 8 Is stopped from the side near the horizontal charge transfer path 10, and one signal charge is accumulated in two electrodes.

In this way, the same operation as the odd field is performed,
The combination of the mixed signal charges is different. Further, a description will be given of a high-speed charge transfer operation at the time of scanning and reading out an even-numbered field, with reference to a typical example shown in FIG. FIG. 3 shows the operation of a certain vertical charge transfer path. The light receiving section 7 has eight rows of photodiodes and the transfer operation of the vertical charge transfer path.
This is performed by using 16 transfer gate electrodes, and the case where eight transfer gate electrodes are provided in the vertical charge transfer path of the accumulation section 8 is shown. or, Is a signal charge in the transfer pixel, and □ is a potential barrier or an empty transfer pixel.

First, at time (t ₁₂ ), the signal charges q _{1 to} q ₈ are field-shifted to the transfer pixel, and at time t _12a , q ₂ and q ₃ , q ₄
q _5, q ₆ and q ₇ are mixed pixel, one of the transfer gate electrode at a time t _12d stored under the transfer gate electrode. The mixed pixel signals (q ₁ ) and (q ₂ +
The transfer of (q ₃ ), (q ₄ + q ₅ ), (q ₆ + q ₇ ), and (q ₈ ) starts. At the timing of “20”, the output S _S1 of the shift register 14 becomes “L” level, and the transfer gate electrode g ₁₁ to g ₄₁ is stopped,
Pixel signal (q ₁₎ is first held under the transfer gate electrodes g _21.

Then, at the timing of "28", the signal S _S2 becomes "L" level, the transfer gate electrode g ₁₂ to g ₄₂ is stopped, mixed pixel signals (q ₂ + q _3), is (q ₄ + q ₅₎ Transfer It is held below the gate electrodes g ₄₁ and g ₂₂ .

Similarly, the mixed pixel signals (q ₆ + q ₇ ) and (q ₈ ) are held at the transfer gate electrodes g ₂₁ and I ₂₁ at the timing “35”.

Note that, in this typical example, a case where eight signal charges are transferred is shown. Generally, when n signal charges q _{1 to} q _n are transferred, ( q ₁ ), (q ₂ + q ₃ ) on the second line, (q ₄ + q ₅ ) on the third line,..., n / 2
The mixed pixel signal of (q _n-1 + q _n ) is transferred to the row.

Next, referring again to FIGS. 20 and 21, when the vertical blanking period _TVB elapses, the read operation of the mixed pixel signal is started in synchronization with the horizontal scanning timing.

That is, the first horizontal blanking period T _HB (time (t ₁₃₎
In ~ period (t _14)), the signal phi _G is always "L" level, all the NMOS transistors of the first drive circuit 10 is rendered non-conductive, electrically from all of the transfer gate electrodes Be separated.

Also, the shift register 14 receives the signal φ _SA of the first cycle,
Even if φ _SB is applied, all the outputs S _{S1 to} S _{Sn / 4} are still at the “L” level, so that the transfer operation of the signal charge is not performed in the storage unit 8.

Next, a first horizontal scanning period T _HB (time (t ₁₄₎ ~
(Period (t ₁₅ )), the horizontal charge transfer path 10 receives the gate signal α at a predetermined timing according to the four-phase driving method or the two-phase driving method.
By performing horizontal transfer in synchronization with the ₁ to? _4, discarding the unnecessary charges in the horizontal charge transfer path 10 to the outside.

Next, the second horizontal blanking period T _HB (time (t
In ₁₅₎ ~ (period t _16)), only the driving signal S _S1 of the first output terminal of the shift register 14 the signal phi _A, phi synchronization with "M" level _B, the other of the drive signal S _S2 to S _{When S2n} goes to the “L” level, the drive signal S _{S1 in} the second drive circuit 13
The first set of NMOS transistors d ₁₁ , d ₂₁ , d ₃₁ , d
Only ₄₁ becomes conductive.

Then, during a period in which only the drive signal S _S1 is at the “M” level, the four-phase timing signal φ for performing the vertical charge transfer is set.
₁ , φ ₂ , φ ₃ , φ ₄ are input to the second drive circuit 13, so that the first to fourth first set of gate signals S ₁₁ , S _21,.
Only S ₃₁ and S ₄₁ are timing signals φ ₁ , φ ₂ , φ ₃ , φ ₄
And the first to fourth gate electrodes of the first set
the performing the charge transfer operation in _{g 11, g 21, g 31} , g 41.
As a result, the first row of pixel signals near the horizontal charge transfer path 10 are transferred to the horizontal charge transfer path 10, and the second row of pixel signals move to the position of the first row.

Next, the second horizontal scanning period T _1H (time (t ₁₆ ))
In (t ₁₇₎ period), the change of the signal is stopped to the transfer gate electrodes g ₁₁ to g _{4n / 4,} whereas, the predetermined timing at which the horizontal charge transfer path 10 pursuant to the four-phase drive method or the two-phase driving mode By performing horizontal transfer in synchronization with the gate signals α _{1 to} α ₄ , the pixel signals in the first first row are read out at the timing of point-sequential scanning.

Next, in a period of time _{(t 17) ~ (t 18} ), by repeating the same operation as when _{(t 15) ~ (t 16} ),
The pixel signal of the next column is read. However, at the time (t ₁₇ )
~ In the horizontal blanking period T _HB of (t _18), the driving signal S _S1 and S _S2 of the second shift register 14a at the same time "M" level, the remaining drive signal _{S S3 ~S Sn / 4 "L} " Level.
As a result, the first to fourth first set of gate electrodes g _{11 to} g _11
41, fifth to eighth second set of gate electrodes g ₁₂ to g
₄₂ is a gate signal S equal to the timing signals φ _{1 to} φ _4
11 to S ₄₁ and S ₁₂ to S becomes ₄₂ to be driven by the pixel signals under these gate electrodes are vertically transferred. In the next horizontal scanning period T _1H from the time point (t ₁₈ ), the horizontal charge transfer path 10 reads the pixel signals of the second column at dot sequential timing. Then, by repeating the same charge transfer operation, the output of the shift register 14 gradually expands to the “M” level, so that the signal charges in the remaining rows are also read.
The signal charges in the last row (the row closest to the light receiving section 7) are
Is the period to the vertical transferred to the horizontal charge transfer path 10 at the time of 20 view and FIG. 21 _{(t 19) ~ (t 20} ), further, the time (t ₂₀₎ ~
During the horizontal transfer period (t ₂₁ ), the read is performed by the horizontal charge transfer path 10, and the reading of all signal charges for the even field is completed.

As described above, according to this embodiment, since the area of the storage section is reduced, a small-sized FIT type charge-coupled solid-state imaging device can be realized. In this embodiment, the vertical 2
Although an example of pixel mixture has been described, frame reading in which only odd rows are read in odd fields and only even rows are read in even fields is also possible.

〔The invention's effect〕

As described above, according to the charge-coupled solid-state imaging device of the present invention, the photoelectric conversion element in the light receiving unit and the vertical charge transfer path are formed separately, and after the exposure, the photoelectric transfer element is transferred from the photoelectric conversion element to the vertical charge transfer path. Since the scanning readout is performed after that, the electronic shutter function is provided, and the pixel signals in the vertical charge transfer path are sequentially transferred from those located on the side of the horizontal charge transfer path in a so-called domino-down manner. The number of transfer gate electrodes can be reduced, and the vertical resolution can be improved. Field storage can be performed in half the area of the conventional field storage unit, and the size of the semiconductor chip can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an electronic still camera to which a charge-coupled solid-state imaging device according to the present invention is applied, FIG. 2 is a schematic configuration diagram of a charge-coupled solid-state imaging device of a preceding embodiment, and FIG. FIG. 4 is an explanatory diagram showing a main part structure and a peripheral circuit configuration of a light receiving area in the embodiment shown in FIG. 4, FIG. 4 is a circuit diagram of a shift register applied in the embodiment, FIG. 5 and FIG. FIG. 7 is a timing chart for explaining the operation of the shift register shown in FIG. 7, FIG. 7 is a longitudinal sectional view taken along the line BB 'in FIG. 3, FIG. 8 is an explanatory view schematically showing the scanning read operation, FIG. FIG. 10 is a timing chart showing the scanning read operation in detail, FIGS. 11 and 12 are timing charts showing the operation in the high-speed charge transfer period in FIGS. 9 and 10 in detail, and FIG. Explanatory diagram showing the operation of the embodiment in a simple case FIGS. 14, 15 and 16 are timing charts for explaining the operation during the horizontal blanking period in FIGS. 9 and 10, and FIG. 17 is a charge-coupled type of the embodiment of the present invention. FIG. 18 is a schematic configuration diagram of a solid-state imaging device, FIG. 18 is an explanatory diagram showing a main part structure and a peripheral circuit configuration of a light receiving unit and a storage unit in the embodiment, and FIG. 19 is a schematic diagram illustrating a scanning read operation of the embodiment. FIGS. 20 and 21 are timing charts showing the scanning read operation of the embodiment in detail, and FIGS. 22 and 23 further show the operation during the high-speed charge transfer period in the case of odd field scan read. FIG. 24 is a timing chart showing details, FIG. 24 is an explanatory diagram showing the operation in the high-speed charge transfer period in the case of the odd-numbered field scanning readout of the embodiment, and FIGS. 25 and 26 are the even-numbered field scanning readout. Fast charge transfer in case of Further a timing chart showing in detail the operation of the period, 27 is an explanatory diagram showing the case a simple operation at a high speed charge transfer period in the case of the even field scanning reading of the embodiment. Explanation of reference numerals: 1; imaging optical system 2; mechanical diaphragm mechanism 3; charge-coupled solid-state imaging device 4; signal processing circuit 5; recording mechanism 6; synchronization control circuit 7; light receiving unit 8; storage unit 10; transfer paths 12, 13, 14; drive circuit 14a, 14b; shift register L ₁ ~L _m; vertical charge transfer path _{M 11, M 21, M 31} , M 41 ~; NMOS transistor _{D 11, D 21, D 31} , D _41- ; NMOS transistors d ₁₁ , d ₂₁ , d ₃₁ , d _41- ; NMOS transistors m ₁₁ , m ₂₁ , m ₃₁ , m _41- ; NMOS transistors G ₁₁ , G ₂₁ , G ₃₁ , G _41- ; transfer Gate electrodes g ₁₁ , g ₂₁ , g ₃₁ , g ₄₁ ；; transfer gate electrodes Q ₂₁ , Q ₄₁ , Q ₂₂ , Q ₄₂ ；; transfer gate electrodes

Continuation of the front page (72) Inventor Kazuhiro Kawajiri 798 Miyadai, Kaisei-cho, Ashigara-gun, Kanagawa Fuji Photo Film Co., Ltd. (56) References JP-A-2-31572 (JP, A) JP-A-63-114377 JP, A)

Claims (1)

(57) [Claims] A plurality of photoelectric conversion elements corresponding to pixels are arranged in a matrix in a row direction and a column direction, and a vertical charge transfer path is formed adjacent to each photoelectric conversion element group arranged in a column direction. And a storage unit having a vertical charge transfer path connected to these vertical charge transfer paths of the light receiving unit. The pixel signal generated in the pixel is transferred to the vertical charge transfer path of the light receiving section. Thereafter, by applying a gate signal at a predetermined timing to the transfer gate electrode of the vertical charge transfer path of the light receiving section and the accumulation section, the pixel signal is transferred at high speed to the vertical charge transfer path of the accumulation section, and further, In a charge-coupled fixed imaging device that applies a gate signal at a predetermined timing to a transfer gate electrode of a vertical charge transfer path and scans and reads out a pixel signal for each row by a horizontal charge transfer path, Are provided two for each photoelectric conversion element, and the number of transfer gate electrodes in the storage section is formed to be half of the number of transfer gate electrodes in the light receiving section. A predetermined number of sets of gate electrodes are applied, a gate signal at a predetermined timing is applied, and transfer gate electrodes adjacent to each other in the storage section are set to the same number as the number of transfer gate electrodes in each set in the light receiving section. The high-speed transfer is performed by stopping the application of the gate signal from the pair closer to the horizontal charge transfer path. At the time of the scan reading, a predetermined number of transfer gate electrodes adjacent to each other in the storage unit are grouped. A charge-coupled solid-state imaging device that performs scanning readout by sequentially applying gate signals at a predetermined timing from the set of transfer gate electrodes closest to the horizontal charge transfer path side .