JPH0817824A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To improve reliability in fine wiring by increasing migration resistance at a low resistance and improving the adhesion force of Cu layer with a weak adhesion force with a diffusion-prevention layer. CONSTITUTION:A wiring is formed so that a first lamination structure which is subjected to patterning by successively depositing W layer 3, Ti layer 4, and Cu layer 5 is heat-treated in an atmosphere containing nitrogen gas and a second lamination structure consisting of the TiW layer 7, Ti layer 4, Cu-Ti layer 8, and Cu layer 5 and the upper surface and side surface are coated with TiN layer 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art Conventionally, Al has been used as a wiring material for semiconductor devices.
Alternatively, an Al alloy is widely used. But LS
As the integration of I increases, further miniaturization advances in the future, and in the case of Al wiring or Al alloy wiring, a delay in signal transmission speed due to a high resistance value and a decrease in reliability due to low migration resistance become problems. On the other hand, Cu is expected as a wiring material replacing Al because it can realize low resistance and high migration resistance, but there are many problems to be solved.

One of the problems when using Cu wiring is Cu.
There is diffusion prevention. Therefore, a structure in which a TiN layer or a TiW layer is formed as a diffusion preventing layer under the Cu layer is used for the Cu wiring.

[0004]

In this conventional semiconductor device, the adhesion between the TiN layer or TiW layer which is the diffusion preventing layer and the Cu layer which is the main component of the wiring is weak, and the Cu layer is not formed during etching. Since peeling occurs, it has been an obstacle to practical use.

An object of the present invention is to provide a semiconductor device having a miniaturized wiring having low resistance and high migration resistance by eliminating peeling of a Cu layer formed on a diffusion prevention layer.

[0006]

According to the present invention, there is provided a semiconductor device comprising:
A laminated structure composed of a TiW layer, a Ti layer, a Cu—Ti layer, and a Cu layer sequentially laminated on an insulating film formed on a semiconductor substrate, and a TiN layer formed by covering the top and side surfaces of the laminated structure And a wiring having a layer.

According to the method of manufacturing a semiconductor device of the present invention, a W (or TiW) layer, a T
sequentially depositing and laminating an i layer and a Cu layer;
Forming a first laminated structure having a wiring pattern by selectively and sequentially anisotropically etching the layer, the Ti layer, and the W (or TiW) layer; and forming the first laminated structure in an atmosphere containing nitrogen gas. , A TiW layer, a Ti layer, a Cu-Ti layer, and a C
A second laminated structure including a u layer and T formed by a reaction of Ti atoms and nitrogen diffused on the surface of the second laminated structure and covering the upper surface and the side surface of the second laminated structure.
forming an iN layer.

[0008]

According to the present invention, a material having a strong adhesive force is inserted between the Cu layer and the diffusion preventing layer. Adhesion depends strongly on the binding energy of molecules at the interface and the interface structure. It has been attempted in the past to increase the binding energy of molecules at the interface by changing the material of the diffusion prevention layer.
However, at the interface between the Cu layer and the diffusion preventing layer, the bond is often an intermolecular force, and a material having a sufficiently high adhesive force for practical use has not been found at present.

In the present invention, a Cu—Ti alloy layer and a Ti layer having a high adhesive force are inserted between a Cu layer and a TiW layer serving as a diffusion preventing layer, so that a Cu—Ti alloy layer having a high adhesive force and Can be obtained.

Further, in the present invention, after the Ti layer and the Cu layer are deposited and patterned, heat treatment is performed in an N ₂ or N ₂ + H ₂ atmosphere to form a Cu—Ti layer and a TiN layer on the upper and side surfaces. Since the steps can be performed simultaneously, the process is simplified. The formation of the Cu-Ti layer is caused by slight interdiffusion at the interface between the Cu layer and the Ti layer, and the formation of the TiN layer on the upper surface and side surfaces is caused by the diffusion of Ti to the upper surface and side surfaces of the Cu layer. . When only the diffusion prevention layer is the underlayer as in the prior art, mutual adhesion cannot be performed, and therefore the adhesion force depends only on the intermolecular force, but in the present invention, the Ti layer as the adhesion layer is not limited to diffusion prevention. Therefore, the adhesive force can be increased not only by the binding energy of the molecule but also by the change of the interface structure due to diffusion.

There is a concern that the specific resistance of the wiring may increase due to the diffusion of Ti. However, the diffusion of Ti into the upper surface and the side surface of the Cu layer is due to the diffusion in the Cu grain boundaries. Since the layer formed is thinner than the Cu layer, in either case, the specific resistance is not affected at a practical level.

[0012]

Embodiments of the present invention will now be described with reference to the drawings.

FIGS. 1A to 1C are sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to a first embodiment of the present invention.

First, as shown in FIG. 1A, an SiO ₂ film 2 is formed on one main surface of a Si substrate 1 by a thermal oxidation method or a CVD method.
Is formed to a thickness of 10 to 1000 μm, and a W layer 3 having a thickness of 10 to 100 μm 3 is formed on the SiO ₂ film 2.
00 μm Ti layer 4, 10-500 μm thick Cu layer 5
Are sequentially deposited and laminated by a sputtering method or a CVD method.

Next, as shown in FIG. 1B, the Cu layer 5, the Ti layer 4 and the W layer 3 are selectively and sequentially etched by an ion milling method to form a first laminated structure of a wiring pattern. .

Next, as shown in FIG. 1 (c), in an N ₂ gas or N ₂ + H ₂ gas atmosphere,
When the heat treatment is performed for 0 minutes to 2 hours, Ti atoms diffused from the Ti layer 4 to the surfaces of the Cu layer 5 and the W layer 3 react with N ₂ gas to cover the top and side surfaces of the laminated structure.
At the same time as the formation of Ti, a TiW layer 7 is formed by the mutual diffusion of the W layer 3 and the Ti layer 4, and a Cu—Ti layer 8 is formed by the mutual diffusion of the Ti layer 4 and the Cu layer 5, and is covered with the TiN layer 6. The TiW layer 7, Ti layer 4,
A wiring having a second laminated structure in which the Cu—Ti layer 8 and the Cu layer 5 are laminated is formed, and a fine wiring having a high adhesive force and a high Cu diffusion preventing ability can be obtained.

FIGS. 2A to 2C are sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to a second embodiment of the present invention.

First, as shown in FIG. 2A, the thickness 10 formed on the Si substrate 1 by the same process as in the first embodiment.
Approximately 1000 μm on the SiO ₂ film 2 by sputtering or C
A TiW film 9 having a thickness of 10 to 100 μm, a Ti layer 4 having a thickness of 5 to 100 μm, and a Cu layer 5 having a thickness of 100 to 500 μm are sequentially deposited and laminated by the VD method.

Next, as shown in FIG. 2B, the Cu layer 5, the Ti layer 4, and the TiW layer 9 are selectively etched sequentially to form a laminated structure having a wiring pattern.

Next, as shown in FIG. 2 (c), in an atmosphere of N ₂ gas or N ₂ + H ₂ gas, 500 to 1000 ° C., 1
When the heat treatment is performed for 0 minutes to 2 hours, the TiW layer 9, the Ti layer 4, the Cu—Ti layer 8, and the Cu layer 5 are sequentially stacked from the substrate side in the same manner as in the first embodiment. T
Since the wiring covered with the iN layer 6 is formed, there is an advantage that the lower limit temperature of the heat treatment can be lowered as compared with the first embodiment.

It should be noted that instead of the Si substrate 1, GaAs, In
A semiconductor substrate made of P, AlGaAs, SiGe or the like may be used, and Si _x N ₂ may be used instead of the SiO ₂ film 2.
A dielectric film such as a _1-x film, a PSG film, or a BPSG may be used.

[0022]

As described above, according to the present invention, the adhesion of the Cu layer is achieved by interposing a Ti layer between the Cu layer and the underlying diffusion layer preventing layer and forming a Cu-Ti layer by heat treatment. To prevent the Cu layer from peeling off in the etching step or the like.
The layer can prevent oxidation of the Cu layer and a reaction with the interlayer insulating film, and have an effect that a low-resistance and highly reliable fine wiring can be obtained.

[Brief description of drawings]

1A to 1C are cross-sectional views of a semiconductor chip in the order of steps for explaining a manufacturing method according to a first embodiment of the present invention.

2A to 2D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to a second embodiment of the present invention.

[Explanation of symbols]

1 Si substrate 2 SiO ₂ film 3 W layer 4 Ti layer 5 Cu layer 6 TiN layer 7, 9 TiW layer 8 Cu-Ti layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication C23C 16/34 H01L 23/12 H01L 23/12 N

Claims (2)

[Claims] 1. A TiW layer, a Ti layer, a Cu—Ti layer, which are sequentially laminated on an insulating film formed on a semiconductor substrate.
A semiconductor device comprising: a wiring having a stacked structure including a Cu layer; and a TiN layer formed by covering an upper surface and side surfaces of the stacked structure. 2. The method according to claim 1, wherein the insulating film is formed on a semiconductor substrate.
(Or TiW) layer, a Ti layer, and a Cu layer are sequentially deposited and laminated, and a Cu layer, a Ti layer, and a W (or TiW) layer are selectively anisotropically etched sequentially to form a wiring pattern. Forming a TiW layer and a TiW layer formed by inter-diffusion by heat-treating the first stacked structure in an atmosphere containing nitrogen gas and sequentially stacked from the substrate side.
Layer, a Cu-Ti layer, a second laminated structure composed of a Cu layer, and a top surface and a side surface of the second laminated structure formed by a reaction of Ti atoms and nitrogen diffused on the surface of the second laminated structure. And a step of forming a TiN layer to cover the semiconductor device.