JPH02111052A - Formation of multilayer interconnection - Google Patents

Abstract

PURPOSE:To enhance an integration density without damaging reliability by a method wherein, before an interlayer insulating film is formed, an interlayer connection layer is formed on a first wiring layer. CONSTITUTION:A first wiring layer 14 having an interlayer connection layer 14n protruding from the surface is formed in one part on the surface of a substrate 10; after that, an interlayer insulating layer 22A covering the first wiring layer 14 is formed so as to expose the surface top of the interlayer connection layer 14n. Then, a second wiring layer 24 is formed on the interlayer insulating layer 22A so as to come into ohmic contact with the surface top of the interlayer connection layer 22A. Thereby, before the interlayer insulating layer is formed, the interlayer connection layer can be formed surely to be small-sized; accordingly, an integration density and reliability are enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for forming multilayer wiring used in the manufacture of integrated circuit devices and the like, and particularly relates to an improvement in technology for connecting upper and lower wiring layers.

[Summary of the Invention] The present invention provides a method for forming a first wiring layer having an interlayer connection layer, and then forming a second wiring layer on the first wiring layer so as to be in ohmic contact with the interlayer connection layer via a living room insulation layer. By forming this, the degree of integration and reliability are improved.

[Prior Art] Conventionally, as a multilayer wiring forming method, the method shown in FIG. 1θ and FIG. 11 is known.

In the step shown in FIG. 10, a first wiring layer 3 is formed by depositing a wiring material such as AfL on the insulating layer 2 formed on the surface of the semiconductor substrate 1 and patterning it.

After forming an interlayer insulating layer 4 on the upper surface of the substrate by a CVD (chemical paper deposition) method or the like, a connection hole 4A is formed between the layers to expose a part of the first wiring layer 3 by a selective etching process or the like. It is formed on the insulating layer 4.

Next, in the step shown in FIG. 11, a suitable wiring material is deposited on the upper surface of the substrate and patterned so that the second wiring layer 5 is in ohmic contact with the first wiring layer 3 through the connection hole 4A. form.

[Problems to be Solved by the Invention] According to the above-mentioned prior art, when forming the connection hole 4A in the process of FIG. It is necessary to provide a margin d depending on the alignment accuracy. If such a margin is not provided, a contact hole may be formed as shown in 4A', for example, and the insulating layer 2 will be etched and the step will become large, so the second wiring layer 5
The first wiring layer 3 may be thinned by etching, and a good interlayer connection state cannot be obtained, leading to a decrease in reliability.

Furthermore, if the size of the contact hole 4A is made small, step coverage will not be good during metal deposition for forming the wiring layer 5, and disconnection will easily occur at the location shown by the arrow 4a in FIG. 11, resulting in poor reliability. decreases. Therefore, in order to ensure the desired reliability, the size of the connection hole 4A must be increased to a certain extent, and the above-mentioned margin d must also be taken into account, so it occupies a considerable area even as an interlayer connection. is required, which inevitably leads to a decrease in the degree of integration.

An object of the present invention is to easily manufacture a multilayer wiring structure with high integration and reliability.

[Means for Solving the Problems] A method for forming multilayer wiring according to the present invention includes forming a first wiring layer having an interlayer connection layer protruding from a part of one surface, and then forming a first wiring layer having an interlayer connection layer protruding from the surface. An interlayer insulation layer is formed to cover the first wiring layer so as to expose the wiring layer, and a second wiring layer is further formed on the living room insulation layer so as to be in ohmic contact with the upper surface of the interlayer connection layer. It is something to do.

In such a multilayer wiring formation method, after forming the first wiring layer, side spacers are formed on the surface of the first wiring layer so as to surround the interlayer connection layer adjacent to the side thereof. death,
Thereafter, an interlayer insulating layer may be formed as described above.

[Function] According to the multilayer interconnection forming method of the present invention, an interlayer connection layer is formed on the first interconnection layer before forming the first interlayer insulating layer.
The problem of step coverage that occurs in conventional connection hole formation can be avoided, and the interlayer connection layer can be formed as small as desired within processing limits. Therefore, the degree of integration can be improved without impairing reliability.

Furthermore, providing the side spacers as described above can prevent the interlayer connection layer from falling down, which is particularly useful when forming a small-sized interlayer connection layer.

[Example] FIGS. 1 to 8 show a multilayer wiring forming method according to an example of the present invention, and the steps (1) corresponding to each figure are shown in FIGS.
- (8) will be explained in order.

(1) Wiring material layers 14L, 14M, and 14N are sequentially stacked and deposited on the insulating layer 12 made of silicon oxide or the like formed on the surface of the semiconductor substrate lO made of silicon or the like. - As an example, the wiring material layers 14L and 14N are made of A or IQ alloy, and the wiring material layer 14M is made of Ti, which are deposited using a sputtering method. The wiring material layer 14M is used as an etching stopper in the steps shown in FIGS. 2 and 4, which will be described later, and may be thinner than the wiring material layers 14L and 14N. , W, poly-Si, etc. can be used in addition to Ti,
The wiring material layers 14L and 14M may be formed as a single layer of poly-Si.

(2) Next, by selectively etching the wiring material layer 14N using the resist layer 1B corresponding to the desired interlayer connection pattern as a mask, an interlayer connection layer 14n of a desired size made of the remaining portion of the wiring material layer 14N is formed. do. After this, the resist layer 18 is removed.

(3) Next, an insulating material layer is formed to cover the interlayer connection layer 14n on the wiring material layer 14M! 8. The insulating material layer 18 is to become a side spacer in the process shown in FIG. 4, which will be described later.
It is formed by depositing by method D. Insulating material layer 1
As the material 8, silicon oxide etc. can also be used, and if the wiring material layer 14M is not polySi, polyS
i can also be used.

(4) Next, the insulating material layer 18 is subjected to an anisotropic etching process to form side spacers 18A made of the remaining portions of the insulating material layer 18. In this case, side spacer 1
8A is formed so as to surround the interlayer connection layer 14n adjacent to the side thereof, as shown in FIG.
This is useful for preventing 4n from falling over when it is formed small.

(5) Next, selective etching is performed with the interlayer connection layer 14n, side spacers 18A, and part of the wiring material layer 14M masked with the resist layer 20 corresponding to the desired wiring pattern, so that the wiring material layer 14M remains. Part 14m and wiring material layer! A first wiring layer 14 consisting of the remaining 14 lines of 4L is formed. After this, the resist layer 20 is removed.

During the selective etching, the pattern of the resist layer 20 is determined so as to cover at least the outer edge of the side spacer 18A, as shown in FIG. 5, for example. In this way, even if the edge of the resist recedes (side etch) from the position shown by the broken line 20a in FIG. 5 during etching, the side spacer 18A acts as an etching stopper.

It is possible to prevent side etching from spreading to the interlayer connection layer 14n.

(6) Next, the insulating material layer 22 is deposited on the upper surface of the substrate so as to cover the interlayer connection layer 14n, the side spacer +8A, and the first wiring layer 14. The insulating material layer 22 is to become an interlayer insulating layer in the process shown in FIG. 7, which will be described later.

For example, it can be formed with good flatness by applying 5OG (spin-on glass) using a spin coating method. Another method is to deposit the insulating material layer 22 by CVD or the like and then planarize it by resist etchback.

(7) Next, the interlayer insulating layer 22A is formed by etching back the insulating material layer 22 to expose the upper surface of the interlayer connection layer 14n. In this case, side spacer 18A
By using different materials for the side spacer 18A and the insulating material layer 22, thinning of the side spacer 18A can be prevented.

(8) Thereafter, a suitable wiring material is deposited and patterned by a well-known method to form the second wiring layer 24 so as to make ohmic contact with the upper surface of the interlayer connection layer 14n.

Note that in the above embodiment, the patterning for the first wiring layer 14 may be performed before forming the interlayer connection layer 14n. That is, in the process shown in FIG. 1, after forming the wiring material layers 14L, 14M, and 14N,
The wiring material layer 1 is selectively etched using the resist layer 20A corresponding to the desired wiring pattern as a mask.
A wiring stack consisting of the remaining portions of 4L, 14M, and 14N is formed. Then, when the steps shown in FIGS. 2 to 4 are carried out in the same manner as described above, the interlayer connection layer 14n is formed in the step shown in FIG. In the process, side spacers 18A are formed around the interlayer connection layer 14n, and as shown in FIG.
8B is formed. Thereafter, the steps shown in FIGS. 6, 7, and 8 are carried out in the same manner as described above, without going through the step shown in FIG. 5.

[Effect of the invention 1 As described above, according to the present invention, the interlayer connection layer can be reliably formed in a small size before forming the living room insulation layer, so that the effect of improving the density and reliability can be obtained. It is. Further, the provision of side spacers has the advantage that a small-sized interlayer connection layer can be easily formed and manufacturing yield can be improved.

[Brief explanation of drawings]

1 to 8 are cross-sectional views of a substrate showing a multilayer interconnection forming method according to an embodiment of the present invention, FIG. 9 is a top view showing the resist pattern of FIG. 5, and FIGS. 1O and 11 are FIG. 12 is a cross-sectional view of a substrate showing a conventional multilayer wiring formation method. FIG. 12 is a top view showing a connection hole pattern in FIG. 1θ. lO...Semiconductor substrate, 12...Insulating layer, 14L
, 14M. 14N... Wiring material layer, 14n... Interlayer connection layer, 14
...first wiring layer, 18A...side spacer, 22
A... Interlayer insulating layer, 24... Second wiring layer.

Claims (1)

[Claims] 1. (a) forming a first wiring layer having an interlayer connection layer protruding from the surface on a part of the surface; (b) exposing the upper surface of the interlayer connection layer; (c) forming a second wiring layer on the interlayer insulation layer so as to make ohmic contact with the upper surface of the interlayer connection layer; A multilayer wiring formation method including a step of. 2. (a) forming a first wiring layer having an interlayer connection layer protruding from the surface on a part of the surface; (b) forming the interlayer connection layer on the surface of the first wiring layer; (c) forming an interlayer insulating layer to cover the first wiring layer so as to expose the upper surface of the interlayer insulating layer; (d) forming a second wiring layer on the interlayer insulating layer so as to make ohmic contact with the upper surface of the interlayer connection layer.