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JPH0777258B2 - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH0777258B2
JPH0777258B2 JP2066683A JP6668390A JPH0777258B2 JP H0777258 B2 JPH0777258 B2 JP H0777258B2 JP 2066683 A JP2066683 A JP 2066683A JP 6668390 A JP6668390 A JP 6668390A JP H0777258 B2 JPH0777258 B2 JP H0777258B2
Authority
JP
Japan
Prior art keywords
bed
chip
chips
package
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2066683A
Other languages
English (en)
Other versions
JPH03268351A (ja
Inventor
陽一 蛭田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2066683A priority Critical patent/JPH0777258B2/ja
Priority to US07/670,270 priority patent/US5138433A/en
Publication of JPH03268351A publication Critical patent/JPH03268351A/ja
Publication of JPH0777258B2 publication Critical patent/JPH0777258B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、複数の半導体チップを同一のパッケージに実
装した半導体装置（マルチチップパッケージ）に関す
る。
（従来の技術） 従来のマルチチップパッケージを第８図，第９図に示
す。即ち第８図の場合、チップ11は、Fe-42wt％Niアロ
イ等のベッド12上にアルミナフィルム13,Alフィルム14
を介して実装され、チップ間等の配線は、アルミナ13上
のAl配線14により、ボンディングワイヤ15を用いてなさ
れていた。16はベッド12と同材質のリード、17はモール
ド用プラスチックである。
また第９図では、バンプ21によりチップ（例えばLSIメ
モリ用）22を配線基板（ベッド）231,232に実装してい
た。この場合、チップ22のSi基板はパッケージを構成す
る部材とは、直接接していないことになる。第９図中24
はAlフィン、25は高熱伝導接着剤、26はリード、27はム
ライトフランジ、28はアルミナキャップ、29は封止用接
着剤、30は封止用接着剤である。
（発明が解決しようとする課題〕 第８図に示した従来例にあっては、チップ11をAlフィル
ム14及びアルミナフィルム13を介してベッド12上に実装
しているが、プラスチック17でモールドされ、ベッド12
は、アルミナ13があるため、直接外へ引き出されていな
いので、放熱特性が悪い。
第９図に示した従来例にあっては、ベッド231,232からA
lフィン24までの熱伝達特性は向上しているものの、LSI
チップ22とベッド231がバンプにより接続されているた
め、チップ22からの放熱特性は改善されていない。
この様に従来例では、同一パッケージに複数のチップを
搭載した場合に、増加する発熱量に対する対策が不充分
であり、チップ温度の上昇をまねき、回路動作に不良を
引き起こす。
本発明は、同一パッケージに複数のチップを搭載した場
合、問題となる放熱特性を改善することが目的である。
［発明の構成］ （課題を解決するための手段と作用） 本発明は、複数の半導体チップを同一のパッケージに実
装した半導体装置において、前記複数の半導体チップが
直接接着されるベッドまたはパッケージ基板と、このベ
ッドまたはパッケージ基板に接着された前記複数の半導
体チップ間に、チップ表面の高さと略同一の高さで充填
された電気絶縁性の高い樹脂とを具備したことを特徴と
する半導体装置である。
また、本発明は、複数の半導体チップを同一のパッケー
ジに実装した半導体装置において、前記複数の半導体チ
ップがベッドまたはパッケージ基板の両面に直接接着さ
れていることを特徴とする半導体装置である。
即ち本発明では、チップ裏面をベッドまたは基板に直接
接着し、チップ間に電気絶縁性の高い樹脂をチップ表面
とほぼ同じ高さで充填する、もしくはチップ裏面をベッ
ドまたは基板の両面に直接接着することにより、放熱特
性と実装性とを向上させたものである。
（実施例） 第１図に本発明の第１実施例を示す。この実施例では、
半導体チップ41の裏面を直接ベッド42に接着している。
チップ間等に配線は、チップ間にチップ表面とほぼ同じ
高さで充填された絶縁性の高い例えばポリイミド43上に
形成したCu配線44を介してボンディングワイヤー45によ
り行なっている。ベッド42の材質としては、42アロイ
（鉄，ニッケル系合金）、Cu等でよい。チップ41とベッ
ド42との接着は、ポリイミド等の絶縁性接着剤とか導電
性接着剤等で行なってもよい。第１図の構成は、その後
例えば有機性樹脂で封止される。
第１図のようにすれば、チップ41とベッド42との間に、
第８図のアルミナフィルム13等が介在されないため、両
者間の放熱性が良くなる。
また、チップ間に後からポリイミド43を充填するように
しているため、チップ41の実装が簡単で実装性が良く、
しかもチップ間の配置スペースをつめることができて、
実装の高密度化が可能となる。
さらに、ポリイミド43上に形成した配線44を介してチッ
プ間等の配線を行うようにしているため、配線44は微細
加工が可能であり、高密度実装の際に特に有効となる。
第２図は実装方法をセラミックパッケージ51に適用した
場合の第２の実施例の断面図である。チップ41とセラミ
ックパッケージ51との間には、ベッド42があっても、な
くてもよい。第２図中52は放熱フィン、53は配線、54は
ピン（配線端子）、55はリッドである。なお、上記実装
方法をセラミックパッケージによらず、プラスチックパ
ッケージに封止する場合は、樹脂剥離を防止するため、
ベッドにアンカーホールを設けるとよい。
第３実施例を第３図に示す。この実施例では、チップ間
等の接続をTAB（Tape Automated Bonding）により行な
っている。即ちベッド42にポリイミド43を塗布し、Cuの
配線パターン44及び電極61を形成した後（第３図
（ａ））、チップ41をベッド42に直接接着し（第３図
（ｂ））、テープボンディングによりテープ62上の配線
パターン63を用いて、チップ41上の電極64、ポリイミド
上の配線パターン電極45間とか、チップと外部導出リー
ド間等の配線を行なう（第３図（ｃ））。
第４図に示す第４の実施例では、第1,第３の実施例とは
異なり、ポリイミド43上にはCu配線を形成せず、絶縁性
テープ71の下面に配線パターン72を形成している。本実
施例ではチップ41をベッド42に直接接着後、ポリイミド
43を平坦に400〜500μｍほど塗布し（第４図（ａ））、
チップ上パッド部のバンプ部64のみポリイミド43を除去
し（第４図（ｂ））、Cu配線72が形成されたボンディン
グ用テープ71の圧着により、チップ間接続を行なう（第
４図（ｃ））。
第５の実施例を第５図に示す。本実施例では、チップ41
付近はプラスチック81で封止される。即ちチップ41をア
ルミナ基板82に直接接着し、これとリードのインナーリ
ード部83が接してモールドされている。プラスチック81
の封止の場合、樹脂剥離を防止するため、基板82にアン
カーホールを設けるとよい。
第６の実施例を第６図に示す。この実施例では、基板91
には、熱伝導性の良い例えばAlNを用い、基板91の両面
にチップ41が実装されており、インナーリード83で基板
91をはさみ込んでいる。
上述した各実施例では、ベッド42またはこれと同等の役
目をするアルミナ基板91、パッケージ基板51等にチップ
41を直接接着したため、チップ−ベッド又は基板間の熱
抵抗の減少と放熱面積の拡大により、半導体チップから
パッケージ表面までの熱抵抗を大幅に減らすことができ
た。
また、第5,6図に示す構造を採った場合、チップからベ
ッドまたは基板を経てリードへ熱が伝わる経路が形成さ
れるため、熱抵抗に低減にさらに効果がある。
第７図に、従来の熱抵抗と本発明を適用したパッケージ
の熱抵抗を示す。パッケージには放熱フィンはつけてお
らず、無風状態で測定を行った。図から明らかな様に、
本発明により、熱抵抗は従来より30〜50％改善されてい
る。
またTABによりチップ間配線を行った場合、特に第４の
実施例では、チップ間隔を従来の半分程度に減らすこと
ができ、実装密度の向上の点からも効果がある。
なお、本発明は上記実施例に限られず、種々の応用が可
能である。例えば、本発明はベッド，パッケージ等の材
質を実施例で述べたものに限定するものではない。また
例えばTAB配線を用いた場合、全部をTABとしなくても、
一部のみでもよい。
［発明の効果］ 以上説明した如く本発明によれば、放熱効果に優れ、高
密度実装や小型化する際に極めて有効なマルチチップパ
ッケージ型半導体装置が提供できるものである。
【図面の簡単な説明】
第１図は本発明の第１実施例の要部断面図、第２図は本
発明の第２実施例の断面図、第３図，第４図は本発明の
第3,第４実施例の製造工程図、第５図は本発明の第５実
施例の断面図、第６図は本発明の第６実施例の要部の斜
視図、第７図は上記実施例の効果を示す特性図、第８
図，第９図は従来装置の断面図である。 41……チップ、42……ベッド、43……ポリイミド、44…
…配線パターン、45……ボンディングワイヤ、51……セ
ラミックパッケージ、52……放熱ファン、61,64……電
極、62……TAB用テープ、71……テープ、72……配線パ
ターン、81……封止用プラスチック、82……アルミナ基
板、83……インナーリード、91……基板。

Claims (4)

    【特許請求の範囲】
  1. 【請求項１】複数の半導体チップを同一のパッケージに
    実装した半導体装置において、 前記複数の半導体チップがベッドまたはパッケージ基板
    の両面に直接接着されている ことを特徴とする半導体装置。
  2. 【請求項２】前記複数の半導体チップが接着された前記
    ベッドまたはパッケージ基板は、外部リードのインナー
    リード部と接していることを特徴とする請求項１に記載
    の半導体装置。
  3. 【請求項３】前記チップ間および前記チップと前記外部
    リードとの配線が、前記チップ間に充填される樹脂上に
    形成された配線パターンを介してワイヤーまたはTABに
    より行われることを特徴とする請求項２に記載の半導体
    装置。
  4. 【請求項４】前記複数の半導体チップが接着される前記
    ベッドまたはパッケージ基板は絶縁性材料からなり、こ
    れが外部リードのインナーリード部の一部によりはさみ
    込まれていることを特徴とする請求項１に記載の半導体
    装置。
JP2066683A 1990-03-16 1990-03-16 半導体装置 Expired - Lifetime JPH0777258B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2066683A JPH0777258B2 (ja) 1990-03-16 1990-03-16 半導体装置
US07/670,270 US5138433A (en) 1990-03-16 1991-03-15 Multi-chip package type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2066683A JPH0777258B2 (ja) 1990-03-16 1990-03-16 半導体装置

Publications (2)

Publication Number Publication Date
JPH03268351A JPH03268351A (ja) 1991-11-29
JPH0777258B2 true JPH0777258B2 (ja) 1995-08-16

Family

ID=13322976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2066683A Expired - Lifetime JPH0777258B2 (ja) 1990-03-16 1990-03-16 半導体装置

Country Status (2)

Country Link
US (1) US5138433A (ja)
JP (1) JPH0777258B2 (ja)

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US5422514A (en) * 1993-05-11 1995-06-06 Micromodule Systems, Inc. Packaging and interconnect system for integrated circuits
US5380956A (en) * 1993-07-06 1995-01-10 Sun Microsystems, Inc. Multi-chip cooling module and method
US5688716A (en) * 1994-07-07 1997-11-18 Tessera, Inc. Fan-out semiconductor chip assembly
US6848173B2 (en) * 1994-07-07 2005-02-01 Tessera, Inc. Microelectric packages having deformed bonded leads and methods therefor
JP3123638B2 (ja) * 1995-09-25 2001-01-15 株式会社三井ハイテック 半導体装置
US6468638B2 (en) 1999-03-16 2002-10-22 Alien Technology Corporation Web process interconnect in electronic assemblies
US6982478B2 (en) * 1999-03-26 2006-01-03 Oki Electric Industry Co., Ltd. Semiconductor device and method of fabricating the same
US6636334B2 (en) * 1999-03-26 2003-10-21 Oki Electric Industry Co., Ltd. Semiconductor device having high-density packaging thereof
JP3576030B2 (ja) * 1999-03-26 2004-10-13 沖電気工業株式会社 半導体装置及びその製造方法
US6606247B2 (en) 2001-05-31 2003-08-12 Alien Technology Corporation Multi-feature-size electronic structures
US7218527B1 (en) * 2001-08-17 2007-05-15 Alien Technology Corporation Apparatuses and methods for forming smart labels
US7214569B2 (en) 2002-01-23 2007-05-08 Alien Technology Corporation Apparatus incorporating small-feature-size and large-feature-size components and method for making same
US7253735B2 (en) 2003-03-24 2007-08-07 Alien Technology Corporation RFID tags and processes for producing RFID tags
DE102004025684B4 (de) 2004-04-29 2024-08-22 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zum Ausbilden einer Kontaktstruktur zur elektrischen Kontaktierung eines optoelektronischen Halbleiterchips
US7688206B2 (en) 2004-11-22 2010-03-30 Alien Technology Corporation Radio frequency identification (RFID) tag for an item having a conductive layer included or attached
US7690096B1 (en) * 2008-09-19 2010-04-06 Dreamwell, Ltd. Method of manufacturing an aged mattress assembly

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Also Published As

Publication number Publication date
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US5138433A (en) 1992-08-11

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