JPH0773112B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art The structure of a multi-layer wiring of a conventional semiconductor device will be described with reference to FIG. A first Al wiring 2 is formed on a semiconductor substrate 1, and an interlayer insulating film 3 having a silicon oxide film as a main component is formed so as to cover the Al wiring 2. The second Al wiring 4 on the interlayer insulating film 3 and the first Al wiring
In order to electrically connect the wiring 2, the interlayer insulating film 3
A connection hole (contact hole) 5 is opened in the so as to establish conduction.

This conduction yield (probability) sharply decreases as the diameter of the connection hole 5 becomes finer as shown in FIG. In the figure, the line connecting the white dots is the case where the second Al wiring is deposited after the sputter etching, and the line connecting the black circles is the case without the sputter etching. As is clear from the above line, when the diameter is 1 μm, there is almost no conduction. That is, the conduction yield is 99.9% or less. The reason is that an alumina layer is formed on the surface of the first Al wiring 2 exposed through the connection hole 5 by the time the contact hole 5 is opened and the second Al wiring 4 is formed. This is because conduction cannot be achieved even if an Al film that is the second wiring layer is deposited on the alumina layer. However, when the diameter of the connection hole 5 becomes large, defects such as pinholes and cracks exist in the alumina layer, and conduction can be established through these defects. In view of this, in the past, the first
In order to remove the alumina layer on the Al wiring 2, the second wiring 4 was deposited in the same vacuum without being exposed to the atmosphere by sputter etching with Ar ions. As a result, even if the diameter of the connection hole 5 was 1 μm, the conduction yield could be about 99.99% (see FIG. 4).

However, in order to further improve the yield,
Various methods of sputter etching have been improved. As a result, the conduction yield has been improved, but a new problem has occurred. That is, when the first wiring Al2 is connected to the gate electrode, a large amount of Ar ions for the sputter etching are irradiated through the connection hole 5, and the gate oxide film is destroyed by charging. It has been found. The problem of damage due to ion irradiation becomes more and more serious as semiconductor devices become finer and gate oxide films become thinner.

[0005]

As described above, the conventional A
In the method of removing the alumina layer at the portion opened to the connection hole on the Al wiring surface by sputter etching of r ions,
There is a problem that the semiconductor device is damaged, such as breaking the gate oxide film.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of destroying and removing the alumina layer without damaging the semiconductor device.

[0007]

According to the method of manufacturing a semiconductor device of the present invention, a second metal wiring is formed on a first metal wiring formed on a semiconductor substrate via an interlayer insulating film, and the first metal wiring is formed.
And a method of manufacturing a semiconductor device in which a second metal wiring is electrically connected through a connection hole opened in the interlayer insulating film, at least a surface of the first metal wiring exposed in the connection hole and the A step of forming a highly oxidizable metal layer on the surface of the interlayer insulating film, and preventing the second metal wiring from reacting with a material below it on the surface of the highly oxidizable metal layer. A step of forming a barrier metal layer that reinforces the mechanical strength of the second metal wiring and has good adhesion to the second metal wiring, and the second metal on the surface of the barrier metal layer. A step of forming a wiring and a heat treatment are performed so that the second metal wiring is left as it is without reacting with another material due to the barrier function of the barrier metal layer, but is exposed to the connection hole. Metal wiring surface A heat treatment step of the high-resistance oxide layer is reduced with the high oxidizing metal layer, a conductive metal layer,
Is configured to include.

[0008]

In the present invention, the high resistance oxide layer on the first metal wiring is reduced with the highly oxidizing metal when conducting the first and second metal wirings through the connection hole of the interlayer insulating film. To form a conducting metal layer, and the conducting metal layer conducts electricity.
Thus, the high resistance oxide layer on the first metal wiring is reduced by the highly oxidizing metal, so that the first and second metal wirings are surely conducted with high accuracy.

A barrier metal layer is formed between the second metal wiring layer and the semiconductor substrate and the highly oxidizable metal layer. For this reason, it is possible to prevent the second metal wiring layer from reacting with the semiconductor substrate and the highly-oxidizable metal layer to reduce the reliability of the second metal wiring layer. The barrier metal layer reinforces the mechanical strength of the second metal wiring layer.

Further, even when the high resistance oxide layer is reduced by the high oxidation metal layer to form the conductive metal layer, the barrier metal layer causes the second metal wiring to react with the high oxidation metal layer. Is prevented, which improves the reliability of the second metal wiring. Further, although it has a three-layer structure of a highly oxidizable metal layer, a barrier metal layer and a second metal wiring, the crystallographic direction of the barrier metal layer is aligned with the highly oxidizable metal layer and the second metal is provided in the barrier metal layer. The crystal directions of the wiring are aligned. In this way, since the crystal directions of the three layers are aligned, the migration breakdown voltage is improved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of the embodiments of the present invention, FIG.
The related art of the present invention will be described in detail with reference to (c).

As shown in FIG. 1A, the semiconductor substrate (S
i) The first Al wiring 12 is formed on 11. An interlayer insulating film 13 containing a silicon oxide film as a main component is formed so as to cover the Al wiring 12, and the connection hole 1 is formed in the film 13.
5 is formed. At the bottom of this connection hole 15
There is an alumina layer 16 of about 100 Å.

Next, as shown in FIG. 1B, a Ti film 17 is formed on the alumina layer 16 and the interlayer insulating film 13 by 500 times.
Deposited to a thickness of angstrom by sputtering,
The second Al as the second wiring layer without being exposed to the atmosphere
The wiring 14 is deposited to a thickness of 1 μm by the sputtering method similarly to the above.

Next, the second Al wiring 14 and the Ti film 1 are formed.
7 is formed into a desired wiring pattern. Then, the semiconductor device in the intermediate stage thus formed is subjected to N ₂ at 450 ° C.
And heat treatment was performed for 30 minutes in a forming gas containing H ₂ . As a result, as shown in FIG.
The alloy layer 1 is formed on the joint portion between the second Al wirings 12 and 14.
8 is formed. The alloy layer 18 is configured such that the Ti film 17 reduces the alumina layer 16 and is made of titanium, aluminum and oxygen. This alloy layer 1
8 significantly improves the conductivity of the first and second Al wirings 12 and 14.

In the related art described above, the heat treatment is performed after the second Al wiring 14 is deposited. However, the heat treatment may be performed in vacuum after the Ti film 17 is deposited and before the Al wiring 14 is deposited. Further, the substrate temperature may be raised during the deposition of the Ti film 17 to promote the reaction with the alumina layer 16 and the heat treatment may be omitted.

Further, although the Ti film 17 is used in the related art, it is also possible to use a metal having a strong oxidizing power such as Hf, V, Mg, Li and Ni, or an alloy thereof or an alloy containing them. it can.

In accordance with the above-mentioned related art, an experiment was conducted for the connection hole 15 having a thickness of 1 μm. The probability of conduction between the first and second Al wirings 12 and 14 was 99.999% or more. Further, it was checked whether or not the 100 angstrom thick gate oxide film was broken, and it was found that the gate oxide film was not broken at all.

The alumina layer 16 is thin and the Ti film 17 is thin.
Is excessive, the Ti film 17 becomes Si on the substrate 11.
May form an alloy spike and cause a PN junction leak. Therefore, the first Al wiring 12
It is also possible to interpose a TiN layer or a W layer as a barrier layer for preventing the reaction between Al and the substrate (Si) between the Si substrate 11 and the Si substrate 11.

2A to 2C show T as a barrier layer.
This shows an embodiment of the present invention in which the iN layer 17A is used between the second Al wiring 14 and the Ti layer 17.

FIG. 3A shows an intermediate semiconductor device similar to that shown in FIG. As shown in FIG. 2B, a Ti layer 17 and a TiN layer 17A are provided on the semiconductor device.
It is sequentially deposited by the sputtering method without exposing it to the atmosphere. Then, the second Al wiring 14 is deposited by the sputtering method.

Next, the second Al wiring 14, the TiN layer 17A and the Ti layer 17 are formed into a desired wiring pattern. Then, the semiconductor device in such an intermediate stage was subjected to heat treatment at 450 ° C. for 30 minutes in a forming gas composed of N ₂ and H ₂ . As a result, the figure (c)
As shown in, the alloy layer 18A is formed at the joint portion of the first and second Al wirings 12 and 14. The alloy layer 18A
Is configured such that the Ti film 17 reduces the alumina layer 16 and is made of titanium, aluminum, and oxygen.
With this alloy layer 18A, the first and second Al wirings 1
The conductivity of 2, 14 is significantly improved.

In the above embodiment, the TiN film 17A is not directly deposited on the first Al wiring 12 but is deposited via the Ti film 17. Therefore, the first Al wiring 12 and the T
It is possible to prevent the contact resistance from increasing due to the presence of N _{2 at} the interface with the iN film 17A. Furthermore, Ti is formed under the TiN film 17A.
Since the film 17 is laid, the adhesion strength between the TiN film 17A and the interlayer insulating film (SiO ₂ ) 13 is increased. Further, since the TiN film 17A is laid under the second Al wiring 14, the resistance to electromigration and thermal migration is improved. That is, from the bottom to the top, the Ti film 17, the TiN film 17A, and the second A film
It has a three-layer structure of the l wiring 12. Therefore, the TiN film 17A has the same crystallographic direction as the TiN film 17A,
The crystal orientation of the second Al wiring is aligned with A. That is, the crystal directions of all three layers are aligned. This improves resistance to electromigration and thermal migration. When a Mo layer is present on the first Al wiring 12, a horizontal hillock (Horizontal)
hillock) is not preferable, and such a two-layer structure has a drawback that etching is difficult and after-corrosion is likely to occur. .

[0023]

According to the semiconductor device of the present invention, when the first and second metal wirings are conducted through the connection hole of the interlayer insulating film, the high resistance oxide layer on the surface of the first metal wiring is formed. Since it is reduced by the highly oxidizable metal and is made conductive by the conductive metal layer generated by the reduction, the first and second metal wirings can be surely made conductive without causing damages such as ion etching to the semiconductor device. Can be made.

Further, according to the present invention, the barrier metal layer prevents the second metal wiring from reacting with the semiconductor substrate and the highly-oxidizable metal layer, so that the reliability of the second metal wiring is maintained for a long period of time. Can be maintained for extended life. Furthermore, since the barrier metal layer is formed below the second metal wiring to form a multilayer structure, the mechanical strength of the second metal wiring can be increased and the occurrence of disconnection and conduction failure can be avoided as much as possible. Therefore, the electrical characteristics of the wiring can be improved.

Further, due to the presence of the barrier metal layer,
Although the highly-oxidizable metal layer was present on the interlayer insulating film,
The second metal wiring does not directly contact the highly oxidizable metal layer but contacts the barrier metal layer. Since the adhesiveness of the second metal wiring to the barrier metal layer is good, the adhesiveness of the second metal wiring to the barrier metal layer, and further to the interlayer insulating film, can be achieved while using the highly oxidizing metal layer. The property can be significantly improved.

Further, even when the high resistance oxide layer is reduced by the high oxidation metal layer, the barrier metal layer prevents the second metal wiring from reacting with the high oxidation metal layer, and It is possible to reliably prevent disconnection of metal wiring and defective conduction.

Further, since the three-layer structure of the highly oxidizable metal layer, the barrier metal layer and the second metal wiring is adopted, the crystal directions of these three layers can be aligned and the migration resistance can be improved.

[Brief description of drawings]

FIG. 1 is a manufacturing process chart showing an embodiment of a method of manufacturing a semiconductor device as a related technique of the present invention.

FIG. 2 is a manufacturing process diagram showing an embodiment of the present invention.

FIG. 3 is a cross-sectional view of a conventional semiconductor device.

FIG. 4 is a diagram showing conduction probabilities of first and second Al wirings.

[Explanation of symbols]

 11 Semiconductor Substrate 12 First Al Wiring 13 Interlayer Insulating Film 14 Second Al Wiring 15 Connection Hole 16 Alumina Layer 17 Ti Film 17A TiN Film 18, 18A Alloy Layer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshinori Araki 72 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Stock company Toshiba Horikawa-cho factory (56) Reference JP-A-53-121490 (JP, A) JP-A-60-5560 (JP, A)

Claims (2)

[Claims] 1. A second metal wiring is formed on a first metal wiring formed on a semiconductor substrate via an interlayer insulating film, and the first and second metal wirings are opened in the interlayer insulating film. In the method for manufacturing a semiconductor device in which conduction is established through the connection hole, a highly oxidizable metal layer is formed on at least the surface of the first metal wiring and the surface of the interlayer insulating film exposed in the connection hole. And a step of preventing the second metal wiring from reacting with a material therebelow on the surface of the highly oxidizable metal layer, and reinforcing the mechanical strength of the second metal wiring. A step of forming a barrier metal layer having good adhesion to the second metal wiring, a step of forming the second metal wiring on the surface of the barrier metal layer, and a heat treatment to form the second metal wiring. The second metal wiring is a barrier machine for the barrier metal layer. The first portion exposed to the connection hole while being left as it is without reacting with other materials due to its function.
A heat treatment step of reducing the high resistance oxide layer on the surface of the metal wiring with the highly oxidizable metal layer to form a conductive metal layer. 2. The first and second metal wirings are formed of aluminum, and the highly oxidizable metal layer is formed of Ti, Hf, V, Mg, Li,
The method for manufacturing a semiconductor device according to claim 1, wherein the barrier metal layer is formed of Ni, an alloy thereof, or an alloy containing these, and the barrier metal layer is formed of TiN.