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JPH05299418A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05299418A
JPH05299418A JP9923492A JP9923492A JPH05299418A JP H05299418 A JPH05299418 A JP H05299418A JP 9923492 A JP9923492 A JP 9923492A JP 9923492 A JP9923492 A JP 9923492A JP H05299418 A JPH05299418 A JP H05299418A
Authority
JP
Japan
Prior art keywords
contact hole
semiconductor device
forming
thin film
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9923492A
Other languages
Japanese (ja)
Inventor
Tatsuya Yamada
達也 山田
Hiroshi Nishimura
宏 西村
Takehito Yoshida
岳人 吉田
Shinichi Ogawa
真一 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9923492A priority Critical patent/JPH05299418A/en
Publication of JPH05299418A publication Critical patent/JPH05299418A/en
Pending legal-status Critical Current

Links

Landscapes

  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To provide a method for the manufacture of a highly reliable semiconductor device. CONSTITUTION:A method for the manufacture of a semiconductor device composed of a process for forming a contact hole 3 in an insulating film 2 on a semiconductor substrate 1; a process for forming a high melting point conductive thin film 4 on the substrate 1 by sputter deposition; and a process for tapering the side wall of the above contact hole by argon sputtering. The wet etching process for tapering a contact hole is omitted, and thus the possibility of resist being stripped during the process; argon sputtering in a sputtering system is employed for tapering a contact hole 3 instead. This enables the formation of an aluminum wiring 7 excellent in step coverage.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は高集積度・高信頼性半導
体装置の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated and highly reliable semiconductor device.

【0002】[0002]

【従来の技術】半導体装置の高密度化にともなって、接
続孔の径に対する層間絶縁膜厚の比(アスペクト比)が
高くなり、コンタクトホールは深くなるため、スパッタ
法により堆積したアルミ配線は、コンタクトホールにお
いて段差被覆性(ステップカバレジ)が低下し、初期の
段階で断線に至る場合がある。なお、ここではAl元素
を主成分とするAl−X(X;添加不純物)合金からな
る配線を称してアルミ配線と記述する。さらに、微細化
されたアルミ配線は、アルミ配線形成後のプロセス中の
熱処理、および半導体チップ組立後の実動作時に、周囲
の層間絶縁膜およびパッシベーション膜の引っ張り応力
などによるストレスマイグレーション、電流と前記応力
とに誘発されたエレクトロマイグレーションによりアル
ミ配線の断線を引き起こすという問題があった。
2. Description of the Related Art As the density of semiconductor devices increases, the ratio of the interlayer insulating film thickness to the diameter of connection holes (aspect ratio) increases, and the contact holes become deeper. In some cases, the step coverage in the contact hole deteriorates, which may lead to disconnection in the initial stage. Note that, here, a wiring made of an Al-X (X; additive impurity) alloy containing Al element as a main component is referred to as an aluminum wiring. Furthermore, the miniaturized aluminum wiring has stress migration caused by tensile stress of the surrounding interlayer insulating film and passivation film during the heat treatment during the process after forming the aluminum wiring and during the actual operation after assembling the semiconductor chip. There is a problem that the aluminum wiring is broken due to the electromigration induced by.

【0003】従来、半導体装置における接続孔の構造を
形成する方法として、図2に示したように、半導体素子
を形成したシリコン基板1上に絶縁膜2を形成し、さら
にフォトレジストを塗布し、絶縁膜2にコンタクトホー
ルを開口後、ウェットエッチング法によりコンタクトホ
ールにテーパを付け、レジストの除去を行いテーパ化コ
ンタクトホール5を形成する。そして、バリアメタル層
としてTiN/Ti薄膜6及びAl-1%Si-0.5%Cu薄膜7の
堆積を行う方法が一般的である。
Conventionally, as a method of forming a structure of a connection hole in a semiconductor device, as shown in FIG. 2, an insulating film 2 is formed on a silicon substrate 1 on which a semiconductor element is formed, and a photoresist is further applied. After forming a contact hole in the insulating film 2, the contact hole is tapered by a wet etching method and the resist is removed to form a tapered contact hole 5. Then, the TiN / Ti thin film 6 and the Al-1% Si-0.5% Cu thin film 7 are generally deposited as the barrier metal layer.

【0004】[0004]

【発明が解決しようとする課題】しかしながら上記のテ
ーパ化コンタクトホールの形成方法においては、アルミ
配線形成工程の前に、ウェットエッチング工程が必要と
なること、およびウェットエッチング工程後に、絶縁膜
とレジストの密着性が悪いために、レジストの剥離が生
じるという問題があった。本発明は上記の問題点に鑑
み、テーパ化コンタクトホールを確実に形成し、かつ工
程簡略を計った半導体装置の製造方法を提供することを
目的とする。
However, in the above method for forming a tapered contact hole, a wet etching step is required before the aluminum wiring forming step, and the insulating film and the resist are not formed after the wet etching step. Due to the poor adhesion, there is a problem that the resist peels off. In view of the above problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device in which a tapered contact hole is surely formed and the process is simplified.

【0005】[0005]

【課題を解決するための手段】上記問題点を解決するた
めに本発明の半導体装置の製造方法は、ウェットエッチ
ング工程を必要とせず、かつスパッタ装置内でのアルゴ
ンスパッタによってテーパ化コンタクトホールを形成さ
せるものである。更に詳述すると本発明の半導体装置の
製造方法は、半導体基板上の絶縁膜に接続孔を設ける工
程と、スパッタ堆積法による基板上に高融点導電薄膜を
形成する工程と、その後アルゴンスパッタ法による接前
記続孔側壁に傾斜を形成する工程とを備え、前記半導体
基板へのダメージを抑えたことを特徴とする。
In order to solve the above problems, the method of manufacturing a semiconductor device according to the present invention does not require a wet etching process and forms a tapered contact hole by argon sputtering in a sputtering device. It is what makes them. More specifically, the method of manufacturing a semiconductor device of the present invention comprises a step of forming a connection hole in an insulating film on a semiconductor substrate, a step of forming a refractory conductive thin film on a substrate by a sputter deposition method, and then an argon sputtering method. And a step of forming a slope on the side wall of the continuous hole, so that damage to the semiconductor substrate is suppressed.

【0006】[0006]

【作用】本発明は上記した方法によって、半導体装置の
製造工程を簡略化させ、容易にコンタクトホールにテー
パを付け、アルミ配線のステップカバレジを向上させ
て、高信頼性半導体装置を製造することができる。
According to the present invention, the manufacturing method of a semiconductor device can be simplified by the method described above, the contact hole can be easily tapered, and the step coverage of aluminum wiring can be improved to manufacture a highly reliable semiconductor device. it can.

【0007】[0007]

【実施例】本発明の実施例を図面を参照しながら説明す
る。
Embodiments of the present invention will be described with reference to the drawings.

【0008】図1は本発明の一実施例における半導体装
置の製造工程断面図を示すものである。図1aでは、半
導体素子を形成したシリコン基板1上に厚さ800nm
の絶縁膜2を形成し、その絶縁膜2にコンタクトホール
3を開口した後、高融点導電薄膜として80nmTi薄
膜4を堆積する。
FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. In FIG. 1a, a silicon substrate 1 on which a semiconductor element is formed has a thickness of 800 nm.
The insulating film 2 is formed, a contact hole 3 is opened in the insulating film 2, and then a 80 nm Ti thin film 4 is deposited as a high melting point conductive thin film.

【0009】続いて図1bでは、スパッタ装置におい
て、真空度10mTorr、電力360Wの条件でウエハ全
面アルゴンスパッタ(逆スパッタ)を行い、コンタクト
ホール3の角がエッチングされテーパ化コンタクトホー
ル5が形成できる。その際、ホール底部にはTi薄膜4
が部分的に残り、シリコン基板1へのダメージを防ぐこ
とができる。
Subsequently, in FIG. 1B, in the sputtering apparatus, the entire surface of the wafer is subjected to argon sputtering (reverse sputtering) under the conditions of a vacuum degree of 10 mTorr and a power of 360 W, and the corners of the contact holes 3 are etched to form tapered contact holes 5. At that time, a Ti thin film 4 was formed on the bottom of the hole.
Are partially left, and damage to the silicon substrate 1 can be prevented.

【0010】次に図1cでは、逆スパッタされたTi薄
膜4上にバリアメタル層として100/20nmのTi
N/Ti薄膜6を堆積させる。ホール底には図1bの段
階でTi薄膜が残るために、TiN/Ti薄膜6は底部
で厚く、テーパ化により側壁でも厚く形成され、バリア
性の向上を計ることができる。以上、Ti堆積(図1
a)からTiN/Ti堆積(図1c)までの工程は、連
続してスパッタ装置内で行う。
Next, in FIG. 1c, 100/20 nm Ti is used as a barrier metal layer on the reverse-sputtered Ti thin film 4.
The N / Ti thin film 6 is deposited. Since the Ti thin film remains at the bottom of the hole at the stage of FIG. 1b, the TiN / Ti thin film 6 is thick at the bottom and also thick at the side wall due to the taper, so that the barrier property can be improved. Above, Ti deposition (Fig. 1
The steps from a) to TiN / Ti deposition (FIG. 1c) are continuously performed in the sputtering apparatus.

【0011】次に図1dでは、バリア性を確保するため
にウエハを一旦大気暴露させ、その後再びスパッタ装置
で800nmAl-1%Si-0.5%Cu薄膜7の堆積を行う。テー
パを形成してあるため、アルミ薄膜のステップカバレジ
は良好に保つことができる。
Next, in FIG. 1d, the wafer is once exposed to the atmosphere to secure the barrier property, and then the 800 nm Al-1% Si-0.5% Cu thin film 7 is deposited again by the sputtering apparatus. Since the taper is formed, good step coverage of the aluminum thin film can be maintained.

【0012】以上のように本実施例では、バリアメタル
層TiN/Ti薄膜6堆積前にTi薄膜4を堆積し、続
いて逆スパッタを行い、コンタクトホール3をテーパ化
させるため、シリコン基板1へのダメージを抑えること
ができる。
As described above, in this embodiment, the Ti thin film 4 is deposited before the barrier metal layer TiN / Ti thin film 6 is deposited, and then the reverse sputtering is performed to taper the contact hole 3. The damage of can be suppressed.

【0013】なお、本実施例でのテーパ化のためのアル
ゴンスパッタ条件は、スパッタ装置の形状等により異な
るので、真空度1〜500mTorr、電力10〜600W
で最適化を行うことにより実施が可能である。
Since the argon sputtering conditions for taper in this embodiment differ depending on the shape of the sputtering apparatus and the like, the degree of vacuum is 1 to 500 mTorr and the power is 10 to 600 W.
This can be done by optimizing with.

【0014】[0014]

【発明の効果】以上のように本発明は、テーパ化接続孔
形成のためのウェットエッチング工程を必要とせず、そ
の工程でのレジスト剥離の可能性を無くし、接続孔の側
壁をテーパ化させて、アルミ配線のステップカバレジを
良好にさせることで、エレクトロマイグレーション、ス
トレスマイグレーション耐性の強いアルミ配線を形成す
ることを可能にするものであり、超微細な半導体装置の
製造に大きく寄与するものである。
As described above, the present invention eliminates the need for a wet etching step for forming a tapered contact hole, eliminates the possibility of resist stripping in that step, and makes the sidewall of the contact hole tapered. By improving the step coverage of the aluminum wiring, it is possible to form an aluminum wiring having a strong resistance to electromigration and stress migration, which greatly contributes to the manufacture of ultrafine semiconductor devices.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における半導体装置の製造工
程断面図
FIG. 1 is a sectional view of a semiconductor device manufacturing process according to an embodiment of the present invention.

【図2】従来の方法による半導体装置の断面図FIG. 2 is a sectional view of a semiconductor device according to a conventional method.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 絶縁膜 3 コンタクトホール 4 Ti薄膜 5 テーパ化コンタクトホール 6 TiN/Ti薄膜 7 Al-1%Si-0.5%Cu薄膜 1 Silicon substrate 2 Insulating film 3 Contact hole 4 Ti thin film 5 Tapered contact hole 6 TiN / Ti thin film 7 Al-1% Si-0.5% Cu thin film

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/90 C 7735−4M (72)発明者 小川 真一 大阪府門真市大字門真1006番地 松下電器 産業株式会社内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification number Internal reference number FI Technical indication H01L 21/90 C 7735-4M (72) Inventor Shinichi Ogawa 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. Sangyo Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上の絶縁膜に接続孔を設ける工
程と、スパッタ堆積法による基板上に高融点導電薄膜を
形成する工程と、その後アルゴンスパッタ法による接前
記続孔側壁に傾斜を形成する工程とを備え、前記半導体
基板へのダメージを抑えたことを特徴とする半導体装置
の製造方法。
1. A step of forming a connection hole in an insulating film on a semiconductor substrate, a step of forming a high-melting-point conductive thin film on a substrate by a sputter deposition method, and then forming a slope on the side wall of the contact hole by an argon sputtering method. The method of manufacturing a semiconductor device, comprising:
JP9923492A 1992-04-20 1992-04-20 Manufacture of semiconductor device Pending JPH05299418A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9923492A JPH05299418A (en) 1992-04-20 1992-04-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9923492A JPH05299418A (en) 1992-04-20 1992-04-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05299418A true JPH05299418A (en) 1993-11-12

Family

ID=14241995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9923492A Pending JPH05299418A (en) 1992-04-20 1992-04-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05299418A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6476496B1 (en) 1999-06-28 2002-11-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
JP2005252160A (en) * 2004-03-08 2005-09-15 Ricoh Co Ltd Semiconductor device
JP2005277251A (en) * 2004-03-26 2005-10-06 Ricoh Co Ltd Semiconductor device
JP2017140717A (en) * 2016-02-08 2017-08-17 キヤノン株式会社 Liquid discharge head substrate, liquid discharge head, liquid discharge device, manufacturing method of the liquid discharge head substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6476496B1 (en) 1999-06-28 2002-11-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
JP2005252160A (en) * 2004-03-08 2005-09-15 Ricoh Co Ltd Semiconductor device
JP2005277251A (en) * 2004-03-26 2005-10-06 Ricoh Co Ltd Semiconductor device
JP2017140717A (en) * 2016-02-08 2017-08-17 キヤノン株式会社 Liquid discharge head substrate, liquid discharge head, liquid discharge device, manufacturing method of the liquid discharge head substrate

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