JPH0736704A - Program down-loading system - Google Patents

Abstract

PURPOSE:To promptly down-load programs from a master processor to the local nonvolatile memory of a slave processor. CONSTITUTION:When a power source is applied, a reset circuit 23 turns a microprocessor 21 to a standstill state and a bus interface 24 makes access from the master processor 1 to a volatile memory 22 possible. The master processor 1 loads the programs from an external device 4 through an external interface 15 to a reloadable nonvolatile memory 13 by executing the programs stored in the nonvolatile memory 12, copies the ones for the present processor 1 among them to the volatile memory 14, writes the ones for the slave processor 2 through the bus interfaces 16 and 24, a system bus 3 and a CPU bus 25 to the volatile memory 22 and releases the reset circuit 23. Thus, the standstill state is cancelled and the microprocessor 21 starts the execution of the programs stored in the volatile memory 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program download system in a multiprocessor system.

[0002]

2. Description of the Related Art When a program to be executed by a processor is stored in a non-volatile memory such as a ROM, it is difficult to change the program, and the non-volatile memory is generally a RAM.
Since it is more expensive than a volatile memory such as, the system price is increased.

Therefore, in a multiprocessor system including a plurality of processors, a processor other than a specific one processor (referred to as a master processor in this specification) called a master processor, a host processor, etc. (referred to as a master processor in this specification) It is known that only a volatile memory is provided in the slave processor), and a necessary program is downloaded from the master processor to the volatile memory of the slave processor. The following methods have been conventionally proposed as such a program download method.

(1) The slave processor is provided with a volatile shared memory that is also accessible by the master processor, and a reset holding circuit for holding a reset signal from the master processor to the own processor is provided. A method in which a program to be downloaded is written in the shared memory in a state where the slave processor is stopped by the circuit and then the reset by the reset holding circuit is released, and the slave processor executes the program written in the shared memory (for example, Japanese Laid-Open Patent Publication 1-246652).

(2) A volatile memory for storing data and programs in a slave processor, a volatile shared memory accessible from the master processor, and an address conversion circuit for performing address conversion of an arbitrary area of this shared memory. And a reset holding circuit for holding a reset signal from the master processor to the own processor. When the master processor stops the slave processor by the reset holding circuit, the slave processor I
The PL is transferred to the shared memory, the address of the transfer area is converted by the address conversion circuit so as to be after the start address after the slave processor (after the restart address), and then the reset state is released. A method in which the slave processor executes the IPL on the shared memory at the timing, and the download program is loaded from the memory of the master processor to the non-volatile memory of the own processor via the shared memory and executed (for example, JP-A-63-63). -184155).

[0006]

However, the above-mentioned conventional program download method has the following problems.

In the conventional system (1), since the download program to be executed by the slave processor is stored in the shared memory, the nature of the shared memory causes
While another processor is accessing the shared memory, the slave processor cannot access the shared memory, thus stopping the execution of the program and degrading the performance of the local processing by executing the download program.

On the other hand, the conventional method (2) does not have the problem of the conventional method (1) because the download program is finally stored in the local non-volatile memory in the slave processor. Forwards the IPL for the processor, then the slave processor
Since the PL is executed to read the download program into the shared memory and further stores it in the local non-volatile memory, there is a problem that it takes a long time to complete the download.

The present invention solves such a conventional problem, and an object thereof is to provide a program download system capable of promptly downloading a program from a master processor to a local non-volatile memory of a slave processor. Especially.

[0010]

In order to achieve the above-mentioned object, a program download system of the present invention comprises a master processor and a slave processor connected to the master processor via a system bus. In the slave processor,
A first bus that is a CPU bus; a first microprocessor connected to the first bus; and a reset circuit that stops the first microprocessor until a request is made from the master processor after power is turned on. A volatile local memory connected to the first bus;
And a first bus interface connected to the bus of the master processor to enable the master processor to access the local memory while the first microprocessor is stopped. A program to be downloaded to the processor is written to the local memory through the system bus, the first bus interface and the first bus, and then a reset release request is issued to the reset circuit.

The master processor has a second bus, which is a CPU bus, and a second bus connected to the second bus.
And a microprocessor connected to the second bus,
Connected to a first non-volatile memory storing a program to be executed first when the power is turned on and the second bus;
A rewritable non-volatile memory in which a program for each microprocessor is stored and a second bus interface connected to the second bus and the system bus are provided, and the master is turned on when the master processor is powered on. The second microprocessor of the processor executes the program stored in the first non-volatile memory to download the download program stored in the rewritable non-volatile memory to the second bus interface,
After writing to the local memory through the system bus, the first bus interface, and the first bus, a reset release request is issued to the reset circuit.

Further, the second processor is provided in the master processor.
A second volatile memory connected to the bus for storing data or a program, and connected to the second bus;
An external interface for downloading a program to the rewritable non-volatile memory, and when the master processor is powered on, the second microprocessor of the master processor stores the program stored in the first non-volatile memory. By executing, by downloading the program from the external device to the rewritable non-volatile memory by the external interface, while writing the program for its own processor from the rewritable non-volatile memory to the second volatile memory, After writing the download program for the slave processor from the rewritable non-volatile memory to the local memory through the second bus interface, the system bus, the first bus interface and the first bus, the reset program is executed. It makes a request for reset release the circuit, after that, so as to execute a program stored in the second volatile memory.

The second microprocessor is
When the external device is not connected to the external interface, the download process from the external device to the rewritable nonvolatile memory is skipped.

[0014]

When the power of the master processor and the slave processor is turned on, on the slave processor side, the reset circuit keeps the microprocessor in its own processor stopped until the master processor makes a request, and the first bus interface Enables the master processor to access the local memory in its own processor.
The program stored in the non-volatile memory of is executed.

By executing this program, it is first checked whether or not an external device is connected to the external interface, and if it is connected, the external device is used for the master processor and the slave processor through the external interface. The program is loaded into the rewritable nonvolatile memory. If not connected, this process is skipped. Next, the program for the master processor is written from the rewritable nonvolatile memory to the second volatile memory, and the download program for the slave processor is written from the rewritable nonvolatile memory to the second bus interface, system bus, slave processor. Write to the local memory of the slave processor through the first bus interface and the first bus, and then request the reset release to the reset circuit, and then execute the program stored in the second volatile memory. To do.

When a reset cancellation request is issued, on the slave processor side, the reset circuit cancels the stopped state of the microprocessor in the self processor. This causes the microprocessor to start executing the program downloaded to local memory.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Referring to FIG. 1, an example of a multiprocessor system to which the present invention is applied is composed of a master processor 1 and a slave processor 2 connected to the master processor 1 by a system bus 3. Although the number of slave processors 2 is one in this example, the present invention is also applicable to a system in which a plurality of slave processors are connected to the master processor 1 via the system bus 3.

The master processor 1 includes a microprocessor 11, a nonvolatile memory 12 such as a ROM, a rewritable nonvolatile memory 13 such as a flash EEPROM, and R.
A volatile memory 14 such as AM and an external interface 15
, The bus interface 16 and the CP connecting them
The bus interface 16 is connected to the system bus 3, and the external interface 15 is connected to the download device 4 such as a hard disk device or a floppy disk device.

The slave processor 2 includes a microprocessor 21, a volatile memory 22 such as a RAM, a bus interface 24, and a CPU bus 25 connecting them.
And a reset circuit 23, the bus interface 2
4 is connected to the system bus 3.

The operation of the program download system of this embodiment will be described below.

When the power is turned on, the reset circuit 23 of the slave processor 2 keeps outputting the reset signal to the microprocessor 21 until it receives a reset release request from the master processor 1 through the bus interface 24. Is stopped, and at the same time, the bus interface 24 is notified that the microprocessor 21 is stopped.

Upon receiving this notification, the bus interface 24 makes the volatile memory 22 directly accessible to the master processor 1 through the system bus 3 and the CPU bus 25.

On the other hand, when the power is turned on, the microprocessor 11 of the master processor 1 starts execution of the program by accessing the restart address.
This restart address is the start address of the program stored in advance in the non-volatile memory 12, whereby the program stored in the non-volatile memory 12 is executed by the microprocessor 11 when the power is turned on.
The following processing is performed.

First, the microprocessor 11 confirms whether or not the download device 4 is connected to the external interface 15. When connected, the program is downloaded from the download device 4 to the rewritable nonvolatile memory 13 through the external interface 15. As a result, the program for the master processor 1 and the program for the slave processor 2 can be externally downloaded to the multiprocessor system. If the download device 4 is not connected, such a download process is skipped.

Next, the microprocessor 11 stores the program stored in the rewritable non-volatile memory 13 (the program that was downloaded when the download process was performed, and originally stored when the download process was skipped). The program for its own processor in the program) is copied to the volatile memory 14, and the program for the slave processor 2 is bus interface 16, system bus 3, bus interface 24, CPU bus 2
5 is copied, that is, downloaded to the volatile memory 22 of the slave processor 2 via 5. Then, it issues a reset release request to the slave processor 2 through the bus interface 16 and the system bus 3, and itself starts executing the program stored in the volatile memory 14.

A reset release request from the master processor 1 is sent to the reset circuit 2 via the bus interface 24.
3, the reset circuit 23 releases the stopped state of the microprocessor 21 when triggered by this. As a result, the microprocessor 21 accesses the restart address and starts executing the program. This restart address is the start address of the program downloaded to the volatile memory 22, and thus the microprocessor 21 starts executing the downloaded program.

Next, referring to FIG. 2, a configuration example of the bus interface 24 and the master processor 1 will be described as the volatile memory 2.
A more detailed operation when accessing 2 will be described.

The bus interface 24 shown in FIG. 2 is composed of buffers 241, 242, 243 and an AND circuit 244. Further, the CPU bus 25 is A0-A1.
9 address bits, read / write signals R / W, D0
-D7 is a bus for transmitting data bits, and address bits A0-A output from the microprocessor 21
Address bits A16-A19 of 19 are for decoder 2
6 and the address bits A0-A15 are input to the volatile memory 22. The decoder 26 chip-selects the volatile memory 22 when all the address bits A16-A19 are "1".

When buffer 241 is enabled by the output of AND circuit 244, address bits A16-A1 on CPU bus 25 of microprocessor 21 are provided.
Forcibly fix 9 to "1".

The buffer 242, when enabled by the output of the AND circuit 244, sends the read / write signal R / W and address bits A0-A15 sent from the master processor 1 through the system bus 3 to the CPU.
Transfer to bus 25.

When the buffer 243 is enabled by the output of the AND circuit 244, the data bit on the system bus 3 is transferred in the transfer direction according to the read / write signal R / W sent from the master processor 1 through the system bus 3. It buffers D0-D7 and the data bits D0-D7 on the CPU bus 25.

The AND circuit 244 receives the reset signal Reset from the reset circuit 23 and the download request D sent from the master processor 1 through the system bus 3.
The ownLoad and the address strobe signal AS are input, and the logical product signal is input to the buffers 241-243.
The gate is used as the enable signal of. The download request DownLoad is applied to the reset circuit 23, and the reset circuit 23 downloads the download request DowLoad.
It is recognized that there is a reset release request when nLoad falls.

As described above, the reset circuit 23 sends the reset signal Reset to the microprocessor 21 when the power is turned on.
While in the stop state due to t, reset signal Rese
t is "1". In this state, the master processor 1 sends a download request Dow through the system bus 3.
nLoad and address strobe signal AS “1”
Then, the output of the AND circuit 244 becomes "1" and the buffers 241 to 243 are enabled. As a result, the CPU bus 25 of the slave processor 2 is connected to the system bus 3, and although not shown in FIG.
It is connected to the CPU bus 17 of the master processor 1 through the bus interface 16 of FIG. At this time, the CPU
A16-A19 of the address bits of the bus 25 are forcibly fixed to "1" by the buffer 241. Therefore, the master processor 1 sends the address A to the system bus 3.
By sending 0-A15, the area of addresses F0000 to FFFFF of the volatile memory 22 can be accessed, and the download program can be written in the program area of the volatile memory 22 which is the local memory of the microprocessor 21. it can.

Then, the master processor 1 finishes downloading the program, and download request Down
When Load is set to “0”, the output of the AND circuit 244 becomes “0”, the buffers 241 to 243 are turned off, and the reset circuit 23 resets the reset signal Reset.
Is set to “0”. As a result, the microprocessor 21
Starts its operation and starts execution from the instruction at the restart address on the volatile memory 22.

When the master processor 1 and the slave processor 2 exchange data with each other, the data is transmitted through the system bus 3. As a method therefor, a method through a shared memory not shown in FIG. An arbitrary method such as a transmission method is adopted.

[0037]

As described above, according to the present invention, the following effects can be obtained.

The slave processor is provided with a bus interface that enables the master processor to access the local memory while the microprocessor is stopped, and the master processor writes the download program directly to the slave processor's local memory. Since this is done, the program download processing time to the slave processor is shortened compared to the conventional method (2), and the slave processor can start executing the program promptly. Of course, since the download program is stored in the local memory, there is no problem as in the conventional method (1) of storing the download program in the shared memory.

When changing the program for the master processor and the program for the slave processor, the rewritable non-volatile memory in the master processor may be rewritten, and the rewriting is also connected to the external device for downloading to the external interface of the master processor. It can be easily implemented. Since this external device does not need to be normally used, the device configuration can be simplified.

Since the program read from the external device is stored in the rewritable nonvolatile memory,
Unless the program is changed, you only have to download it from the external device once.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a multiprocessor system to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration example of a bus interface 24.

[Explanation of symbols]

 1 ... Master processor 11 ... Microprocessor 12 ... Nonvolatile memory 13 ... Rewritable nonvolatile memory 14 ... Volatile memory 15 ... External interface 16 ... Bus interface 17 ... CPU bus 2 ... Slave processor 21 ... Microprocessor 22 ... Volatile Memory 23 ... Reset circuit 24 ... Bus interface 241-243 ... Buffer 244 ... AND circuit 25 ... CPU bus 26 ... Decoder 3 ... System bus 4 ... Download device

Claims (4)

[Claims] 1. A multi-processor system including a master processor and a slave processor connected to the master processor via a system bus, wherein the slave processor includes a first bus that is a CPU bus, and the first processor. A first microprocessor connected to the bus, a reset circuit for stopping the first microprocessor after power-on until a request from the master processor, and a volatile memory connected to the first bus. A local memory and a first bus interface connected to the first bus that enables the master processor to access the local memory while the first microprocessor is halted; The master processor is the program to be downloaded to the slave processor. Said system bus, a program download method characterized by having a configuration in which a request for reset release to the reset circuit after writing to the local memory via the first bus interface and said first bus. 2. The master processor includes a second bus which is a CPU bus, a second microprocessor connected to the second bus, and a second bus which is connected to the second bus and is first connected to the master bus when power is turned on. A first non-volatile memory storing a program to be executed, a rewritable non-volatile memory connected to the second bus and storing a program for each microprocessor, the second bus and the system A second bus interface connected to a bus, wherein the second microprocessor of the master processor executes a program stored in the first non-volatile memory when the master processor is powered on. The download program stored in the rewritable non-volatile memory according to the second bus interface, the system bus, 2. The program download method according to claim 1, wherein a reset release request is issued to the reset circuit after writing to the local memory through the first bus interface and the first bus. 3. The master processor includes a second volatile memory connected to the second bus and storing data or a program; and a second volatile memory connected to the second bus to the rewritable nonvolatile memory. An external interface for downloading a program, wherein when the master processor is powered on, the second microprocessor of the master processor executes the program stored in the first non-volatile memory, After downloading the program from the external device to the rewritable non-volatile memory by an interface, the program for the own processor is written from the rewritable non-volatile memory to the second volatile memory and from the rewritable non-volatile memory. In front of the download program for the slave processor After writing to the local memory through the second bus interface, the system bus, the first bus interface, and the first bus, a reset release request is issued to the reset circuit, and then the 3. The program download method according to claim 2, wherein the program stored in the volatile memory 2 is executed. 4. The second microprocessor skips download processing from the external device to the rewritable nonvolatile memory when the external device is not connected to the external interface. The program download method according to claim 3.