JP2581753B2 - Self-diagnosis method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention uses a buffer memory provided in each sub-control device for work and for bidirectional data relay transfer with a main control device. In addition, the present invention relates to a self-diagnosis method in which a sub-control device is used for storing a diagnostic program so that a sub-control device performs a self-diagnosis.

[Conventional technology]

A conventional program diagnosis method is disclosed in
As described in Japanese Patent Publication No. 229339, the microprogram storage control memory in the device to be diagnosed or the sub-control device (hereinafter referred to as a subordinate device) is configured as a RAM.
The diagnostic program is transferred and stored by the main control device and executed by the subordinate device. On the other hand, apart from the above, "Method design of computer" (Tanpo, 19
On pages 227 to 229 of July 1, 1972), the normal processing is ROM
The diagnostic processing is performed by the microprogram stored in
This shows that the diagnosis is performed by a diagnostic program stored in the RAM.

[Problems to be solved by the invention]

However, in the case of the former as the prior art,
Apart from the fact that the diagnostic program needs to be loaded into the RAM each time the diagnostic processing is performed, the normal processing microprogram must be loaded into the RAM every time the diagnostic processing returns to the normal processing as well as when the power is turned on. There is.
Therefore, there is a problem that the start-up of the apparatus is delayed by the time required for the loading. In the latter case, a dedicated RAM for storing a diagnostic program is required, and self-diagnosis of the apparatus cannot be performed economically.

SUMMARY OF THE INVENTION An object of the present invention is to provide a self-diagnosis method in a subordinate device in which a dedicated RAM for storing a diagnostic program is not required and loading of a normal processing microprogram is not required.

[Means for solving the problem]

The above object is achieved by a processor executing a microprogram stored in a ROM, which is accommodated in parallel in a main control device as an upper-level device via an external bus, and performs normal processing with the main control device. The bidirectional data transfer is a self-diagnosis method in each of the subordinate devices, which is performed through a buffer memory as a two-port RAM that also serves as a work RAM at the same time. When each slave device performs a self-diagnosis, the processor in the slave device is temporarily stopped by the main controller, and the slave device is set to the address translation mode so that the access address to the ROM from the processor becomes the access address to the buffer memory. In the set state, after the diagnostic program is DMA-transferred and stored in the buffer memory in the slave device from the master controller, When the processor in the slave device is released from the temporary halt state by the controller, the processor is started, and each access address from the processor to the ROM is converted into each access address to the buffer memory. In the state
By executing the diagnostic program in the buffer memory by the processor, the slave device is self-diagnosed, and the self-diagnosis result is achieved by being read by the main controller via the buffer memory.

[Action]

Under the control of the microprogram stored in the ROM, the slave device performs a normal process as an original function while using a buffer memory as a work RAM. By the way, when it is necessary to confirm whether or not the processing operation in the slave device is normal, the self-diagnosis is performed by the slave device. Once stopped, a diagnostic program is transferred and stored in the buffer memory from the main controller. After that, if the slave device is started in a state where it is set in advance to convert the address in the ROM to the address in the buffer memory, eventually the RO
When the buffer memory is accessed instead of M, the diagnostic program is executed, that is, the self-diagnosis processing is performed. When returning from the self-diagnosis processing to the normal processing, the slave device is restarted in a state where the address conversion setting is canceled by the initial setting.

〔Example〕

 Hereinafter, the present invention will be described with reference to FIGS.

First, a control processing system according to the present invention will be described. FIG. 1 shows a system outline in one example. If due to this, a plurality of slave devices 2 ₁ to 2 _n has a parallel housed configuration via the external bus 3, a main control unit 1. The slave device 2 ₁ to 2 _n each processing function connection control and the other data processing apparatus, the line connection control of a remote terminal, such as performing specific data processing, various things can be considered, in this example Line connection control is assumed.

As shown in the figure, in the main controller 1, the main processor 11 is a ROM.
As a result of activating the DMA control unit 14 under the control of the bootstrap stored in the main control memory 12 in advance, the program required for data processing from the external memory 15 via the internal bus 16 is used as a RAM in the DMA mode. Is transferred and stored in the main memory 13. Thereafter, data processing is executed by programs stored in the main control memory 12 and the main memory 13.

On the other hand, the expansion device 2 ₁ to 2 _n each operation the main control unit 1
The bidirectional data transfer with the main controller 1 is performed via a buffer memory (for example, a two-port RAM) 21 as a RAM. In normal data processing, data from main controller 1 is temporarily written to buffer memory 21 via external bus 3. The data is read from the buffer memory 21 and processed by the processor 22 operating according to a program stored in the control memory 23 as a ROM in advance, and the processing result is sent from the line control unit 24 via the internal bus 25. It is sent to the outside. On the other hand, after data from the outside is received by the line control unit 24, the data is temporarily written to the buffer memory 21 via the internal bus 25 under the control of the processor 22.
The data written in the buffer memory 21 is thereafter read by the main controller 1 via the external bus 3, and once written in the main memory 13, is subjected to data processing.

Above, the main controller 1 has been described normal processing outline of the dependent device 2 ₁ to 2 _n, respectively, the main controller 1 and the expansion device
Performing the data transfer between each of the 2 _{1 to} 2 _n via the buffer memory 21 is advantageous from various aspects. The memory addresses allocated to the buffer memory 21 are stored in the internal memory (main memory 13 and control memory 23) of each of the devices.
The buffer memory 21 can be treated in the same manner as the internal memory on the program by simplifying the program processing. Also, buffer memory 2
1.If the data transfer between the main memories 13 is performed in the DMA transfer mode under the control of the DMA control unit 14, the data transfer will be executed collectively independently of the operation of the main processor 11, and the It is advantageous.

By the way, as a processor, 8 bits or 16 bits
Bit microprocessor (for example, Motorola 68
00 and 68000) are often used for simplification of the device configuration. When the microprocessor is turned on at the time of power-on or manual initialization, the program running start memory address is the address 0 where all bits are "0" or the FF where all bits are "1". Address F (FF ... F is displayed in hexadecimal) is set. That is, the control memory
In the memory area of memory addresses 0 to N (FF... F) or memory addresses M (<FF... F) to FF. It is.

FIG. 3 shows the buffer memory 21 and the control memory 23.
3 shows an example of a memory address allocation state in the example of FIG. As shown in the figure, during normal data processing, the buffer memory 21 is accessed by the main controller 1 in the range of memory addresses 10000 to 107 FFF in hexadecimal, but in the slave device, the memory addresses 0000 to 7FFF are stored. It is to be accessed within range. Also control memory
No. 23 is accessed only from within the slave device within the range of memory addresses 8000 to FFFF. Therefore,
When a slave device is diagnosed, the main controller 1 is stored in the buffer memory 21.
In order to execute the diagnostic program transferred and stored by the processor 22, the memory addresses 8000 to FFFF for accessing the control memory 23 are changed to the memory addresses 0000 to FFFF.
It is only necessary to convert the address to 7FFF. Of 16-bit data constituting Fortunately memory address in this example, the most significant bit, i.e., so that it Seshimere inverting the bits having the weights of 2 ^15. The selector 26 is provided in the slave device for inversion control of the bit.

Here, how the self-diagnosis of the slave device is performed will be described in more detail as follows.

That is, showing a specific configuration of the selector 26 together with its peripheral circuits in FIG. 2, in the case of this, the expansion device 2 ₁ to 2 _n
When any of the above is self-diagnosed, the main controller 1 controls the selector 26 in the slave device via the external bus 3. Selector 26 as shown
Inside is a flip-flop 26 for processor halt control
Flip-flop 265 for 4 and most significant bit inversion control
Is provided. First, the flip-flop 264 is set via the decoder 261 by a control signal from the main controller 1. As a result, the halt signal 27 as the Q output keeps the processor 22 in a hold state, and the operation of the slave device is stopped. In this state, the flip-flop 265 is then set via the decoder 261, so that the most significant bit signal 28 of the address bus 252 constituting the internal bus 25 together with the data bus 251 is output by the disjunction OR gate 266. It is the one that will be inverted. After all, the memory addresses 8000 to FFFF on the address bus 252 are stored in the memory address 0 while the flip-flop 265 is in the set state.
After being converted to 000 to 7FFF and given to the buffer memory 21 and the control memory 23, the address bus 252
Buffer memory by upper memory address 8000 to FFFF
Access to the control memory 23 is disabled, but access to the control memory 23 is disabled. Thereafter, the main controller 1 transfers the diagnostic program from the main memory 13 to the buffer memory 21 via the external bus 3 in the DMA transfer mode. When the transfer and storage are completed, the flip-flop 264 is reset via the decoder 261 to release the halt state in the processor 22.
Is to execute the diagnostic operation while sequentially reading the diagnostic program from the memory address 7FFF of the buffer memory 21. The diagnosis result is temporarily stored in the buffer memory 21 and later read out to the main controller 1.

Although the state of the flip-flop 265 is controlled by the main controller 1 in the above description, the state may be controlled by the manual switch 267 in some cases. Inverter 268,269 and OR gate 2
62 and 263 are for enabling control by the manual switch 267. Further, in the above example, the address conversion is represented only by inversion of the most significant bit signal of the address bus signal. The address conversion is performed by calculating the bus signal. In addition, the control memory 23
In the case of using a RAM, loading is required only when power is turned on. Therefore, the RAM may be used in some cases.

〔The invention's effect〕

As described above, according to the present invention, the dedicated RAM for storing the diagnostic program is not required, and the reloading of the normal processing microprogram at the end of the diagnosis is not required. is there.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system outline of an example of a control processing system according to the present invention, FIG. 2 is a diagram showing a specific configuration of a selector as a main part thereof together with its peripheral circuits, and FIG. FIG. 10 is a diagram showing an example of allocation of memory addresses to a buffer memory and a control memory in a slave device. 1 ...... Main controller, 2 ₁ to 2 _n ...... slave device, 3 ...... external bus, 21 ...... buffer memory, 22 ...... processor, 23 ......
Control memory, 26 ... selector.

Claims (1)

(57) [Claims] 1. A main controller as a host device is accommodated in parallel via an external bus, and normal processing is performed by a processor executing a microprogram stored in a ROM. The bidirectional data transfer between the slave devices is a self-diagnosis method in each of the slave devices, which is performed through a buffer memory as a two-port RAM that also serves as a work RAM at the same time. When each slave device performs a self-diagnosis, the processor in the slave device is temporarily stopped by the main controller, and the slave device is set to the address translation mode so that the access address to the ROM from the processor becomes the access address to the buffer memory. In the set state, the diagnostic program is stored in the buffer memory in the slave device from the master control device.
After the DMA transfer and the storage, the main controller releases the temporary suspension of the processor in the slave device and starts the processor, so that each access address from the processor to the ROM is transferred to the buffer memory. The slave device is self-diagnosed by the execution of the buffer memory-like diagnostic program by the processor in a state converted to the respective access addresses, and the self-diagnosis result is read by the main controller via the buffer memory. Self-diagnosis method to be performed.