JPH07321213A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit device, which has excellent element isolating property, by improving short channel effect, and a manufacture art which can easily manufacture it. CONSTITUTION:This has MOSFETs which use a plurality of island-shaped Si-Ge mixed crystal layers 4 and 5 provided on a substrate 1 as several channel regions. Moreover, manufacture process comprises a step of forming a plurality of island-shaped Si-Ge mixed crystal Si-Ge mixed crystal layers 4 and 5 at one part on the germanium layer 2 made on the substrate 1, a step of forming MOSFETs which use the Si-Ge mixed crystal layers 4 and 5 as several channel regions, and a step of forming an insulating film 7 for element isolation on the germanium layer 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a MOS having excellent high speed.
The present invention relates to a technique effectively applied to a (Metal Oxide Semiconductor) type semiconductor integrated circuit device.

[0002]

2. Description of the Related Art MOS type semiconductor integrated circuit devices are
Since the FET is the main element, it is possible to obtain a semiconductor integrated circuit device which can be easily highly integrated and consumes less power.

In the MOS type semiconductor integrated circuit device, as a structure having high speed, Si having a channel region in which a silicon region and a germanium region are combined is used.
Some have adopted the Ge channel.

[0004]

However, the present inventor has found that there are various problems in adopting the Si-Ge channel in the channel region.

(1) Since the Si-Ge channel has a silicon layer and a germanium layer separately superposed on each other, a short channel effect, that is, a threshold voltage (Vth) and a lowering (lowering). )
However, it is determined only by the silicon layer or the germanium layer, and there is a problem that the optimization for preventing the short channel effect cannot be performed.

Regarding element isolation, since the oxide film on the germanium layer is unstable, the reliability becomes poor, and LOCOS (Local Oxidation) used for manufacturing a semiconductor integrated circuit device mainly containing silicon is used. of Silic
There is a problem that it cannot be used because it is unsuitable for element isolation by a field insulating film of on) structure.

(2) Therefore, Si-Ge is formed on the oxide film.
In some cases, the method of forming islands is used. However, in this method, in the portion where the Si-Ge layer and the field insulating film are in contact with each other, the interface charge is large because the plane orientation is different, and a leak current flows between the source and the drain through the interface charge, resulting in power consumption. There is a problem that is increased.

An object of the present invention is to provide a semiconductor integrated circuit device having an excellent short channel suppressing effect.

Another object of the present invention is to provide a semiconductor integrated circuit device having excellent element isolation characteristics.

Another object of the present invention is to provide a manufacturing technique capable of easily manufacturing a semiconductor integrated circuit device having an excellent short channel suppressing effect.

Another object of the present invention is to provide a manufacturing technique capable of easily manufacturing a semiconductor integrated circuit device having excellent element isolation characteristics.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

The typical ones of the inventions disclosed in the present invention will be outlined below.

A semiconductor integrated circuit device according to the present invention is a MOSF having a plurality of island-shaped Si-Ge mixed crystal layers provided on a substrate and the Si-Ge mixed crystal layers as channel regions.
With ET.

In the method for manufacturing a semiconductor integrated circuit device of the present invention, a step of forming a plurality of island-shaped Si-Ge mixed crystal layers on a part of a germanium layer formed on a substrate, and the Si -MOSFET using a Ge mixed crystal layer as a channel region
And a step of forming an element isolation insulating film on the germanium layer.

[0016]

According to the above-described semiconductor integrated circuit device of the present invention, a plurality of island-shaped Si-Ge provided on the substrate.
By using the MOSFET having the mixed crystal layer as the channel region, the shape of the depletion layer that can be controlled by the gate electrode in the channel region can be improved, so that the short channel effect can be improved. Further, since a stable element isolation insulating film such as a silicon oxide film can be provided on the germanium layer, the leak current is reduced and excellent element isolation characteristics can be obtained.

Further, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, after forming a plurality of island-shaped Si—Ge mixed crystal layers on a part of the germanium layer, the Si—Ge mixed crystal layer is formed. Forming a MOSFET having a channel region as a channel region, and then forming an element isolation insulating film on the germanium layer to easily process a MOSFET having an island-like Si-Ge mixed crystal layer to improve the short channel effect. And a stable element isolation insulating film such as a silicon oxide film can be formed on the germanium layer by a simple manufacturing technique.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and a duplicate description will be omitted.

(Embodiment 1) FIGS. 1 to 8 are sectional views showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention. A semiconductor integrated circuit device of the present invention and a specific manufacturing method thereof will be described with reference to FIG.

First, as shown in FIG. 1, a substrate 1 having a semiconductor region such as p-type single crystal silicon is prepared, and a germanium layer 2 is formed on the surface of the substrate 1 by a CVD method.
It is formed with a thickness of 00Å.

The substrate 1 is a semiconductor wafer made of single-crystal silicon, has a circular planar shape, and an orientation flat is provided in a part thereof, and a plurality of square IC chip formation regions are formed inside in the XY directions. It has one. However, in the present embodiment, the substrate 1 is not limited to a semiconductor wafer made of silicon alone, but may be an SOI (Silicon on I) substrate.
This is a general term for substrates including a variety of materials such as a semiconductor wafer in which a single crystal thin film of silicon is formed on an insulating region (substrate) such as an insulator structure.

Next, CV is formed on the surface of the germanium layer 2.
The Si-Ge mixed crystal layer 3, which is a mixed crystal of silicon and germanium, is formed into 5 by the D (Chemical Vapor Deposition) method.
It is formed with a thickness of 00Å. The Si—Ge mixed crystal layer 3 is a superlattice layer having a relative dielectric constant higher than that of a semiconductor such as silicon, and is formed by a CVD method using a mixed crystal gas of SiH ₄ and GeH ₄ as a reaction gas. Is.

Next, as shown in FIG. 2, the Si--Ge
A photoresist film is formed on a selective region of the surface of the mixed crystal layer 3 and is used as an etching mask for Si-
The Ge mixed crystal layer 3 is patterned by a photolithography technique for selectively etching to form island-shaped Si-Ge.
Mixed crystal layers 4 and 5 are formed.

Next, as shown in FIG. 3, an insulating film 6 such as a silicon oxide film is formed on the substrate 1 having the germanium layer 2 and the Si-Ge mixed crystal layers 4 and 5 by the CVD method.
It is formed with a film thickness of 00Å. The insulating film 6 made of the silicon oxide film or the like has a function as a protective film or the like when impurities are ion-implanted in a later step.

Next, as shown in FIG. 3, a device isolation insulating film 7 such as a silicon oxide film having a thickness of 4000 Å is formed on the substrate 1 by a CVD method, and then a photolithography technique is used. Patterning is performed by selectively removing the element isolation insulating film 7 such as a silicon oxide film to form the element isolation insulating film 7 that becomes element isolation.

Next, as shown in FIG. 4, a photoresist film for use as an impurity diffusion mask is formed so as to cover the right half region in the drawing, and then boron is formed in the left half region. A p-type impurity such as is ion-implanted by an ion implantation method to form a p-type well region 8. Next, after removing the unnecessary photoresist film, a new photoresist film for use as an impurity diffusion mask is formed so as to cover the left half region of the drawing, and then the right film is formed. N such as phosphorus in half the area
-Type impurities are ion-implanted by the ion implantation method,
The n-type well region 9 is formed. Next, an operation of removing the photoresist film which has become unnecessary is performed.

Next, the insulating film 6 whose surface is exposed
Is no longer needed and should be removed.

Next, as shown in FIG. 5, a 100 Å gate insulating film 10 made of a silicon oxide film or the like is formed on the surfaces of the exposed germanium layer 2 and the Si-Ge mixed crystal layers 4 and 5 by the CVD method. It is formed to have a film thickness of about a certain degree.

Next, the gate electrode 11 is formed on a part of the surface of the gate insulating film 10 formed on the surfaces of the Si-Ge mixed crystal layers 4 and 5. The gate electrode 11 is formed by forming a conductive polycrystalline silicon film or the like by a CVD method and then performing patterning as a gate electrode by using a photolithography technique.

Next, as shown in FIG. 6, a photoresist film for use as an impurity diffusion mask is formed so as to cover the right half region of the drawing, and then the photoresist film and gate are formed. Using the electrode 11 as a mask for impurity diffusion, n-type impurities such as phosphorus are ion-implanted into the left half region by an ion implantation method, and the surface is exposed in a self-aligned state using the gate electrode 11 as a mask. An n-type source region 12 and a drain region 13 are formed in a part of the Si—Ge mixed crystal layer 4 and the germanium layer 2 thereunder.

Next, after removing the unnecessary photoresist film, a new photoresist film for use as an impurity diffusion mask is formed so as to cover the left half region in the drawing. Then, using the photoresist film and the gate electrode 11 as a mask for impurity diffusion, p-type impurities such as boron are ion-implanted into the right half region by an ion implantation method, and the gate electrode 11 is used as a mask. Si-Ge mixed crystal layer 5 whose surface is exposed in a consistent state and germanium layer 2 thereunder
A part of the p-type source region 14 and drain region 15
To form. Next, an operation of removing the photoresist film which has become unnecessary is performed.

Next, as shown in FIG. 7, a passivation film 16 such as a silicon oxide film is formed by the CVD method, and then the source region 1 is formed by using the photolithography technique.
Through holes are formed in the passivation film 16 above the drain regions 2 and 14 and the drain regions 13 and 15. The passivation film 16 is a protective film that protects the surface, and
A PSG (Phosho Silicate Glass) film which is a silicon oxide film containing phosphorus and a BPSG which is a silicon oxide film containing boron and phosphorus, which can be formed by the D method.
It is formed using a (Boron Phosho Silicate Glass) film, a single-layer film such as an SOG (Spin On Glass) film that can be formed by a spin coating method, or a composite film combining them.

Next, as shown in FIG. 8, an electrical wiring layer 17 such as an aluminum film or a three-layer film of tungsten and aluminum and tungsten is formed by a CVD method, and then patterned by using a photolithography technique. A patterned electrical wiring layer 17 is formed.

As described above, according to the semiconductor integrated circuit device and the method of manufacturing the same in this embodiment, the short channel effect is improved, the short channel suppressing effect and the element isolation characteristic are excellent, and the synergistic effects thereof are obtained. As a result, a semiconductor integrated circuit device having excellent high speed can be easily manufactured.

In the semiconductor integrated circuit device and the method of manufacturing the same according to the present embodiment described above, the Si--
Ge mixed crystal layers 4 and 5 are formed, and an element isolation insulating film 7 is formed on the germanium layer 2 as an element isolation region.
That is, the Si-Ge mixed crystal layers 4 and 5 are formed as the active regions, the germanium layer 2 is formed so as to surround the regions of the Si-Ge mixed crystal layers 4 and 5, and the element isolation insulation made of a thick silicon oxide film or the like is formed. The film 7 is formed on the germanium layer 2.

Therefore, the permittivity of the channel region of the MOSFET composed of the Si-Ge mixed crystal layers 4 and 5 is about 1.2 times that of silicon in the substrate 1, so that the short channel effect is suppressed. The conditions to be satisfied are obtained, and the short channel effect can be improved. The permittivity of the channel region of the MOSFET composed of the Si-Ge mixed crystal layers 4 and 5 is smaller than that of the germanium layer 2, and a single layer of the germanium layer 2 alone causes the depletion layer to extend too much and punch through is likely to occur. Therefore, since the Si-Ge mixed crystal layers 4 and 5 are provided on the Si-Ge mixed crystal layers 4 and 5 to form the channel regions, the condition that the short channel effect is suppressed can be obtained, and the short channel effect can be improved.

Further, since Ge has a higher dielectric constant than the Si--Ge mixed crystal layer, the threshold voltage Vth of the channel region in the germanium layer 2 is the threshold voltage of the channel region in the Si--Ge mixed crystal layers 4 and 5. It becomes higher than the voltage Vth. Therefore, the leak current in the element isolation region below the element isolation insulating film 7 can be reduced.

Further, since the element isolation insulating film 7 is formed on the upper surface of the germanium layer 2 having a uniform plane orientation, the leak current does not increase in the pattern edge region.

Therefore, according to the semiconductor integrated circuit device and the manufacturing method thereof in this embodiment, the short channel effect is improved, and the semiconductor integrated circuit device excellent in the short channel suppressing effect and the element isolation characteristic can be easily manufactured.

The short channel effect is an inconvenient effect that occurs when the gate length is shortened in the MOSFET, and it remarkably occurs in a region where the gate length, that is, the channel length is 1 μm or less.

That is, when the channel length is shortened, the depletion layer from the drain and the source overhangs just below the gate, and the potential barrier of the channel portion is lowered. As a result, the threshold voltage V
As th decreases, the drain current increases only by slightly increasing the voltage VDS between the drain and the source, and the constant current region cannot be obtained. Further, when the voltage VDS between the drain and the source is increased, a depletion layer from the source and the drain comes into contact with each other to cause a punch-through state, the drain current ID rapidly increases, and the drain-source breakdown voltage decreases. Further, since the drain current (subthreshold current) flowing when the gate voltage VGS is lower than the threshold voltage Vth increases, there arises a problem that the charge holding time becomes short in a dynamic circuit or the like.

Further, when explained in detail with reference to the schematic diagram,
It becomes as follows. Incidentally, FIG. 9 shows the MOS in this embodiment.
FIG. 10 is a schematic plan view of the FET, and FIGS.
It is a schematic sectional drawing of SFET. 9 to 11,
G is a gate electrode, D is a drain, S is a source, DL is a depletion layer, Ge is a germanium layer, W is a silicon substrate, and Z is an element isolation insulating film.

The short channel effect is as shown in FIG.
Depletion layer that can be controlled by the gate electrode G
This is caused by the DL having an inverted trapezoidal shape.

That is, the short channel effect occurs when AB <AC.

Here, A is the end point of the drain D, B is the end point of the depletion layer DL that can be controlled by the gate electrode G on the drain D side, and C is the silicon of the end point of the depletion layer DL on the drain D side inside the silicon substrate W. The projection points on the surface of the substrate W are shown.

On the other hand, as shown in FIG. 11, under the condition AB> AC, the reverse short channel effect occurs in which the threshold voltage Vth increases as the gate length decreases.

By the way, since the length AB from the end point A from the drain D on the surface of the substrate to the end point B on the drain side of the depletion layer DL is proportional to 1/2 of the dielectric constant, the dielectric constant is higher than that of silicon. When a high Si—Ge mixed crystal is formed on the surface of the substrate, its length AB becomes longer than the length AB shown in FIG. 10, and it is possible to make AB = AC. That is, since the cross-sectional shape of the depletion layer DL can be set to a state close to a rectangular shape, the device characteristics can be set to a state between the short channel effect and the reverse short channel effect. From this, an ideal state appears in which the threshold voltage Vth does not change at all with respect to the change in gate length.

Therefore, as a MOSFET, Si-
By using the channel composed of the Ge mixed crystal layer, it is possible to obtain the characteristic that neither the short channel effect nor the reverse short channel effect occurs.

When the gate lengths are the same, the MOSFET having the reverse short channel effect has a higher threshold voltage Vth than the MOSFET having the short channel effect. Therefore, a channel formed of a germanium layer is used in the element isolation region. And the threshold voltage Vth of the element isolation region is
It becomes higher than the threshold voltage Vth of T, and the leak current in the element isolation region can be reduced.

The semiconductor integrated circuit device and the manufacturing technique thereof according to the present embodiment described above use the structure of an ordinary MOSFET, and the Si-Ge mixed crystal layers 4 and 5 are formed in the MOSFET.
However, as another mode, it may have a structure of a variety of semiconductor elements such as MOSFETs.

For example, when the gate length is 1 μm or less,
Since it is necessary to form electric field relaxation and shallow source and drain layers, MO of LDD (Lightly Doped Drain) structure
It is effective to use an SFET and can be applied as another aspect of this embodiment.

In order to reduce the resistance of the gate, source and drain, salicide (Salicide: Self-aligned
It is effective to use a MOSFET having a silicide structure and can be applied as another aspect of this embodiment.

(Embodiment 2) FIG. 12 is a sectional view showing a semiconductor integrated circuit device according to another embodiment of the present invention.

The semiconductor integrated circuit device of this embodiment has an active MOSFET 18 and a parasitic MOSFET 19 which is paired with the active MOSFET 18 and has an element isolation function as a parasitic MOSFET.

The active MOSF in this embodiment
Although the thickness of the gate insulating film 10 in the ET 18 is set to be smaller than that of the gate insulating film 10 in the parasitic MOSFET 19, the thickness of the gate insulating film 10 is set to various values according to the design standard. Can be

The channel region of the active MOSFET 18 is composed of the germanium layer 2 and the Si--Ge mixed crystal layer 4 formed on the surface thereof.

Further, the parasitic MOSFET 1
The channel region in 9 is composed of the germanium layer 2.

Therefore, the permittivity of the channel region of the active MOSFET 18 is the parasitic MOS.
It is smaller than the dielectric constant of the channel region of the FET 19.

Further, the formation of the depletion layer in the active MOSFET 18 has an inverted trapezoidal shape as shown in FIG. 11, and the formation of the depletion layer in the parasitic MOSFET 19 has a trapezoidal shape as shown in FIG. It will be.

Therefore, the parasitic MOSFET
The threshold voltage Vth of 19 becomes larger than the threshold voltage Vth of the active MOSFET 18 while the threshold voltage Vth becomes large due to the reverse short channel effect.

As a result, the element isolation effect in the active MOSFET 18 is reduced by the parasitic MOSFET 1
9 and the germanium layer 2 or a Si-Ge mixed crystal layer 4 with the germanium layer 2 which cannot form a stable oxide film.
Even with a structure in which and are used as the channel region, excellent element characteristics and element isolation characteristics can be obtained.

Therefore, the parasitic MOSFET
The threshold voltage Vth of 19 becomes larger than the threshold voltage Vth of the active MOSFET 18 while the threshold voltage Vth becomes large due to the reverse short channel effect.

The manufacturing process of the semiconductor integrated circuit device according to the present embodiment can be performed by diverting the manufacturing method of the semiconductor integrated circuit device according to the first embodiment described above, and therefore detailed description thereof will be omitted.

(Embodiment 3) FIG. 13 is a sectional view showing a semiconductor integrated circuit device according to another embodiment of the present invention.

The semiconductor integrated circuit device of this embodiment has an SOI
The semiconductor device has a structure, and a semiconductor element is formed on an insulating film 21 such as a silicon oxide film formed on the surface of a semiconductor substrate 20 such as silicon. It is paired with it and has a parasitic MOSFET 19 having an element isolation function as a parasitic MOSFET.

The active MOSF in this embodiment
Although the thickness of the gate insulating film 10 in the ET 18 is set to be smaller than that of the gate insulating film 10 in the parasitic MOSFET 19, the thickness of the gate insulating film 10 is set to various values according to the design standard. Can be

The channel region of the active MOSFET 18 is composed of the Si-Ge mixed crystal layer 4.

Further, the parasitic MOSFET 1
The channel region in 9 is composed of the germanium layer 2.

Therefore, the permittivity of the channel region of the active MOSFET 18 is the parasitic MOS.
It is smaller than the dielectric constant of the channel region of the FET 19.

The formation of the depletion layer in the active MOSFET 18 has an inverted trapezoidal shape as shown in FIG. 11, and the formation of the depletion layer in the parasitic MOSFET 19 has a trapezoidal shape as shown in FIG. It will be.

Therefore, the parasitic MOSFET
The threshold voltage Vth of 19 becomes larger than the threshold voltage Vth of the active MOSFET 18 while the threshold voltage Vth becomes large due to the reverse short channel effect.

As a result, the element isolation effect in the active MOSFET 18 is reduced by the parasitic MOSFET 1
Even if the germanium layer 2 which is improved by 9 and cannot form a stable oxide film is used as the channel region, the device characteristics and the element isolation characteristics can be made excellent.

Therefore, the parasitic MOSFET
The threshold voltage Vth of 19 becomes larger than the threshold voltage Vth of the active MOSFET 18 while the threshold voltage Vth becomes large due to the reverse short channel effect.

The manufacturing process of the semiconductor integrated circuit device according to the present embodiment can be carried out by diverting the manufacturing method of the semiconductor integrated circuit device according to the first and second embodiments described above, and detailed description thereof will be omitted.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

[0076]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

According to the semiconductor integrated circuit device of the present invention, a plurality of island-shaped Si—Ge mixed crystal layers provided on the substrate and the Si—Ge mixed crystal layer serving as a channel region are used.
MO having an OSFET and a plurality of island-shaped Si-Ge mixed crystal layers provided on the substrate as a channel region.
By using SFET, the shape of the depletion layer that can be controlled by the gate electrode in the channel region can be improved. Therefore, the short channel effect can be improved. Further, since a stable element isolation insulating film such as a silicon oxide film can be provided on the germanium layer, leakage current is reduced and excellent element isolation characteristics can be obtained.

According to the method for manufacturing a semiconductor integrated circuit device of the present invention, a step of forming a plurality of island-shaped Si—Ge mixed crystal layers on a part of the germanium layer formed on the substrate, MOS using the Si-Ge mixed crystal layer as a channel region
After forming a FET and a step of forming an insulating film for element isolation on the germanium layer, after forming a plurality of island-shaped Si-Ge mixed crystal layers on a part of the germanium layer , MO using the Si-Ge mixed crystal layer as a channel region
By forming an SFET and then forming an element isolation insulating film on the germanium layer, an island-shaped Si-G is formed.
MO with a mixed crystal layer to easily improve the short channel effect
The SFET can be easily formed by fine processing. Also,
A stable element isolation insulating film such as a silicon oxide film can be formed on the germanium layer by a simple manufacturing technique.

Further, in the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, the Si—Ge mixed crystal layer is formed as the channel region, and the element isolation insulating film is formed on the germanium layer as the element isolation region. By this, Si-G
The permittivity of the channel region of the MOSFET composed of the e mixed crystal layer is about 1.2 times that of silicon, so that the condition for suppressing the short channel effect can be obtained and the short channel effect can be improved. .

Furthermore, since the threshold voltage Vth of the channel region in the germanium layer is higher than the threshold voltage Vth of the channel region in the Si--Ge mixed crystal layer, the threshold voltage Vth in the element isolation region below the element isolation insulating film is increased. Leakage current is reduced. Further, since the element isolation insulating film is formed on the upper surface of the germanium layer having a uniform plane orientation, the leak current does not increase in the pattern edge region.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 9 is a schematic plan view showing a MOSFET in a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view showing a MOSFET.

FIG. 11 is a schematic cross-sectional view showing a MOSFET.

FIG. 12 is a sectional view showing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a semiconductor integrated circuit device which is another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Germanium layer 3 Si-Ge mixed crystal layer 4 Si-Ge mixed crystal layer 5 Si-Ge mixed crystal layer 6 Insulating film 7 Insulating film for element isolation 8 p-type well region 9 n-type well region 10 Gate insulating film 11 Gate electrode 12 Source region 13 Drain region 14 Source region 15 Drain region 16 Passivation film 17 Electrical wiring layer 18 Active MOSFET 19 Parasitic MOSFET 20 Semiconductor substrate 21 Insulating film A End point B End point C Projection point D Drain DL Depletion layer G Gate electrode Ge germanium layer S source W silicon substrate Z insulating film for element isolation

Claims (9)

[Claims] 1. A plurality of island-shaped Si—Ge mixed crystal layers provided on a substrate, a gate insulating film and a gate electrode in a MOSFET having the Si—Ge mixed crystal layer as a channel region, and the Si. -A semiconductor integrated circuit device having a source and a drain provided in a Ge mixed crystal layer. 2. A germanium layer provided on a substrate, a plurality of island-shaped Si—Ge mixed crystal layers provided on the germanium layer, and the Si—Ge mixed crystal layer as a channel region. The semiconductor integrated circuit device having a gate insulating film and a gate electrode in the MOSFET, and a source and a drain provided in the Si—Ge mixed crystal layer. 3. A germanium layer provided on a substrate, a plurality of island-shaped Si—Ge mixed crystal layers provided on the germanium layer, and the Si—Ge mixed crystal layer serving as a channel region. A gate insulating film and a gate electrode in the MOSFET, a source and a drain provided in the Si—Ge mixed crystal layer, and an element isolation insulating film provided on the germanium layer. Semiconductor integrated circuit device. 4. A germanium layer provided on a substrate, a plurality of Si—Ge mixed crystal layers provided on a part of the germanium layer, the germanium layer and the Si—Ge mixed crystal. MOS with layer as channel region
A semiconductor integrated circuit device comprising an FET and a MOSFET having the germanium layer as a channel region. 5. A plurality of Si—Ge mixed crystal layers provided on a part of the substrate so as to be spaced apart from each other, and the substrate of the substrate between the Si—Ge mixed crystal layers separated from each other. A semiconductor integrated circuit device comprising: a germanium layer provided above; a MOSFET having the Si—Ge mixed crystal layer as a channel region; and a MOSFET having the germanium layer as a channel region. 6. The semiconductor integrated circuit device according to claim 1, wherein the MOSFET is a MOSFET having an LDD structure or a salicide structure. 7. A step of forming a germanium layer on a substrate, and a plurality of island-shaped Si-G on a part of the germanium layer.
a step of forming an e mixed crystal layer, a step of forming a gate insulating film on the Si—Ge mixed crystal layer, a step of forming a gate electrode on a part of the gate insulating film, the gate electrode With a mask as a mask, forming a source region and a drain region by ion-implanting impurities into the Si—Ge mixed crystal layer, and forming an element isolation insulating film on the germanium layer. A method of manufacturing a semiconductor integrated circuit device having a feature. 8. A step of forming a germanium layer on a part of a substrate, a step of forming a Si—Ge mixed crystal layer on another part of the substrate, and using the germanium layer as a channel region. MOSFET
And a step of forming a MOSFET having the Si-Ge mixed crystal layer as a channel region, the method of manufacturing a semiconductor integrated circuit device. 9. A step of forming a germanium layer on a substrate, a step of forming a Si—Ge mixed crystal layer on a part of the germanium layer, and a MOSFET having the germanium layer as a channel region.
And a step of forming a MOSFET having the germanium layer and the Si—Ge mixed crystal layer formed thereon as a channel region, the method of manufacturing a semiconductor integrated circuit device.