JPH07193605A - Multi-value modulation circuit - Google Patents

Abstract

PURPOSE:To obtain a large transmission capacity with an inexpensive device by allowing the circuit not to be susceptible to an external factor such as an ambient temperature change. CONSTITUTION:Shift register groups 1, 2 provide an output of data in a timing of a clock generating circuit 3 and roll-off waveform shape data stored in ROMs 5, 6 are read in the timing of a frequency divider circuit 4 to obtain multi-value processing modulation data. Then the multi-value processing data are converted into analog data by a D/A converter 8 and the analog data are given to a BPF 9, from which the multi-value modulation wave is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital multilevel modulation circuit used in a television transmitter, a digital line network or the like.

[0002]

2. Description of the Related Art In wireless communication such as a television transmitter and wired communication such as a digital line network, data communication is performed by performing digital modulation such as QAM and QPSK using a multi-value modulation circuit.

The multi-valued modulation circuit includes an analog type one whose main part is an analog circuit and a digital type one whose main part is a digital circuit.

FIG. 2 is a block diagram of a conventional analog multi-level modulation circuit.

Pch data and Qch data are m-bit parallel digital data, respectively, which are converted into analog signals by D / A converters 30 and 31. This D / A
The outputs of the converters 30 and 31 are roll-off shaped by LPFs (low-pass filters) 32 and 33, and a multiplier 36
And 37.

The local oscillator 34 generates a carrier wave, which is directly input to the multiplier 36, but is multiplied by the multiplier 37.
Are input with a phase shift of 90 degrees via a π / 2 shift unit.

The multiplier 36 multiplies the output of the LPF 32 by the output of the local oscillator 34 and outputs the product. The multiplier 37 outputs the LPF.
The output of 33 and the output of the π / 2 shift unit are multiplied and output. The outputs of the multipliers 36 and 37 are both input to the adder 38, and the addition result of the adder 38 becomes a multilevel modulation wave.

On the other hand, FIG. 3 is a block diagram of a conventional digital multi-level modulation circuit.

Pch data and Qch data are shown in FIG.
Similarly, each is m-bit parallel digital data, and these data are digital filters 40 and 4
It is roll-off shaped at 1 and input to multipliers 44 and 45.

The crystal oscillator 42 oscillates a frequency that is an integral multiple of the carrier wave. Two types of digital subcarrier data having a mutual phase difference of 90 degrees are stored in advance in the ROM 43, and the digital subcarrier data is read from the ROM 43 by utilizing the oscillation frequency of the crystal oscillator 42. The digital subcarrier data read from the ROM 43 is output to the multipliers 44 and 45, but the phase difference between the data output to the multiplier 44 and the data output to the multiplier 45 is 90 degrees.

The multiplier 44 multiplies the output of the digital filter 40 and the digital subcarrier data read from the ROM 43 and outputs the product, and the multiplier 45 outputs the digital filter 41 and the digital subcarrier read from the ROM 43. Multiply with data and output. The outputs of the multipliers 44 and 45 are both input to the adder 46, and the addition result of the adder 46 is analog-converted by the D / A converter 47. And finally, BPF (bandpass filter)
At 48, the image component is removed to form a multi-level modulated wave.

[0012]

In the case of the conventional analog multi-level modulation circuit shown in FIG. 2, since the main part of the circuit is an analog type, it is affected by external factors such as environmental temperature changes. However, it is difficult to adjust the Pch data and the Qch data so as to have orthogonality, and to adjust the LPF for roll-off shaping.

On the other hand, in the case of the conventional digital multi-level modulation circuit shown in FIG. 3, since the main part of the circuit is a digital type, the problems in the conventional analog multi-level modulation circuit described above can be solved. However, there is a problem in that a large transmission capacity cannot be obtained due to the operating speed limit of each device. There is also a problem that each device such as a digital filter is expensive.

The present invention has been made in view of the above points, and an object thereof is to make it less susceptible to external factors such as environmental temperature changes and to obtain a large transmission capacity with an inexpensive device. .

[0015]

In order to achieve the above object, the present invention provides a plurality of shift register groups consisting of m shift registers for inputting each bit of m-bit parallel data, and roll-off waveform shaping. Pre-store data,
First, using the output of the shift register group as an address to output roll-off waveform shaping data according to the address
ROM and roll-off waveform shaping data having a polarity opposite to that of the roll-off waveform shaping data stored in the first ROM are stored in advance, and the output of the shift register group is used as an address to perform the roll-off waveform shaping according to this address. A second ROM for outputting data and a clock generating means for controlling the output timing of the shift register group, the first ROM and the second ROM so as to perform quadrature modulation, and control by the clock generating means. Output of the first ROM and the second RO
A combination circuit for combining the output of M, a D / A conversion circuit for analog-converting the output of the combination circuit, and a bandpass filter for removing an image component from the output of the D / A conversion circuit are provided.

[0016]

According to the present invention, the shift register group outputs data at the timing controlled by the clock generating means, and the first ROM and the second ROM have the above-described structure.
The multi-valued modulated wave data is obtained by reading the roll-off waveform shaping data stored in. And D / A
The conversion circuit converts the multi-valued modulation wave data into an analog signal and finally passes the band pass filter to obtain a multi-valued modulation wave.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a multilevel modulation circuit according to the present invention.

The Pch data and the Qch data are m-bit parallel digital data as in the conventional example, and these data are the shift register groups 1 and 2.
Entered in. The shift register groups 1 and 2 each include m shift registers SR1 to SRm. Shift registers SR1 to SRm of shift register groups 1 and 2
The number of stages of each is the same as that of the digital filter 4 shown in FIG.
Corresponds to 0 and 41 taps.

The shift registers SR1 to SRm of the shift register groups 1 and 2 output data according to the clock from the clock generating circuit 3, and the clock from the clock generating circuit 3 is input to the shift register group 1 as it is. Then, the clock from the clock generation circuit 3 is input to the shift register group 2 via an inverter. For this reason, the shift register group 2 does not output data when the shift register group 1 is outputting data, so that the shift register group 1 outputs data alternately.

The clock from the clock generating circuit 3 is also input to the frequency dividing circuit 4 and divided by 2 by the frequency dividing circuit 4.
The clock divided by two is directly input to the enable terminal E of the ROM 5 and is input to the enable terminal E of the ROM 6 via an inverter. For this reason, the data is read from the ROM 5 in an alternating manner such that the data is not read from the ROM 6 while the data is being read from the ROM 5.

Roll-off waveform shaping data is stored in the ROMs 5 and 6, and data having polarities opposite to each other is stored in the ROM 5 and the ROM 6. ROM 5 using data from shift register groups 1 and 2 as an address
The data read out from the AND circuit 6 and OR circuit 7 are both
Entered in. Then, the output of the OR circuit 7 is input to the D / A converter 8 and converted into an analog signal, and finally the image component is removed by the BPF 9 to become a multi-level modulated wave.

In the multi-valued modulation circuit shown in FIG. 1, the output timing of the shift register groups 1 and 2 and the read timing of the ROMs 5 and 6 are controlled by the clock from the clock generation circuit 3 to perform quadrature modulation. .

That is, the input data to the D / A converter 8 are (P, 0, -P, 0, ...) And (0, Q, 0,-).
Q, ...) is added, and assuming that the amplitude of the subcarrier is 1, the waveform converted from analog by the D / A converter 8 and the image component removed by the BPF 9 becomes a multilevel modulation wave. You can see that

Therefore, assuming that the clock frequency of the clock generation circuit 3 is f _S , the waveform obtained by removing the image component by the BPF 9 has a carrier frequency of f _S / 4.
Is a multi-level modulated wave.

As is well known, the shift register used in the present invention has a higher operating speed and a lower cost than the digital filter used in the conventional digital multi-level modulation circuit, and therefore has a low transmission capacity. It is possible to increase the capacity and reduce the cost.

[0027]

As described above, according to the present invention,
Since the multi-valued modulation circuit can be configured by circuit elements such as a shift register and a ROM that operate at high speed and are inexpensive, the transmission capacity can be easily increased and the cost can be reduced.

Further, since the main part of the multilevel modulation circuit according to the present invention is of a digital type, it is less affected by external factors such as environmental temperature changes.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a multilevel modulation circuit according to the present invention.

FIG. 2 is a block diagram of a conventional analog multi-level modulation circuit.

FIG. 3 is a block diagram of a conventional digital multi-level modulation circuit.

[Explanation of symbols]

 1, 2 shift register group 3 clock generation circuit 4 frequency divider circuit 5, 6 ROM 7 OR circuit 8 D / A converter 9 BPF

Claims (2)

[Claims] 1. A waveform shaping section comprising a shift register and a ROM, which inputs parallel digital data and outputs data without intersymbol interference, a clock generating circuit and a frequency dividing circuit, and the waveform shaping section A quadrature modulator for converting an output into digital multilevel modulation wave data, and a D / A for converting the digital multilevel modulation wave data into an analog signal.
A multilevel modulation circuit comprising an A conversion section and a bandpass filter section for removing an image component from the output of the D / A conversion section. 2. A plurality of shift register groups consisting of m shift registers for inputting each bit of m-bit parallel data and roll-off waveform shaping data are stored in advance, and the output of the shift register group is used as an address. A first ROM for outputting roll-off waveform shaping data corresponding to an address; and roll-off waveform shaping data having a polarity opposite to that of the roll-off waveform shaping data stored in the first ROM, stored in advance,
A second ROM that outputs the roll-off waveform shaping data corresponding to the address using the output of the shift register group as an address; and the shift register group, the first ROM, and the second ROM so as to perform quadrature modulation. A clock generating means for controlling the output timing of the ROM; a synthesizing circuit for synthesizing the output of the first ROM and the output of the second ROM output at the timing controlled by the clock generating means; A multilevel modulation circuit comprising a D / A conversion circuit for converting the output of the circuit into an analog signal and a bandpass filter for removing an image component from the output of the D / A conversion circuit.