JPH06177133A - Multilayer semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a multilayer LSI having good heat dissipation characteristics in which erroneous function or malfunction of circuit elements due to heat is prevented. CONSTITUTION:In a multilayer LSI100 where a plurality of LSI chips 208, 210 are laminated three-dimensionally, dielectric film is removed partially or entirely from LSI wiring constituting the upper and lower LSI chips 208, 210.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated semiconductor integrated circuit, and more particularly to a laminated LSI in which large-scale semiconductor integrated circuits (hereinafter abbreviated as LSI) having circuit elements are laminated in multiple layers. .

[0002]

2. Description of the Related Art In recent years, the degree of integration of LSIs has been increasing four times in three years, and it is expected that the design rule of DRAM in the year 2000 will be about 0.15 μm and the degree of integration will be 1G. To be done. However, these highly integrated circuits pose technical difficulties in all aspects of design, manufacturing, and inspection. For example, ROM, RAM, ALU, CPU, I / O
With a one-chip microcomputer including a controller, as the number of integrated elements on one chip increases, the time required for designing increases, the manufacturing yield decreases, the inspection time increases, and complete inspection becomes difficult. ing.

Therefore, research and development for three-dimensionally bonding and laminating chips and wafers, rather than planar miniaturization, are being actively pursued. For example, most of semiconductor substrates used industrially have a thickness of about 500 μm to 600 μm, and a transistor formed by using the surface thereof has a thickness of about several μm. The miniaturization of an LSI is attempted by thinning a semiconductor substrate to be thinned and stacking the thinned semiconductor substrates.

FIG. 4 (a) is a schematic plan view and a schematic cross-sectional view showing a conventional LSI stacking process.
~ (H). FIGS. 4 (a ') and 4 (e') are plan views showing a semiconductor substrate 202 and a semiconductor substrate 201 on which a transistor circuit is produced through steps such as thermal oxidation and ion implantation on a semiconductor wafer substrate. 4A and 4E show a semiconductor substrate 202 and a semiconductor substrate 201.
FIG.

These semiconductor substrate 201 and semiconductor substrate 2
No. 02 is then advanced to the laminating step, which is roughly divided into the following three steps.

The first step is a step of manufacturing a laminated LSI chip and is shown in FIGS. 4 (a) to 4 (e). First,
The LS is formed on the front surface side of the semiconductor substrate 202 on which the LSI is formed.
The supporting substrate 205 for holding the I-chip is adhered using an adhesive such as a resin (FIG. 4B). FIG. 5 shows an enlarged cross-sectional view of the semiconductor substrate 202 on which the support substrate 205 is mounted at this time. As shown in FIG. 5, the semiconductor substrate 2
02, the gate electrode 30 surrounded by the gate insulating film 307
5, the insulating layer 302 is formed on the semiconductor substrate 202 on which the gate electrode 305 is not formed, and the insulating film 303 is formed on the insulating layer 302. An LSI wiring 301 is formed between the gate insulating film 307 and the insulating film 303, and a through hole 300 for connecting the upper and lower LSIs is formed at a predetermined position of the insulating film 303 by chemical etching or reactive ion etching. Formed by the method.
After that, these through holes 300, insulating film 303, L
An insulating film 304 is formed on the SI wiring 301 and the gate insulating film 307 by a CVD method or the like.
6 is applied to the surface of the wafer, and the supporting substrate 205 is bonded onto the semiconductor substrate 202.

Next, in order to smoothly transfer signals between the upper and lower LSIs after stacking, the back surface of the semiconductor substrate 202 is polished to make the semiconductor substrate 202 sufficiently thin to form the thinned semiconductor substrate 202a. Formed (FIG. 4C). FIG. 6 shows an enlarged cross-sectional view of the internal structure of the thinned semiconductor substrate 202a at this time. As shown in FIG. 6, thinned semiconductor substrate 20
The thinned semiconductor substrate 202a is formed by polishing until 2a becomes the AA 'line shown in FIG. 5, that is, the through hole 300a penetrating the through hole 300.

Further, the thinned semiconductor substrate 202a and the supporting substrate 205 are connected to each other by the scribe line 204 described above.
Along the line to complete the fabrication of the stacked LSI chip 206 (FIG. 4D).

Next, the step of adhering the laminated LSI chips is shown in FIGS. 4 (f) and 4 (g). First, FIG. 4 (e)
And the laminated LSI chip 20 in which the supporting substrate 205 manufactured in the first step is mounted on the LSI chip portion manufactured on the surface of the semiconductor substrate 201 shown in FIG.
6 are aligned and bonded with an adhesive or the like (see FIG. 4).
(F)). Then, the supporting substrate 205 of the stacked LSI chip 206 is removed by melting the adhesive 306 by a chemical means such as heat melting, and the upper LSI chip 208 is left on the semiconductor substrate 201 (FIG. 4G).

The second step is a step in which the number of stacked LSIs can be selected by repeating the required number of times. In FIG. 7, the semiconductor substrate 20 as shown in FIG.
2 shows an enlarged cross-sectional view of the internal structure when two of the two are stacked, for example. A gate electrode 305 surrounded by a gate insulating film 307 is formed on the semiconductor substrate 201.
On the semiconductor substrate 201 on which the insulating layer 302 is not formed
Is formed, an insulating film 303 is formed on the insulating layer 302, and the LS is formed between the insulating film 303 and the gate oxide film 307.
The I wiring 500 is formed. An adhesive 501 is applied on the insulating film 303, the gate oxide film 307, and the LSI wiring 500 to mount the upper LSI chip 208.

A gate electrode 305 surrounded by a gate insulating film 307 is also formed on the upper LSI chip 208, an insulating layer 302 is formed on the semiconductor substrate 201 on which the gate electrode 305 is not formed, and on the insulating layer 302. Is an insulating film 3
03 is formed, and the LSI wiring 301 is formed between the insulating film 303 and the gate oxide film 307. Through holes 300 are formed at predetermined locations in the upper LSI chip 208, and the adhesive 501 under the through holes 300 is removed through the through holes 300 by using a method such as chemical etching or reactive ion etching. The surface of the LSI wiring 500 of the semiconductor substrate 201 is exposed. Insulating film 303 of upper LSI chip 208, LSI wiring 30
1. An insulating film 304 is formed on the gate insulating film 307 and on the sidewall surface of the through hole 300.

FIG. 8 shows the LSI chip 208 shown in FIG.
6 is a cross-sectional view showing a state in which a through-hole electrode 600 is formed in the through-hole 300 in order to electrically connect it to the LSI wiring 500, and the through-hole electrode 600 is formed using a technique such as vapor deposition or plating. To do.

The third and final step is the LS after the lamination is completed.
This is a step of cutting I into chips, which is shown in FIG. In the second step, after laminating a desired number of LSI chips 208 on the semiconductor substrate 201, the LSI chips 208 are cut into laminated LSI chips along the scribe line 203 shown in FIG. After that, the laminated LSI chip 209 becomes a product through an assembly process generally called a latter half process.

[0014]

However, in the above laminated LSI, a plurality of upper LSI chips 2 are used.
Since the 08s are stacked, there is a problem that it is difficult to dissipate the generated heat as compared with the conventional two-dimensional LSI, and malfunction or malfunction occurs due to the heat generated by the circuit element.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a laminated LSI which has good heat dissipation and does not cause malfunction or malfunction of the element due to heat.

[0016]

In order to achieve the above object, a laminated semiconductor integrated circuit according to the present invention is a laminated semiconductor integrated circuit in which a plurality of semiconductor integrated circuits are laminated by an adhesive means to form a three-dimensional structure. In the above, the semiconductor integrated circuit wiring which constitutes each semiconductor integrated circuit is characterized in that a part or all of the semiconductor integrated circuit wiring is not covered with an insulating film. In addition, the stacked semiconductor integrated circuit is characterized in that the semiconductor integrated circuit wiring has a tunnel portion.

[0017]

According to the stacked semiconductor integrated circuit, more specifically, the stacked large-scale semiconductor integrated circuit (LSI), some or all of the LSI wirings constituting each stacked LSI are covered with the insulating film. Therefore, the heat generated in the LSI in the stacked type LSI is radiated through the LSI wiring and the heat radiation characteristics are improved.

Further, when the LSI wiring has an uneven shape, the area in contact with the outside air is increased, and the heat dissipation characteristics are further improved.

In addition, when the LSI wiring has a tunnel portion, the area in contact with the outside air is further increased, and the heat dissipation characteristics are further improved.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a laminated LSI according to the present invention will be described below with reference to the drawings. The components having the same functions as those of the conventional example are designated by the same reference numerals.

FIG. 1 is a schematic enlarged cross-sectional view showing a laminated LSI according to the embodiment, in which LSI chips are laminated in two layers. Reference numeral 210 in the drawing denotes a lower LSI chip, and the lower LSI chip 210 is configured as follows. A gate electrode 305 surrounded by a gate insulating film 307 is formed over the semiconductor substrate 201, an insulating layer 302 is formed over the semiconductor substrate 201 where the gate electrode 305 is not formed, and an insulating film 303 is formed over the insulating layer 302. LSI is formed between the insulating film 303 and the gate insulating film 307.
The wiring 500 is formed. Further, a metal vapor deposition method, a sputtering method, or the like is used as a method for forming the LSI wiring 500, and a plating method or the like may be further used when forming a composite film.

In the figure, reference numeral 208 indicates an upper LSI chip, and the upper LSI chip 208 is constructed as follows. A gate insulating film 307 is formed on the stacked semiconductor substrate 202a.
The gate electrode 305 surrounded by the
The insulating layer 302 is formed on the laminated semiconductor substrate 202a on which 05 is not formed, and the insulating film 303 is formed on the insulating layer 302. Gate insulating film 307 and insulating film 30
3, an LSI wiring 301 is formed between
Through holes connecting the upper and lower LSIs are formed at predetermined locations 03 by a method such as chemical etching or reactive ion etching.

After that, an insulating film 304 for protecting the device is formed on the side wall of the through hole 300a, the LSI wiring 301 and the gate insulating film 307 which have been penetrated by the polishing process by the CVD method or the like. Then, the upper LSI chip 208
Is adhered onto the lower LSI chip 210 coated with the adhesive 501 to form the laminated LSI 100. A through hole electrode 600 is formed in the through hole 300a that penetrates.

Stacked type LSI 10 constructed as described above
At 0, the heat generated in the LSI chip 210 is transferred to the LSI
The air can be effectively released from the wiring 500 to the outside air.
Therefore, the heat dissipation characteristics are improved, and it becomes possible to prevent malfunction and malfunction of the element.

FIG. 2 shows a second laminated LSI according to the present invention.
3 is a schematic enlarged cross-sectional view showing the embodiment of FIG. In the figure, reference numeral 208 denotes an upper LSI chip, and the upper LSI chip 208 has the same configuration as that of the above-described embodiment, and a detailed description of this portion will be omitted here. Reference numeral 201 in the figure denotes a semiconductor substrate, and a gate insulating film 307 surrounding the gate electrode 305 is formed on the semiconductor substrate 201.
On the semiconductor substrate 201 on which the insulating layer 302 is not formed
Is formed, an insulating film 303 is formed on the insulating film 302, and LS is provided between the insulating film 303 and the gate insulating film 307.
The I wiring 502 is formed. Adhesive 50 is applied to the lower LSI chip 210 where the upper LSI chip 208 is mounted.
1 is applied and the lower LSI chip 210 and the upper LSI chip 208 are bonded. Also, the upper LSI chip 2
Although the surface of the LSI wiring 502 where the 08 is mounted is formed in a flat shape, a large number of convex portions 502 are formed on the surface of the LSI wiring 502 which is not covered with the upper LSI chip 208 and is exposed to the outside air.
a is formed. A selective plating method or the like is used for forming the LSI wiring 502.

Stacked type LSI 101 configured as described above
In this case, since many protrusions 502a are formed on the surface of the LSI wiring 502 which is exposed to the outside air, the area in contact with the outside air can be increased. Therefore, the lower LSI chip 2
It is possible to further improve the heat dissipation characteristics of the heat generated in the device 10, and prevent malfunction or malfunction of the element due to the generated heat.

FIG. 3 shows a third embodiment of the laminated LSI according to the present invention.
3 is a schematic enlarged cross-sectional view showing the embodiment of FIG. In the figure, reference numeral 208 denotes an upper LSI chip, and the upper LSI chip 208 has the same configuration as that of the above-described embodiment, and a detailed description of this portion will be omitted here. Reference numeral 201 in the figure denotes a semiconductor substrate, and a gate insulating film 307 surrounding the gate electrode 305 is formed on the semiconductor substrate 201.
Is formed on the lower semiconductor substrate 201 on which the insulating layer 3 is not formed.
02 is formed, an insulating film 303 is formed on the insulating layer 302, and L is provided between the insulating film 303 and the gate insulating film 307.
The SI wiring 503 is formed. Lower LSI chip 210
Adhesive 5 is applied to the place where the upper LSI chip 208 of
01 is applied to the lower LSI chip 210 and the upper LSI.
The chip 208 and the chip 208 are bonded together to form the stacked LSI 102. In addition, the LS of the place where the upper LSI 208 is mounted
Although the surface of the I wiring 503 is formed in a flat shape, the upper LSI
LSI wiring 503 that is not covered by the chip 203 and is exposed to the outside air
A large number of tunnel portions 503a are formed on the surface. The inside of this tunnel portion 503a is a cavity that contacts the outside air. A selective plating method is used to form the LSI wiring 503, and the tunnel portion 503a is formed by etching using an etching solution.

The laminated LSI 102 thus configured
In this case, a large number of tunnel portions 503a are formed on the surface of the LSI wiring 503 exposed to the outside air, so that the area in contact with the outside air can be increased. Therefore, it is possible to further improve the heat dissipation characteristic of the heat generated in the lower LSI chip 210, and prevent malfunction or malfunction of the element due to the generated heat.

In the above embodiment, the case of application to a MOS-LSI is shown, but the present invention is not limited to this, and may be applied to a bipolar LSI, a compound semiconductor, or an individual semiconductor such as an LED. Further, in FIG. 4, the LSI to be laminated is laminated after being cut into chips, but the invention is not limited to this, and may be laminated as a wafer.

The material for the LSI wiring may be any material having electrical conductivity, but it is preferably a material (aluminum or the like) that forms a film when exposed to the atmosphere.

[0031]

As described above in detail, in the laminated semiconductor integrated circuit according to the present invention, some or all of the semiconductor integrated circuit wirings constituting each laminated semiconductor integrated circuit are not covered with the insulating film. Therefore, the heat generated in each semiconductor integrated circuit in the stacked semiconductor integrated circuit is efficiently radiated through the semiconductor integrated circuit wiring, and the heat radiation characteristics can be improved.

Further, when the semiconductor integrated circuit wiring has an uneven shape, the area in contact with the outside air becomes large and the heat dissipation characteristics can be further improved.

Further, when the semiconductor integrated circuit wiring has a tunnel portion, the area in contact with the outside air becomes large and the heat dissipation characteristics can be further improved.

[Brief description of drawings]

FIG. 1 is an enlarged sectional view schematically showing a first embodiment of a laminated LSI according to the present invention.

FIG. 2 is an enlarged cross-sectional view schematically showing a second embodiment of the laminated LSI according to the present invention.

FIG. 3 is an enlarged cross-sectional view schematically showing a third embodiment of the laminated LSI according to the present invention.

4A to 4H are plan views and cross-sectional views showing a manufacturing process of a general laminated LSI, and FIGS. 4A to 4E are plan views showing semiconductor substrates 202 and 201. It is a figure.

FIG. 5 is an upper LSI on which a supporting substrate according to a conventional example is mounted.
It is an expanded sectional view showing.

FIG. 6 is an upper LSI on which a supporting substrate according to a conventional example is mounted.
FIG. 4 is an enlarged cross-sectional view showing the structure of the back surface after polishing.

FIG. 7 is an enlarged cross-sectional view showing a stacked LSI in a conventional example.

FIG. 8 is an enlarged cross-sectional view showing a state after a through-hole electrode is formed on the stacked LSI in the conventional example.

[Explanation of Codes] 100, 101, 102 Stacked LSI 208 Upper LSI Chip 210 Lower LSI Chip 501 Adhesive (Adhesive Means) 502a Convex (Concave and Concave) 503a Tunnel

Claims (3)

[Claims] 1. In a laminated semiconductor integrated circuit in which a plurality of semiconductor integrated circuits are laminated by an adhesive means to form a three-dimensional structure, a part or all of the semiconductor integrated circuit wiring forming each semiconductor integrated circuit is covered with an insulating film. A stacked semiconductor integrated circuit characterized by being not formed. 2. The stacked semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit wiring has an uneven shape. 3. The stacked semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit wiring has a tunnel portion.