JPH06125062A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the flatness of a memory cell region with a peripheral circuit region for higher patterning accuracies by forming a first insulating film on portions of a peripheral circuit lower than the memory cell, and depositing a second insulating film both on the first insulating film and on the memory cell. CONSTITUTION:A first insulating film 28 is formed only on portions of a peripheral circuit 19 that are lower than the memory cell in a memory cell region A, and a second insulating film 31 is deposited both on the first insulating film 28 and on the memory cell. Thus, the height of the peripheral circuit region B is increased by the first insulating film 28, and almost equal to that of the memory cell. This unifies the thickness of resist applied to the second insulating film 31, and consequently eliminates the problem of depth of exposure focus in forming a pattern which is in contact with the lower layers in both regions A and B and expands across the regions, resulting in improved patterning accuracies. An etching stopper film 26 exists only in a beltlike shape in the boundary region C, not in the through holes in the peripheral circuit 19, and no anomaly in shape is not caused, accordingly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device in which the heights of a memory cell and peripheral circuits are significantly different and a method of manufacturing the same.

[0002]

2. Description of the Related Art SRAM (s) composed of MOS transistors
tatic random access memory) The cell is as shown in Figure 7.
Equivalent circuit, and t₁₁, t₁₂Is a driving MOSFET, t
_{twenty one}, t _{twenty two}Is a load MOSFET, t₃₁, t₃₂Is M for transfer
OSFET is shown.

The channel regions of the driving MOSFETs t ₁₁ and t ₁₂ and the transfer MOSFET are formed in the bulk of the semiconductor substrate. Further, the channel regions of the load MOSFETs t ₂₁ and t ₂₂ are provided in the polycrystalline semiconductor film above the semiconductor substrate.

In FIG. 7, each MOSFE surrounded by a broken line
An example of the sectional structure of T is shown in FIG. 8 (a).
In FIG. 8A, a plurality of active regions X surrounded by a selective oxide film 82 are defined in the upper layer of the semiconductor substrate 81. Further, the gate electrode 83 of the driving MOSFET t ₁₁
Is formed on the active region X of the semiconductor substrate 81.
4 and one end thereof is connected to the impurity introduction layer 85 of the adjacent active region X across the selective oxide film 82.

The insulating film 8 covering the gate electrode 83 is also provided.
A gate electrode 87 on the lower side, a polycrystalline semiconductor film 88, and a gate electrode 89 on the upper side, which form the load MOSFET t _22, are formed above 6 by interposing insulating films 90 and 91, respectively.

In this case, impurity is introduced into both sides of the channel region of the polycrystalline semiconductor film 88 to form source / drain regions. Further, the two gate electrodes (double gates) 87 and 89 are connected to the load M on the semiconductor substrate 81.
It is connected to the source / drain region of OSFET t ₂₁ .

Further, a contact hole 92 is formed in the insulating films 86, 90, 91 and the polycrystalline semiconductor film 88 on the gate electrode 83 straddling the selective oxide film 82, and inside the contact hole 92, the inner surface and the bottom portion thereof are formed. A conductive film 93 having a U-shaped cross section is formed along. This allows
The gate electrode 83 of the driving MOSFET t ₁₁ and the load MO
One of the source / drain regions of the SFET t ₂₂ will be connected.

Further, the impurity introduction layer 85 in the active region X connected to the end of the gate electrode 83 of the driving MOSFET t _11.
Is the source / drain region 9 of the transfer MOSFET t _31.
4,95 connected to one of the transfer MOSFETs
The gate electrode 96 of ₃₁ is formed on the semiconductor substrate 81 via a gate insulating film.

Reference numeral 97 indicates an insulating film which covers the SRAM cell region Y and the peripheral circuit region Z. by the way,
As described above, the load MOSFET t ₂₂ includes the two gate electrodes 87 and 89 formed above the semiconductor substrate 81.
Since it has a multi-layer structure with the semiconductor film 88 and
The RAM cell area Y is considerably higher than the peripheral circuit area Z, and a step d is formed at the boundary portion thereof.

Then, in order to reduce the step d,
As shown in FIG. 8 (b), a single BPSG film 97 is formed on the entire surface, and this is heated and melted.

[0011]

However, the planarization is not sufficient by such a method, and the height of the SRAM cell tends to increase more and more. For example, as shown in FIG. 9 (a), a capacitor Q may be formed on the load MOSFET t _{22 as} a countermeasure against the α-ray soft error, and in this case, the step is not sufficiently reduced.

In the capacitor Q, as shown in FIG. 9A, the conductive film 93 for connecting the gate electrode 83 of the driving MOSFET t ₁₁ and the source / drain region of the load MOSFET t ₂₂ is further raised, A fin-shaped storage electrode SN is formed there, the surface thereof is covered with a dielectric film DL, and a counter electrode CP is formed thereon.

When the step d is large as described above, the SR
Photoresist 9 used when simultaneously forming contact holes in the AM cell region Y and the peripheral circuit region Z, and when forming a wiring pattern passing through those regions Y and Z.
In the exposure of 8, the depth of focus becomes smaller than the step d,
The pattern accuracy may decrease.

The present invention has been made in view of the above problems, and a semiconductor device capable of further improving the flatness of the memory cell region and the peripheral circuit region and improving the pattern accuracy, and a method of manufacturing the same. The purpose is to provide.

[0015]

[Means for Solving the Problems]
As illustrated in FIG. 4, a peripheral area B having an uppermost surface lower than the uppermost surface of the memory cell area A, and a memory cell area lower than the uppermost surface of the memory cell area A. A film 26 having a strip-shaped pattern formed in a boundary region C between A and the peripheral circuit region B and a film 26 laminated on the uppermost surface of the peripheral circuit region B and covering the strip-shaped pattern film 26 with an edge portion. This is achieved by a semiconductor device including a first insulating film 28 and a second insulating film 31 that covers the entire first insulating film 28, the memory cell region A, and the boundary region C.

Alternatively, the strip-shaped film 26 is formed of either polycrystalline silicon or a silicon nitride film, and the first insulating film 28 and the second insulating film 31 are
This is achieved by a semiconductor device characterized by being formed of a silicon oxide film containing impurities.

Alternatively, the memory cell region A has a pattern of conductor films 4, 8, 10, 11, 12 formed of a plurality of layers, and the peripheral circuit region B has a pattern larger than that of the memory cell region A. This is achieved by a semiconductor device characterized in that a pattern of the conductor film 22 having a smaller number of layers exists.

Alternatively, a step of forming a memory cell in the first region A of the semiconductor substrate 1 and a peripheral circuit 19 lower than the memory cell in the second region B, and an etching stopper film 26 are grown on the entire surface. After that, a step of selectively removing the etching stopper film 26 on the peripheral circuit 19 and, after growing the first insulating film 28 on the entire surface, the edge portion of the etching stopper film 26 and the peripheral circuit 19
A step of forming a mask 29 having a pattern overlapping with the first insulating film 28 on the first insulating film 28, and etching the first insulating film 28 exposed from the mask 29 to remove the etching stopper in the first region A. A step of exposing the film 26, a step of selectively removing the etching stopper film 26 exposed except a portion overlapping the first insulating film 26, and a step of entirely removing the mask 29 with the mask 29 removed. And a step of laminating the second insulating film 31. This is achieved by a method for manufacturing a semiconductor device.

Alternatively, the etching stopper film 26
Is achieved by a method of manufacturing a semiconductor device, which is made of either polycrystalline silicon or a silicon nitride film. Alternatively, the first insulating film 28 and the second insulating film 31 are formed by a silicon oxide film containing impurities, which is achieved by a method of manufacturing a semiconductor device.

[0020]

According to the present invention, the first insulating film 28 is formed only on the peripheral circuit 19 lower than the memory cell, and the second insulating film 28 is formed on the first insulating film 28 and the memory cell. 31 are stacked.

Therefore, in the peripheral circuit region B, the first insulating film 2 is formed.
8 increases the height, and there is almost no difference in height from the memory cell. Moreover, since the second insulating film 31 is formed in the memory cell region A and the peripheral circuit region B and flattens these regions, the thickness of the resist applied on the second insulating film 31 is uniform. Turn into.

As a result, the problem of the depth of focus of exposure in the case of forming a pattern that crosses both regions while contacting the lower layer in both regions A and B is solved, and the pattern accuracy is improved.

Further, since the etching stopper film 26 exists in a band shape only in the boundary region C and does not exist in the through hole of the peripheral circuit 19, the etching stopper film 26 does not project in the through hole. There is no shape abnormality.

Further, when the first insulating film 28 is removed from the memory cell region A, the underlying film is excessively removed because the etching stopper film 26 exists immediately below the removed portion. Nor.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 4 are cross-sectional views showing a manufacturing process of an embodiment of the present invention, showing a MOSFET surrounded by a broken line of the SRAM cell shown in FIG. 7 and a part of a peripheral circuit.

In FIG. 1A, reference numeral 1 is a semiconductor substrate made of silicon, and a plurality of active regions 3 partitioned by a selective oxide film 2 are provided in a memory cell region A of the semiconductor substrate. A peripheral circuit area B surrounds the area.

In the active area 3 of the memory cell area A, as shown in FIG.
A driving MOSFET t ₁₁ and a transfer MOSFET t ₃₁ are formed in the SRAM shown in FIG. The driving MOSFE
The gate electrode 4 of Tt ₁₁ is formed on the semiconductor substrate 1 in the active region 3 via the gate insulating film 5, and one end of the gate electrode 4 straddles the selective oxide film 2 and is adjacent to the n-type impurity in the active region 3. It is connected to the introduction layer 6. Further, in the active region 3 on both sides of the gate electrode 4, an n-type source / drain layer (not shown) is formed.

On the other hand, a ground line 8 is formed on the SiO ₂ film 7 covering the gate electrode 4 of the driving MOSFET t ₁₁ , and a load MOSFET is further formed on the ground line 8 via the SiO ₂ film 9.
t ₂₂ is formed.

The load MOSFET t ₂₂ is composed of a lower gate electrode 10, a polycrystalline silicon film 11 and an upper gate electrode 12, and the insulating film 1 is provided between these films.
3, 14 are formed, and the polycrystalline silicon film 11 thereof is formed.
Is provided with a p-type source / drain region and a channel region.

Two gate electrodes (double gate) 1
0 and 12 are other load MOSFETs having the same structure.
It is connected to the p-type source / drain region (not shown) of Tt ₂₁ .

Further, contact holes are formed in the SiO ₂ films 7, 9, 13, 14 and the polycrystalline silicon film 11 on the gate electrode 13 of the driving MOSFET t ₁₁ which straddles the selective oxide film 2 at the boundary between the active regions 3. 15 is formed, and
In the contact hole 15, a conductive film 16 having a U-shaped cross section is formed along the inner surface and the bottom of the contact hole 15, whereby the gate electrode 4 of the driving MOSFET t ₁₁ and the load MOSFE.
The polycrystalline silicon film 11 to be the source / drain region of Tt ₂₂ is connected.

On the other hand, the impurity introduction layer 16 in the active region 3 connected to the tip of the gate electrode 4 of the driving MOSFET t _11.
Is a MOSFET used as a transmission
It is connected to one of the n-type source / drain layers 17 and 18 of t ₃₂ .

A part of the SRAM cell is formed by the above laminated structure, and a peripheral circuit 19 which is partially omitted in the drawing is formed around the memory cell area A.

In the figure, reference numeral 20 is a transfer MOSFET formed on the semiconductor substrate 1 via a gate insulating film.
A gate electrode 21 at t ₃₂ is a MOSFET having a gate electrode 22 and source / drain layers 23 and 24 formed on the semiconductor substrate 1 in the peripheral circuit region B.

Next, a process after forming the upper gate electrode 12 of the above load MOSFET t ₂₂ will be described.
First, a SiO ₂ film 25 by a CVD method on the entire thickness of 100 nm, the memory cell region A by the SiO ₂ film 25
And covers the entire peripheral circuit 19.

Next, as shown in FIG. 1 (b), after a polycrystalline silicon film 26 is grown to 100 nm by the CVD method, a resist 27 is applied, and this is exposed and developed, and the memory cell region A and its boundary are formed. A pattern covering only the region C is formed.

Subsequently, the polycrystalline silicon film 26 exposed from the resist 27 is selectively removed by plasma etching using a mixed gas of CF ₄ and O ₂ , and then the resist 27 is peeled off. The state becomes as shown in (a).

Thereafter, BPSG is entirely formed by the CVD method.
A (boro-phospho silicate glass) film 28 is grown. In this case, the thickness of the BPSG film 28 is the height difference between the SiO ₂ film 25 covering the memory cell region A and the peripheral circuit 19, for example, 50.
It is about 0 nm.

Next, as shown in FIG. 2B, the resist 2
9 is applied, and this is exposed and developed to form a pattern covering the region from the peripheral circuit 19 to the upper peripheral portion of the polycrystalline silicon film 26.

Then, as shown in FIG. 2C, the BPSG film 28 exposed from the resist 29 using hydrofluoric acid or the like.
To remove. At this time, since the polycrystalline silicon film 26 in the memory cell region A functions as an etching stopper film,
The underlying SiO ₂ film 25 is not etched.

In this case, a reactive ion etching method may be used, but in that case, sufficient over-etching is performed so that no residue remains on the step portion or the like at the peripheral edge of the memory cell region. This is because, in the etching process described later, the residue serves as a mask for the polycrystalline silicon film 2
This is to prevent 6 from remaining in an undesired place.

Subsequently, as shown in FIG. 3A, the polycrystalline silicon film 26 is removed by plasma etching using the resist 29 as a mask. In this case, if a mixed gas of CF ₄ and O ₂ is used as the etching gas, the SiO ₂ film 25 under the polycrystalline silicon film 26 will not be removed.

Next, as shown in FIG. 3B, the resist 29 is peeled off. By the way, in the boundary area C, BPSG
The polycrystalline silicon film 26 remains below the edge of the film 28, and its planar shape is a band-like pattern surrounding the memory cell region A as shown in FIG. It does not adversely affect the process.

On the other hand, the SiO ₂ film 25 covering the memory cell area A
Is almost the same as the height of the BPSG film 28 in the peripheral circuit region B, but the recess 30 is formed in the boundary region C between the memory cell region A and the peripheral circuit region B or in the memory cell region A. It is not completely flat.

Therefore, the second BP is entirely formed by the CVD method.
The SG film 31 is formed to a thickness of 400 nm, and then 850
When heat treatment is performed at 30 ° C for 30 minutes and reflow is performed, the recess 30
A second BPSG film 31 is filled inside. As a result,
The second BPSG film 31 is completely flattened as shown in FIG. 4A, and there is no step between the memory cell region A and the peripheral circuit 19.

Next, contact holes for connecting wirings are formed in the memory cell region A and the peripheral circuit 19. In this case, a resist 32 is applied on the second BPSG film 31, and this is exposed and developed to form a mask pattern, but there is no unevenness or steps on the upper surface of the second BPSG film 31. Therefore, when the resist 32 is exposed, the focus is not defocused, and an accurate pattern is formed.

After this, using the resist 32 as a mask,
The BPSG film 2 in the memory cell area A or the peripheral circuit 19
Contact holes 33 and 34 are formed by opening the openings 8 and 31 and the SiO ₂ film 25 thereunder, and then metal wirings 35 and 36 made of tungsten that pass through the contact holes 33 and 34.
To form.

It is difficult to wire-bond this tungsten, and since the resistance of tungsten is higher than that of aluminum and the resistance of long-distance wiring is high, the whole of the metal wiring 35, 36 is formed after it is formed. Is covered with an interlayer insulating film such as PSG, then a via hole is formed, and an aluminum wiring is formed, thereby performing well-known two-layer metal wiring.

Although a polycrystalline silicon film is used as the etching stopper film 26 in the above-mentioned embodiments, it may be a silicon nitride film. By the way, in the above-mentioned embodiment, as shown in FIG. 2A, the etching stopper film 26 is removed from the peripheral circuit 19 and left only in the memory cell region A and the boundary region C. The reason is as follows. Describe.

That is, assuming that the etching stopper film 26 is left on the peripheral circuit 19, the etching stopper film 26 is located below the BPSG film 28 covering the peripheral circuit 19, which is the final result. Will not be removed.

Therefore, when forming a contact hole in the peripheral circuit 19, first, as shown in FIG.
Using the resist 32 as a mask, the BPSG films 28, 31 and the etching stopper film 26 and the SiO ₂ film 25 thereunder are etched to form a contact hole 33, and the source / drain layer 23 thereunder is exposed.

After this etching, since the native oxide film 37 as shown in FIG. 6B is formed on the surface of the source / drain layer 23, the native oxide film 37 is removed by using hydrofluoric acid. . At that time, the BPSG films 28 and 31 and the SiO ₂ film 25 are laterally etched, but the etching stopper film 26 having a small etching rate is projected into the contact hole 33 as shown in FIG. 6C. Become.

If the wiring material is sputtered into the contact hole 33 in such a state, the coverage becomes poor and the wire breaks. From the above, inconvenience will occur if the etching stopper film 26 is simply laminated. Therefore, as shown in FIG.
Therefore, it is necessary to remove the etching stopper film 26 located at.

Also, in the case where a capacitor as a countermeasure against α-ray soft error as shown in FIG. 9 is provided as the structure of the SRAM cell, the formation of the etching stopper film 26 to the second BPSG film 31 is performed as described above. The same result can be obtained by applying the steps up to the stacking.

[0055]

As described above, according to the present invention, the first insulating film is formed only on the peripheral circuit lower than the memory cell and the second insulating film is formed on the first insulating film and the memory cell. Since the insulating films are stacked, the height of the peripheral circuit region is increased by the first insulating film, and the height difference from the memory cell is almost eliminated. Moreover, since the second insulating film is formed in the memory cell region and the peripheral circuit region and flattens those regions, the thickness of the resist applied on the second insulating film can be made uniform.

As a result, the problem of the depth of focus of exposure when forming a pattern that crosses both regions while contacting the lower layer in both of these regions is solved, and the pattern accuracy can be improved.

Further, since the etching stopper film exists in a band shape only in the boundary region and does not exist in the through hole of the peripheral circuit, the etching stopper film does not laterally project in the through hole. It is possible to prevent the abnormal shape.

Further, when the first insulating film is removed from the memory cell region, the etching stopper film is present immediately below the removed portion, so that the underlying film can be prevented from being excessively etched.

[Brief description of drawings]

FIG. 1 is a sectional view (1) showing a manufacturing process of an embodiment of the present invention.

FIG. 2 is a sectional view (No. 2) showing the manufacturing process of the embodiment of the present invention.

FIG. 3 is a sectional view (3) showing the manufacturing process of the embodiment of the present invention.

FIG. 4 is a cross-sectional view (4) showing the manufacturing process of the embodiment of the present invention.

FIG. 5 is a plan view showing an etching stopper film remaining around the SRAM cell region in one embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a state where an etching stopper film in a peripheral circuit region is not removed in one embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of an SRAM cell.

FIG. 8 is a cross-sectional view showing a first conventional example.

FIG. 9 is a sectional view showing a second conventional example.

[Explanation of symbols]

1 semiconductor substrate 2 selective oxide film 3 active region 4 gate electrode 5 gate insulating film 6 impurity introduction layer 7, 9 SiO ₂ film 10 lower gate electrode 11 polycrystalline silicon film (semiconductor film) 12 upper gate electrode 13, 14 SiO ₂ film 15 Contact hole 16 Conductive film 17, 18 Source / drain layer 19 Peripheral circuit 25 SiO ₂ film 26 Polycrystalline silicon film (etching stopper film) 27, 29, 32 Resist 28, 31 BPSG film 33, 34 Contact hole 35 , 36 Metal wiring

Claims (6)

[Claims] 1. A peripheral region (B) having an uppermost surface lower than the uppermost surface of the memory cell region (A), and a lower region lower than the uppermost surface of the memory cell region (A). A strip-shaped film (26) formed in a boundary region (C) between the memory cell region (A) and the peripheral circuit region (B), and laminated on the uppermost surface of the peripheral circuit region (B), and A first insulating film (28) having a shape that covers the strip-shaped film (26) with an edge portion, the first insulating film (28), and the memory cell region (A)
And a second insulating film (3) covering the entire boundary region (C).
1) A semiconductor device comprising: 2. The strip-shaped film (26) is formed of either polycrystalline silicon or a silicon nitride film, and the first insulating film (28) and the second insulating film (31).
The semiconductor device according to claim 1, wherein is formed of a silicon oxide film containing impurities. 3. The memory cell area (A) has a pattern of conductor films (4, 8, 10, 11, 12) formed of a plurality of layers, and the peripheral circuit area (B) has a pattern. 3. The semiconductor device according to claim 1, wherein a pattern of the conductor film (22) having a smaller number of layers than the memory cell region (A) is present. 4. A step of forming a memory cell in a first region (A) of a semiconductor substrate (1) and forming a peripheral circuit (19) lower than the memory cell in the second region (B), After the etching stopper film (26) is grown on the entire surface,
A step of selectively removing the etching stopper film (26) on the peripheral circuit (19); and, after growing a first insulating film (28) on the entire surface, an edge of the etching stopper film (26). Section and the peripheral circuit (1
Forming a mask (29) having a pattern overlapping with 9) on the first insulating film (28); and exposing the first insulating film (2) exposed from the mask (29).
8) etching away to expose the etching stopper film (26) in the first region (A), and the etching stopper exposed at a portion other than the portion overlapping the first insulating film (26). A method of manufacturing a semiconductor device, comprising: a step of selectively removing the film (26); and a step of laminating a second insulating film (31) over the entire surface in a state where the mask (29) is peeled off. . 5. The method of manufacturing a semiconductor device according to claim 4, wherein the etching stopper film (26) is either polycrystalline silicon or a silicon nitride film. 6. The first insulating film (28) and the second insulating film (31) are formed of a silicon oxide film containing impurities, according to claim 4 or 5. Manufacturing method of semiconductor device.