KR100266279B1 - A method of fabricating semiconductor memory - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is to prevent a contact-not-open in forming a storage node contact hole and a metal contact hole, and improve a misalign margin between the storage node contact hole and the metal contact hole. CONSTITUTION: The first insulating layer(106) is formed on a semiconductor substrate(100) having a cell array region and a peripheral circuit region. A pad contact hole is formed by etching the first insulating layer. A conductive layer pad(110b) is formed by fill the pad contact hole with a conductive layer. The second insulating layer(112a) is formed on the first insulating layer. A bit line(114') is formed on the second insulating layer. After removing the second insulating layer except for the lower part of the bit line by an etch-back process, The third and fourth insulating layers(118, 120) are formed in this order on the entire surface of the semiconductor substrate. A storage node contact hole is formed at the cell array region by etching the third and fourth insulating layers. A metal contact hole is formed at the periphery circuit region by etching the fourth and third insulating layer and the first insulating layer.

Description

A method of fabricating semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to manufacturing a semiconductor memory device which improves a problem of contact formation due to a difference in etch rate of an insulating layer. It is about a method.

1 is a layout of a semiconductor memory device for explaining the conventional manufacturing method and the manufacturing method of the present invention.

Referring to FIG. 1, a layout of a cell array region of a semiconductor memory device includes a plurality of gate polys GP1 to GP4 and a plurality of bit lines BL1 to BL3. It includes. And a bit line contact BT and a storage node contact ST.

FIG. 2 is a cross-sectional view of a conventional semiconductor memory device taken along the line X-X 'of FIG. 1.

Referring to FIG. 2, in the method of forming a storage node contact in a cell array region of a conventional semiconductor memory device, a device isolation film 12 is formed on a semiconductor substrate 10, and the semiconductor device includes the device isolation film 12. The first insulating layer 14 is formed on (10).

A poly pad 16 is formed to penetrate the first insulating layer 14 and to be electrically connected to the semiconductor substrate 10 between the device isolation layers 12.

The first insulating layer 14 and the poly pad 16 are formed to have a flattened top surface.

A second insulating layer 18, which is a bit line lower insulating layer 18, is formed on the poly pad 16 and the first insulating layer 14.

The third and fourth insulating layers 22 and 24 are sequentially formed on the second insulating layer 18 including the bit line 20 and the bit line 20 formed on the second insulating layer 18. do.

The bit line 20 is, for example, a multilayer film in which a polysilicon film 20a, a tungsten silicide 20b, and an anti-reflective coating 20c are sequentially stacked.

The second to fourth insulating layers 18, 22, and 24 are etched to form storage node contact holes 26 to expose a portion of the poly pad 16.

As the first and third insulating layers 14 and 22 and the fourth insulating layer 24, a BOSG (BoroPhosphoSilicate Glass) film is generally used.

However, a high temperature oxide (HTO) film having a smaller etching rate than the BPSG film is used as the second insulating layer 18.

The reason why the HTO film is used as the bit line lower insulating layer 18 is as follows.

When the gate electrode and the bit line of the peripheral region are to be electrically connected to each other, the contact resistance may be kept constant when the poly of the bit line is directly in contact with the poly of the gate electrode.

Since the gate electrode is formed of a double structure of poly and tungsten silicide, a tungsten silicide removal process of a contact portion is required.

The tungsten silicide removal process is generally carried out using a chemical for tungsten silicide etching. During the tungsten silicide removal process, the HTO layer serves as an etch stop layer of the BPSG layer underneath.

However, as the HTO layer is used as the bit line lower insulating layer 18, as shown by reference numeral 28 when the storage node contact hole 26 is formed, a slope occurs due to the difference in etching rates of different insulating layers. do. The HTO film has a relatively slow etching rate.

The etching slope decreases the area of the contact region, and thus increases the contact resistance. It also gives the possibility of contact not open phenomenon.

3 is a cross-sectional view illustrating a metal contact of a conventional semiconductor memory device.

In FIG. 3, in the method of forming a metal contact in a peripheral circuit region of a conventional semiconductor memory device, a transistor 30 is formed on a semiconductor substrate 10, and the semiconductor substrate 10 includes the transistor 30. First to fourth insulating layers 14, 18, 22, and 24 are sequentially formed on the substrate.

The metal contact hole 32 is formed to penetrate the first to fourth insulating layers 14, 18, 22, and 24 to expose a portion of the semiconductor substrate 10 between the transistors 30.

Similar to the storage node contact hole 26, the metal contact hole 32 also has an abrupt inclination, as indicated by reference numeral 34 at the interface of the insulating layer having different etching rates. This causes a problem of failing during subsequent barrier film formation and filling of a conductive film such as tungsten. In addition, the steep inclination poses a risk of contact sick opening.

In order to prevent opening of the contact sickle, the critical dimension of the contact must be increased. However, increasing the line width of the contact causes a problem that the space margin a between the metal contact hole 32 and the transistors 30 on both sides thereof becomes weak.

The present invention has been proposed to solve the above-described problems, and can prevent a failure such as a contact sick opening phenomenon when forming a storage node contact hole and a metal contact hole, and can improve misalignment margin between the metal contact and the gate electrode. It is an object of the present invention to provide a method for manufacturing a semiconductor device.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of unifying an insulating layer of a storage node contact hole and a metal contact hole forming portion.

1 is a layout of a semiconductor memory device for explaining a conventional manufacturing method and a manufacturing method of the present invention;

FIG. 2 is a cross-sectional view of a conventional semiconductor memory device taken along the line X-X 'of FIG. 1; FIG.

3 is a cross-sectional view showing a metal contact of a conventional semiconductor memory device;

4 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention taken along the line X-X 'of FIG.

5A through 5D are cross-sectional views taken along the line Y-Y 'of FIG. 1 to illustrate a method of manufacturing a semiconductor memory device according to an embodiment of the present invention;

6A through 6D are cross-sectional views taken along the line Z-Z 'of FIG. 1 to illustrate a method of manufacturing a semiconductor memory device according to an embodiment of the present invention;

7A to 7D are cross-sectional views of a peripheral circuit region for explaining a method of manufacturing a semiconductor memory device according to an embodiment of the present invention;

8 is a cross-sectional view illustrating a metal contact of a semiconductor memory device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

GP1 to GP4: Gate poly BL1 to BL3: Bit line

BT: Bitline contact ST: Storage node contact

10, 100: semiconductor substrate 12, 102: device isolation film

14, 106: first insulating layer 16: poly pad

18, 112: second insulating layer 20, 114: bit line

22, 118: third insulating layer 24, 120: fourth insulating layer

26, 122: storage node contact hole 30, 104: transistor

32, 126: metal contact hole 108: pad contact hole

110: conductive film pad 113: bit line contact hole

(Configuration)

According to the present invention for achieving the above object, a method of manufacturing a semiconductor memory device comprises the steps of: forming a first insulating layer on a semiconductor substrate; Etching the first insulating layer to form a pad contact hole; Filling the pad contact hole with a conductive film to form a conductive film pad; Forming a second insulating layer on the first insulating layer, including the conductive film pad, and forming a material having an etch selectivity with respect to the first insulating layer; Forming a bit line on the second insulating layer; Removing a second insulating layer on both sides of the bit line; Sequentially forming a third insulating layer and a fourth insulating layer of a material having the same etching rate as that of the first insulating layer on the entire surface of the semiconductor substrate including the bit line; Etching the fourth and third insulating layers to form a storage node contact hole to expose a portion of the conductive film pad.

In a preferred embodiment of this method, the first and third insulating layers and the fourth insulating layer material are BPSG.

In a preferred embodiment of this method, the second insulating layer material is HTO.

According to the present invention for achieving the above object, a method of manufacturing a semiconductor memory device comprises the steps of: forming a first insulating layer on a semiconductor substrate; Etching the first insulating layer to form a pad contact hole; Filling the pad contact hole with a conductive film to form a conductive film pad; Forming a second insulating layer on the first insulating layer, including the conductive film pad, and forming a material having an etch selectivity with respect to the first insulating layer; Forming a bit line on the second insulating layer and patterning a multilayer film having a conductive layer and an anti-reflection layer sequentially formed thereon; Etching and removing the second insulating layers on both sides of the bit line by a front etch back process; Removing the anti-reflection layer by the etch back process and sequentially forming a third insulating layer and a fourth insulating layer of a material having the same etching rate as that of the first insulating layer on the entire surface of the semiconductor substrate including the bit line; Etching the fourth and third insulating layers to form a storage node contact hole to expose a portion of the conductive film pad.

In a preferred embodiment of this method, the first and third insulating layers and the fourth insulating layer material are BPSG.

In a preferred embodiment of this method, the second insulating layer material is HTO.

In a preferred embodiment of the method, the removal of the antireflective layer compensates for the bit line step resulting from the second insulating layer etch.

According to the present invention for achieving the above object, a method of manufacturing a semiconductor memory device comprises the steps of forming an isolation layer by defining an active region and an inactive region on a semiconductor substrate having a cell array region and a peripheral circuit region; Forming a transistor having a gate electrode in an active region of the cell array region; Forming a first insulating layer over the semiconductor substrate including the transistor; Etching a first insulating layer of the cell array region to form a pad contact hole; Filling the pad contact hole with a conductive film to form a conductive film pad; Forming a second insulating layer on the first insulating layer, including the conductive film pad, and forming a material having an etch selectivity with respect to the first insulating layer; Forming a bit line on the second insulating layer of the cell array region, by patterning a multilayer film having a conductive layer and an anti-reflection layer sequentially; Removing a second insulating layer on both sides of the bit line and the peripheral circuit region by a front etch back process; Removing the anti-reflection layer by the etch back process and sequentially forming a third insulating layer and a fourth insulating layer of a material having the same etching rate as that of the first insulating layer on the entire surface of the semiconductor substrate including the bit line; Etching the fourth and third insulating layers to form a storage node contact hole to expose a portion of the conductive pad; Etching the fourth and third and first insulating layers to form a metal contact hole to expose a portion of the semiconductor substrate between the gate electrodes of the peripheral circuit region.

In a preferred embodiment of this method, the first insulating layer, the third insulating layer, and the fourth insulating layer are formed of a material having the same etching rate.

In a preferred embodiment of this method, the first and third insulating layers and the fourth insulating layer material are BPSG.

In a preferred embodiment of this method, the second insulating layer material is HTO.

In a preferred embodiment of the method, the removal of the antireflective layer compensates for the bit line step resulting from the second insulating layer etch.

(Action)

In the method of manufacturing a semiconductor device according to the present invention, the insulating layers of the storage node contact holes and the metal contact hole forming portions are unified, thereby preventing contact sickness opening due to the etching rate of different insulating layers, and margin of misalignment between the metal contacts and the gate electrodes. To improve.

(Example)

4 and 8, a method of manufacturing a novel semiconductor memory device according to an embodiment of the present invention includes a first insulating layer 106 formed on a semiconductor substrate 100 having a cell array region and a peripheral circuit region. To form a pad contact hole. The pad contact hole is filled with a conductive film to form a conductive film pad 110b, and a second insulating layer having an etch selectivity with a first insulating layer material on the first insulating layer 106 including the conductive film pad 110b. Form layer 112. The bit line 114 is formed on the second insulating layer 112 in the cell array region. The second insulating layer 112 except for the lower portion of the bit line 114 is removed by a front etch back process. The third insulating layer 118 and the fourth insulating layer 120 are sequentially formed on the entire surface of the semiconductor substrate 100 including the bit line 114 ′, and are etched to form storage node contact holes 122 in the cell array region. To form. The fourth and third insulating layers 120 and 118 and the first insulating layer 106 are etched to form metal contact holes 126 in the peripheral circuit region. In this method of manufacturing a semiconductor memory device, the contact sickle opening phenomenon and the conductive film filling by the insulating layers having different etching rates are made by unifying the types of the insulating layers of the bit line contacts, the storage node contacts, and the metal contact forming regions. Fail can be prevented, and thus the size of the contact can be reduced, and the misalignment margin between the metal contact and the gate electrode can be improved. In addition, the step difference of the metal contact in the peripheral circuit region can be reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 4 to 8.

In Figs. 5 to 8, the same reference numerals are given to components having the same functions as the components of the semiconductor memory device shown in Fig. 4.

4 is a cross-sectional view of a semiconductor memory device according to an exemplary embodiment of the present invention taken along the line X-X 'of FIG. 1.

Referring to FIG. 4, in the method of forming a storage node contact according to an exemplary embodiment of the present invention, a device isolation layer 102 is formed on a semiconductor substrate 100 and the device isolation layer 102 includes the semiconductor substrate 100. The first insulating layer 106 is formed on it.

The conductive film pad 110b is formed of a polysilicon film so as to be electrically connected to the semiconductor substrate 100 between the device isolation layer 102 through the first insulating layer 106.

The device isolation layer 102 and the conductive layer pad 110b may be partially overlapped to increase the pad contact hole formation margin.

The first insulating layer 106 and the conductive film pad 110b have a planarized upper surface.

A second insulating layer 112a, which is a bit line lower insulating layer 112a, is locally formed on the first insulating layer 106, and a bit line 114 'is formed on the second insulating layer 112a. do.

The bit line 114 ′ is, for example, a multilayer film in which a polysilicon film 114a and a tungsten silicide film 114b are sequentially stacked.

The third insulating layer 118 and the fourth insulating layer 120 are sequentially formed on the entire surface of the semiconductor substrate 100 including the bit line 114 ′.

The first insulating layer 106, the third insulating layer 118, and the fourth insulating layer 120 are BPSG films used as a general interlayer insulating film, and the second insulating layer 112a is relative to the BPSG film. This is an HTO film having a low etching rate.

The fourth insulating layer 120 and the third insulating layer 118 on the poly pad 110b are etched to form a storage node contact hole 122.

Since the storage node contact holes 122 are formed by etching the fourth and third insulating layers 120 and 118, that is, the BPSG single layer, the storage node contact holes 122 may be formed at a lower portion than the entrance area of the storage node contact holes 122 by a uniform etching rate. There is no problem that the area is drastically small.

5A to 5D are cross-sectional views taken along the line YY ′ of FIG. 1 to explain a method of manufacturing a semiconductor memory device according to an embodiment of the present invention, and FIGS. 6A to 6D are semiconductors according to an embodiment of the present invention. FIG. 1 is a cross-sectional view taken along the line ZZ 'of FIG. 1 to explain a method of manufacturing a memory device.

5A and 6A, a method of manufacturing a semiconductor memory device according to an embodiment of the present invention includes a device isolation film 102 and a transistor 104a in a cell array region in a conventional manner on a semiconductor substrate 100. ).

The transistor 104a includes, for example, a gate electrode layer in which a polysilicon film, a tungsten silicide film, and a silicon nitride film are sequentially stacked, and a gate electrode composed of a silicon nitride film spacer.

The first insulating layer 106, which is an interlayer insulating layer, is formed on the entire surface of the semiconductor substrate 100 including the transistor 104a. The first insulating layer 106 is, for example, a BPSG film.

The first insulating layer 106 is etched to form pad contact holes 108a and 108b to expose the semiconductor substrate 100 between the device isolation layer 102 and the transistor 104a, respectively.

In particular, the pad contact hole 108b of FIG. 6A is formed by a self-aligned contact (SAC) method.

5B and 6B, the pad contact holes 108a and 108b are filled with a conductive film such as a polysilicon film to form the conductive film pads 110a and 110b.

The first insulating layer 106 and the conductive film pads 110a and 110b are formed to have a top surface planarized by a planarization etching process such as chemical mechanical polishing (CMP).

A second insulating layer 112 is formed on the first insulating layer 106 including the conductive film pads 110a and 110b, but has an etch selectivity with the first insulating layer 106. The substance is formed of, for example, HTO.

5C and 6C, the second insulating layer 112 is etched to form bit line contact holes 113a and 113b to expose a portion of the conductive pads 110a and 110b. The multilayer layer including the bit line contact holes 113a and 113b and the bit line forming conductive layers 114a and 114b and the anti-reflection film 114c are sequentially stacked on the second insulating layer 112.

The conductive layers 114a and 114b are, for example, a multilayer film in which a polysilicon film and a tungsten silicide film are stacked, and the antireflection film 114c is a multilayer film in which a PE-TEOS film and a silicon nitride film (SiON) are stacked.

The conductive layers 114a and 114b and the antireflection film 114c are etched using a photoresist layer pattern (not shown) which is a bit line forming mask. Then, the bit line 114 is formed.

Finally, after removing the photoresist layer pattern, a second etch back process is performed to remove the second insulating layer 112 on both sides of the bit line 114 except for the lower portion of the bit line 114. 5D and 6D, bit line contacts in the cell array region are formed.

The anti-reflection film 114c is removed by the front etch back process so that the step difference caused by the bit line 114 'is maintained similarly as compared with the related art.

7A to 7D are cross-sectional views of a peripheral circuit region for explaining a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 7A, in the method of manufacturing a semiconductor memory device according to an exemplary embodiment of the present invention, a device isolation film 102 and a transistor 104b are formed on a semiconductor substrate 100 by a conventional method in a peripheral circuit region. do.

The first insulating layer 106 is formed on the semiconductor substrate 100 including the transistor 104b by, for example, BPSG.

In FIG. 7B, the second insulating layer 112 is formed of a material having an etching selectivity with the first insulating layer 106, for example, HTO, on the first insulating layer 106.

Referring to FIG. 7C, the second insulating layer 112 and the first insulating layer 106 are etched to form a bit line contact hole 113c to expose a portion of the semiconductor substrate 100.

A multilayer film including a bit line forming conductive layer and an anti-reflection film is sequentially formed on the second insulating layer 112 including the bit line contact hole 113c.

The multilayer film is patterned using a photoresist film pattern (not shown) to form a bit line in the same manner as the bit line forming method of the cell array region.

In addition, when the second etch back process is performed to remove all of the second insulating layers 112 except for the second insulating layer 112a formed under the bit line 114, as shown in FIG. Bit line contacts in the circuit area are formed.

The anti-reflection film 114c is removed by the front etch back process so that the step difference caused by the bit line 114 'is maintained similarly as compared with the related art.

As shown in FIG. 4, when the storage node contact hole 122 is formed in a subsequent process by removing the second insulating layer 112 on both sides of the bit line 114, a unitary insulating layer structure may be formed. As a result, it is possible to form the storage node contact hole 122 having no sharp inclination.

8 is a cross-sectional view illustrating a metal contact of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 8, in the method of forming a metal contact in a peripheral circuit region of a semiconductor memory device according to an exemplary embodiment of the present invention, a transistor 104c is formed on a semiconductor substrate 100, and the transistor 104c is included. The multilayer insulating layers 106, 118, and 120 are sequentially formed on the semiconductor substrate 100.

The multilayer insulating layers 106, 118, and 120 are etched to form metal contact holes 126 to expose a portion of the semiconductor substrate 100 between the transistors 104c.

The space margin b of the metal contact hole 126 and the transistor 104c is relatively increased in comparison with the related art.

This is possible because the multilayer insulating layers 106, 118, and 120 have the same etching rate, for example, each insulating layer is formed of BPSG.

Since the HTO film in the metal contact hole forming portion is removed by the above-described front etch back process, there is no risk of contact sick opening due to the difference in etching rate of the insulating layer. The HTO film has a relatively slow etching rate than the BPSG film.

In addition, the step of the metal contact is reduced by the removal of the HTO film.

According to the present invention, by unifying the types of the insulating layers of the bit line contacts, the storage node contacts, and the metal contact forming regions, the contact sickle opening phenomenon and the conductive film peeling failure due to the insulating layers having different etching rates can be prevented. The size of the contact can be reduced, and the misalignment margin between the metal contact and the gate electrode can be improved. In addition, there is an effect that can reduce the step difference of the metal contact in the peripheral circuit area.

Claims (12)

Forming a first insulating layer on the semiconductor substrate; Etching the first insulating layer to form a pad contact hole; Filling the pad contact hole with a conductive film to form a conductive film pad; Forming a second insulating layer on the first insulating layer, including the conductive film pad, and forming a material having an etch selectivity with respect to the first insulating layer; Forming a bit line on the second insulating layer; Removing a second insulating layer on both sides of the bit line; Sequentially forming a third insulating layer and a fourth insulating layer of a material having the same etching rate as that of the first insulating layer on the entire surface of the semiconductor substrate including the bit line; Etching the fourth and third insulating layers to form a storage node contact hole to expose a portion of the conductive film pad. The method of claim 1, The first insulating layer, the third insulating layer, and the fourth insulating layer material are BPSG. The method of claim 1, And the second insulating layer material is HTO. Forming a first insulating layer on the semiconductor substrate; Etching the first insulating layer to form a pad contact hole; Filling the pad contact hole with a conductive film to form a conductive film pad; Forming a second insulating layer on the first insulating layer, including the conductive film pad, and forming a material having an etch selectivity with respect to the first insulating layer; Forming a bit line on the second insulating layer and patterning a multilayer film having a conductive layer and an anti-reflection layer sequentially formed thereon; Etching and removing the second insulating layers on both sides of the bit line by a front etch back process; The anti-reflection layer is removed by the etch back process, Sequentially forming a third insulating layer and a fourth insulating layer of a material having the same etching rate as that of the first insulating layer on the entire surface of the semiconductor substrate including the bit line; Etching the fourth and third insulating layers to form a storage node contact hole to expose a portion of the conductive film pad. The method of claim 4, wherein The first insulating layer, the third insulating layer, and the fourth insulating layer material are BPSG. The method of claim 4, wherein And the second insulating layer material is HTO. The method of claim 4, wherein The removal of the anti-reflective layer compensates for the step difference of the bit line according to the etching of the second insulating layer. Forming an isolation layer by defining an active region and an inactive region on a semiconductor substrate having a cell array region and a peripheral circuit region; Forming a transistor having a gate electrode in an active region of the cell array region; Forming a first insulating layer over the semiconductor substrate including the transistor; Etching a first insulating layer of the cell array region to form a pad contact hole; Filling the pad contact hole with a conductive film to form a conductive film pad; Forming a second insulating layer on the first insulating layer, including the conductive film pad, and forming a material having an etch selectivity with respect to the first insulating layer; Forming a bit line on the second insulating layer of the cell array region, by patterning a multilayer film having a conductive layer and an anti-reflection layer sequentially; Removing a second insulating layer on both sides of the bit line and the peripheral circuit region by a front etch back process; The anti-reflection layer is removed by the etch back process, Sequentially forming a third insulating layer and a fourth insulating layer of a material having the same etching rate as that of the first insulating layer on the entire surface of the semiconductor substrate including the bit line; Etching the fourth and third insulating layers to form a storage node contact hole to expose a portion of the conductive pad; Etching the fourth and third and first insulating layers to form metal contact holes to expose a portion of the semiconductor substrate between the gate electrodes of the peripheral circuit region. The method of claim 8, The first insulating layer, the third insulating layer, and the fourth insulating layer are formed of a material having the same etching rate. The method of claim 8, The first insulating layer, the third insulating layer, and the fourth insulating layer material are BPSG. The method of claim 8, And the second insulating layer material is HTO. The method of claim 8, The removal of the anti-reflective layer compensates for the step difference of the bit line according to the etching of the second insulating layer.

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