JPH0555204A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To implant ions after the formation of a field oxide film without using a mask, and to formed a channel stop impurity layer by forming a polysilicon film between a silicon oxide film and a silicon nitride film and increasing the level difference between the surface of a silicon substrate and the surface of the silicon nitride film. CONSTITUTION:A field oxide film 8 is shaped in 5000-7000Angstrom through oxidation in a wet atmosphere at 1000-1050 deg.C, and the field oxide film 8 of the upper section of a silicon substrate 1 is etched in 2000-4000Angstrom through hydrofluoric acid treatment. Boron ions are implanted under the conditions of 100-150KeV and approximately 0.7-2.0X10<13>/cm<2> by utilizing film thickness difference between an insulating film in 5500-7800Angstrom (the composite film of a first silicon oxide film 2, a polysilicon film 3 and a first silicon nitride film 4) and the field oxide film 8 in 1000-3000Angstrom on an active region by forming the field oxide film 8 in 1000-3000Angstrom . A channel stop impurity layer 9 is formed just under the field oxide film 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fine element isolation technique.

[0002]

2. Description of the Related Art FIG. 2 shows a process chart of forming a conventional element isolation region. 1 is a P-type silicon substrate, 2 is a first silicon oxide film, 4 is a first silicon nitride film, 5 is a second silicon oxide film, 6 is a second silicon nitride film, 7 is a third silicon oxide film, and 8 is a field. An oxide film, 9 is a channel stop impurity layer, and 10 is a high concentration N-type diffusion layer.

Next, a conventional element isolation region forming process will be described. First, the first silicon oxide film 2 is formed on the P-type silicon substrate 1 by a thermal oxidation method to a thickness of 500-80.
After forming 0 Å, the first silicon nitride film 4 is deposited to 1000 to 2000 Å and the second silicon oxide film 5 is deposited to 1000 to 2000 Å by the CVD method (FIG. 2A). If the thickness of the first silicon nitride film 4 is too thick, crystal defects occur in the silicon substrate 1, so there is a limit. next,
Patterning for forming an element isolation region is performed using known photolithography and etching techniques, and boron ion implantation is performed for channel stop (FIG. 2B). Next, the second silicon nitride film 6 is deposited to 500 by the CVD method.
~ 1000Å, the third silicon oxide film 7 1000 ~ 20
00Å is deposited (FIG. 2C), the third silicon oxide film 7 and the second silicon nitride film 6 are etched back, and then the second silicon oxide film 5 and the third silicon oxide film 7 are removed by hydrofluoric acid treatment. (FIG.2 (d)). Next, 1000-10
By oxidizing in a wet atmosphere at 50 ° C., the field oxide film 8 is formed to 5000 to 7000Å, and at the same time, the channel stop impurity layer 9 is diffused and redistributed (FIG. 2).
(E)). After that, the high concentration N-type diffusion layer 10 is formed (FIG. 2F).

[0004]

According to the above steps, FIG.
The channel stop impurity layer 9 has a spread as shown in (e), and the channel stop impurity layer 9 is in contact with the high-concentration N-type diffusion layer 10 as shown in FIG.
N-junction is formed. For this reason, the junction breakdown voltage is lowered, and normal element formation becomes impossible.

If the concentration of the channel stop impurity layer 9 is lowered to prevent the junction breakdown voltage from being lowered, the original function as a channel stopper cannot be achieved, and the field inversion voltage is lowered and the punch-through characteristic is deteriorated. .. Therefore, the conventional technique cannot prevent a decrease in junction breakdown voltage and a decrease in inversion voltage and punch-through characteristics at the same time, and it is difficult to form a fine element isolation.

An object of the present invention is to provide a means for simultaneously preventing a decrease in junction breakdown voltage and a decrease in inversion voltage and punch-through characteristics by forming a channel stop impurity layer after forming a field oxide film.

[0007]

According to the method of manufacturing a semiconductor device of the present invention, a silicon oxide film is formed on a semiconductor substrate, then a polysilicon film is formed, and a silicon nitride film and a silicon oxide film are formed on the polysilicon film. A step of forming a film, a step of patterning an element isolation region formation after the step, a step of forming a field oxide film and etching back the field oxide film after the step, and a step of performing the element isolation after the step. A step of forming a channel stopper by implanting ions in the region.

[0008]

By forming a polysilicon film between the silicon oxide film and the silicon nitride film, the step difference between the surface of the silicon substrate and the surface of the silicon nitride film can be increased without increasing the thickness of the silicon nitride film. Since the channel stop impurity layer can be formed by performing ion implantation after the field oxide film is formed without using, the diffusion of the channel stop impurity layer does not occur, and the impurity concentration immediately below the field oxide film layer is high and high. The impurity concentration around the N-type diffusion layer can be set low.

[0009]

The present invention will be described in detail below based on an example. FIG. 1 shows a manufacturing process diagram of an embodiment of the present invention.
1 is a P-type silicon substrate, 2 is a first silicon oxide film, 3 is a polysilicon film, 4 is a first silicon nitride film, 5 is a second silicon oxide film, 6 is a second silicon nitride film, and 7 is a third silicon film. An oxide film, 8 is a field oxide film, 9 is a channel stop impurity layer, and 10 is a high concentration N-type diffusion layer.

Next, the manufacturing process of one embodiment of the present invention will be described. First, using a thermal oxidation method on the P-type silicon substrate 1,
After forming the first silicon oxide film 2 of 500 to 800 Å,
The polysilicon film 3 is set to 4000 to 500 by using the CVD method.
0Å, the first silicon nitride film 4 is 1000 to 2000Å,
A second silicon oxide film 5 is deposited in the order of 1000 to 2000Å (FIG. 1A). Next, using known photolithography and etching techniques, patterning for forming an element isolation region is performed (FIG. 1B). Next, the second using the CVD method
The silicon nitride film 6 and the third silicon oxide film 7 are deposited to 500 to 1000Å and 1000 to 2000Å, respectively (see FIG. 1).
(C)) After that, the third silicon oxide film 7 and the second silicon nitride film 6 are etched back, and then the second silicon oxide film 5 and the third silicon oxide film 7 are removed by hydrofluoric acid treatment (FIG. 1 (d). )). Next, the field oxide film 8 is formed to 5000 to 7000 Å by performing oxidation in a wet atmosphere at 1000 to 1050 ° C., and the field oxide film 8 on the silicon substrate 1 is formed to 20 times by hydrofluoric acid treatment.
By etching from 0 to 4000 Å and setting the field oxide film 8 to 1000 to 3000 Å, 5500 to 7800 Å insulating film (composite of the first silicon oxide film 2, the polysilicon film 3 and the first silicon nitride film 4) on the active region Film thickness) and the field oxide film 8 having a thickness of 1000 to 3000 Å, the boron content is 100 to 150 KeV,
Ion implantation is performed under the condition of about 0.7 to 2.0 × 10 ¹³ / cm ² . As a result, the channel stop impurity layer 9 is formed immediately below the field oxide film 8 (see FIG. 1).
(E)). Next, the first and second silicon nitride films 4 and 6 are removed by hot phosphoric acid treatment, and the polysilicon film 3 and the first silicon oxide film 2 are removed by hydrofluoric acid treatment. After that, the high-concentration N type diffusion layer 10 (MOS type F
Source or drain layer in ET).

[0011]

As described in detail above, by using the present invention, ion implantation for forming a channel stopper is performed after forming a field oxide film, so that diffusion into the active region does not occur unlike the conventional case. Further, due to the difference in the thickness of the insulating film on the element isolation region and on the active region, the ion implantation can be selectively performed just below the element isolation region, so there is no influence on the active region. Further, since the diffusion of the channel stop impurity layer does not occur, the concentration directly under the field oxide film can be set high and the concentration around the high concentration N-type diffusion layer can be set low, so that the junction breakdown voltage does not decrease and the field withstand voltage does not decrease. The inversion voltage and the punch-through breakdown voltage can be increased. Furthermore, since there is almost no effect of seeping into the active region, it is possible to prevent the effective channel width from decreasing.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of an example of the present invention.

FIG. 2 is a manufacturing process diagram of an element isolation region according to a conventional technique.

[Explanation of symbols]

 1 P-type silicon substrate 2 First silicon oxide film 3 Polysilicon film 4 First silicon nitride film 5 Second silicon oxide film 6 Second silicon nitride film 7 Third silicon oxide film 8 Field oxide film 9 Channel stop impurity layer 10 High Concentration N type diffusion layer

Claims (1)

[Claims] 1. A step of forming a silicon oxide film on a semiconductor substrate, then forming a polysilicon film, and forming a silicon nitride film and a silicon oxide film on the polysilicon film, and after the step, an element isolation region. A step of patterning formation, a step of forming a field oxide film after the step, and a step of etching back the field oxide film, and a step of forming a channel stopper by performing ion implantation in the element isolation region after the step. A method of manufacturing a semiconductor device, comprising: