JPH0548088A - Mis transistor - Google Patents

Abstract

PURPOSE:To provide a MIS transistor which can control the injection of hot carriers into a gate insulation film. CONSTITUTION:In a MIS transistor comprising a source region 25 and a drain region 24 formed on a substrate 21, a channel region 32 formed between the source region 25 and drain region 24 and a gate electrode 23 provided near the channel region 32, the cavity regions 28, 29 maintained under the vacuum condition or filled with inactive gas are provided between the substrate 21 and gate electrode 23 covering at least the upper part of the interface 33 of the drain region 24 and channel region 32.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an insulated gate transistor, that is, MIS (Metal-Insulator-Semiconducer).
tor) Transistors, especially those with hot carrier countermeasures.

[0002]

2. Description of the Related Art FIG. 8 is a diagram showing a conventional MIS transistor. In the figure, 1 is a p-type substrate, 2 is this substrate 1
A gate insulating film such as SiO ₂ formed on the gate electrode 3, a gate electrode such as polysilicon formed on the gate insulating film 2,
Reference numerals 4 and 5 denote n-type high-concentration diffusion regions formed on the surface of the substrate 1 on which the gate insulating film 2 is not formed, one of which is a drain region 4 and the other of which is a source region 5.
Further, 6 to 9 are a gate terminal, a drain terminal, a source terminal and a substrate terminal, respectively.

In the above structure, when a positive voltage is applied to the drain terminal 7 to ground the source terminal 8 and the substrate terminal 9 and a voltage exceeding a threshold value is applied to the gate terminal 6, the voltage directly below the gate insulating film 2 is applied. An inversion layer is formed on the surface of the substrate 1, which becomes the channel region 10 and the source-
Current flows between the drains.

[0004]

However, in the above-mentioned conventional MIS transistor, the gate terminal 6 is used.
When a high voltage is applied to the drain terminal 7 and a large amount of hot carriers are generated in the depletion layer near the drain region 4, the portion 11 where the hot carriers are most generated 11
Since the gate insulating film 2 exists above (hereinafter referred to as a hot spot), a part of this hot carrier crosses the barrier at the interface between the substrate and the insulating film and is injected into the gate insulating film 2 above the hot spot 11. There was a phenomenon that was being done. Then, a part of the hot carriers injected into the gate insulating film 2 is trapped in the gate insulating film 2 and becomes a fixed charge, which gradually changes the threshold voltage of the MIS transistor to change its characteristics, and in the long term, There is a problem that the life of the element is shortened. Such a phenomenon is
A DDD (Double Diffused Drain) structure or LDD in which a high electric field near the drain region 4 is relaxed to achieve a high breakdown voltage
The MIS transistor having a (Lightly Doped Drain) structure also has a problem.

An object of the present invention is to provide a MIS transistor which can suppress injection of hot carriers into the gate insulating film.

[0006]

The present invention will be described with reference to FIGS. 1 and 4 showing an embodiment. In the present invention, a source region 25 and a drain region 24 are formed on a substrate 21.
A channel region 32 formed between the source region 25 and the drain region 24, and the channel region 3
2 and a gate electrode 23 provided in proximity to the MI
Applies to S-transistors. And the above-mentioned purpose is
By providing cavity regions 28 and 29 formed between the substrate 21 and the gate electrode 23 and covering at least the boundary portion 33 between the drain region 24 and the channel region 32 and filled with a vacuum or an inert gas. To be achieved.
The invention of claim 2 is the MIS transistor according to claim 1, wherein the cavity region 60 is formed in the gate electrode 23.
It is formed over the entire region sandwiched between the substrate 21 and the substrate 21.

[0007]

When a current flows in the channel region 32, a large amount of hot carriers are generated in the hot spot 33 near the drain region 24, and a part of the hot carriers cross the barrier between the substrate and the insulating film to insulate the gate region near the drain region 24. It is injected into the film 22 and the cavity region 28. At this time, since the cavity region 28 is formed at least at the boundary between the channel region 32 and the drain region 24 side, that is, above the hot spot 33, most of the cavity region 28 is injected into the cavity region 28. The hot carriers injected into the cavity region 28 flow into the gate electrode 23 and the drain region 24 due to the electric field formed inside the cavity region 28 by the gate electrode 23 or the drain region 24.

Incidentally, in the section of means and action for solving the above-mentioned problems for explaining the constitution of the present invention, the drawings of the embodiments are used to make the present invention easy to understand. It is not limited to.

[0009]

EXAMPLES First Example FIG. 1 is a sectional view showing a first example of an MIS transistor according to the present invention. The basic structure of the MIS transistor of this embodiment is almost the same as the above-mentioned conventional example. In the figure, 21 is a p-type substrate, 22 is a gate insulating film formed on this substrate 21, and 23 is a gate insulating film 22. And the gate electrodes 24 and 25 formed on the gate insulating film 22 respectively.
Is an n-type high-concentration diffusion region formed on the surface of the substrate 21 on which no is formed, one of which is a drain region 24 and the other of which is a source region 25. Further, 26 and 27 are a drain electrode and a source electrode, respectively.

The feature of this embodiment is that the gate insulating film 22 above the boundary between the side of the drain region 24 and the substrate 21 and the boundary between the side of the source region 25 and the substrate 21 is removed. That is, the hollow regions 28 and 29 filled with a vacuum or an inert gas are formed. The hollow regions 28 and 29 are surrounded by a relatively thin insulating film 30 and an interlayer insulating film 31 to hermetically seal the inside. The insulating film 30 is formed on the surface of the substrate 21 including the drain region 24 and the source region 25, and the gate insulating film 22.
It is formed so as to cover the side surface and the surface of the gate electrode 23.

The MIS transistor having the structure as shown in FIG. 1 can be manufactured by the following method as an example.

First, a gate insulating film 22 made of SiO ₂ or the like is formed on the surface of the p-type substrate 21, and a gate electrode 23 made of polysilicon or the like is formed on the gate insulating film 22.
Next, using the gate insulating film 22 and the gate electrode 23 as a mask, n-type high concentration diffusion regions 24 and 25 are formed on the surface of the substrate 21 on both sides thereof. Further, the gate insulating film 22
Only the side surface is over-etched to form a gap between the gate electrode 23 and the substrate 21, and then the diffusion region 2
4, the surface of the substrate 21 including 25, and the gate insulating film 22
An insulating film 30 is formed to cover the side surface and the surface of the gate electrode 23. Then, by forming the interlayer insulating film 31 by deposition or the like in a vacuum atmosphere or an inert gas atmosphere, the cavity regions 28 and 29 filled with the vacuum or inert gas can be formed. After that, by forming the drain electrode 26 and the source electrode 27 through the interlayer insulating film 31 and the insulating film 30, the MIS transistor as shown in FIG. 1 can be manufactured.

In the above structure, the source electrode 2
When a positive high voltage is applied to the gate electrode 23 and the drain electrode 26 with 7 and a substrate terminal (not shown) grounded, a current flows to the surface of the substrate 21 immediately below the gate insulating film 22, that is, the channel region 32, and the channel electrons are Due to the high electric field around the drain region 24, it becomes hot electrons (hot carriers), and a part thereof is injected into the gate insulating film 22 and the cavity region 28 in the vicinity of the drain region 24 beyond the energy barrier between the substrate and the insulating film. Alternatively, a large amount of hot carriers are generated near the drain region 24 due to impact ionization with channel electrons, and a part of the hot carriers cross the barrier between the substrate and the insulating film to the gate insulating film 22 or the cavity region 28 near the drain region 24. Injected. At this time, since the cavity region 28 is formed at the boundary between the substrate 21 and the side of the drain region 24, that is, above the hot spot 33, most of the cavity region 28 is injected into the cavity region 28. The hot carriers injected into the cavity region 28 are generated by the electric field generated inside the cavity region 28 by the gate electrode 23 or the drain region 24.
3, flowing to the drain region 24.

Therefore, according to this embodiment, most of the hot carriers that cross the barrier between the substrate and the insulating film are injected into the cavity region 28, so that they are injected into the gate insulating film 22.
The number of fixed hot carriers can be reduced, and fluctuations in device characteristics and device life can be suppressed.

-Modification of First Embodiment- FIG. 2 shows an LDD (Lightly Do) configuration of the first embodiment described above.
FIG. 3 is a cross-sectional view showing an example applied to a MIS transistor having a ped drain structure. In the following description, the same components as those in the above-described first embodiment will be designated by the same reference numerals to simplify the description.

In FIG. 2, 40 is an n-type low concentration diffusion region formed on the side of the drain region 24 on the channel region 32 side, and 41 is an n-type low concentration concentration formed on the side of the source region 25 on the channel region 32 side. These are diffusion regions, and the presence of these n-type low-concentration diffusion regions 40 and 41 alleviates the electric field concentration on the side of the drain region 24, thereby achieving high breakdown voltage and high reliability. Then, a cavity region 28 filled with a vacuum or an inert gas is provided above the low concentration diffusion regions 40, 41.
29 is formed. In addition, in FIG.
Reference numeral 3 is a sidewall formed of SiO ₂ or the like on the side of the gate insulating film 22 and the gate electrode 23.

Therefore, even in the embodiment shown in FIG. 2, it is possible to obtain the same effect as that of the first embodiment.

Next, FIG. 3 shows a DDD configuration of the first embodiment.
It is sectional drawing which shows an example applied to the MIS transistor of a (Double Diffused Drain) structure. In FIG. 3, 5
0 and 51 are the drain region 24 and the source region 25 n
N-type low-concentration diffusion regions formed by the double diffusion method together with the n-type high-concentration diffusion regions. Due to the presence of these n-type low-concentration diffusion regions 50 and 51, the concentration of the electric field on the side of the drain region 24 is relaxed. Withstand voltage and high reliability. Cavity regions 28 and 29 filled with a vacuum or an inert gas are formed above the side portions of the low concentration diffusion regions 50 and 51.

Therefore, even in the embodiment shown in FIG. 3, it is possible to obtain the same effect as that of the first embodiment.

Second Embodiment FIGS. 4 and 5 are views showing a second embodiment of the MIS transistor according to the present invention. FIG. 4 is a sectional view taken along the channel length direction, and FIG. 5 is a channel width direction. It is sectional drawing which followed.

The feature of this embodiment is that the cavity region 60 is formed over the entire region sandwiched between the gate electrode 23 and the substrate 21, that is, in the conventional MIS transistor shown in FIG. 2 is omitted. Therefore, this cavity region 60
Is surrounded by the interlayer insulating film 31 and the field oxide film 61 to hermetically seal the inside. Further, the insulating film 30 is formed on the substrate 21 including the drain region 24 and the source region 25.
It is formed so as to cover the surface and the surface of the gate electrode 23.

The MIS transistor having the structure as shown in FIGS. 4 and 5 can be manufactured by the following method as an example.

First, a gate insulating film 22 made of SiO ₂ or the like is formed on the surface of the p-type substrate 21 separated by the field oxide film 61, and a gate electrode 23 made of polysilicon or the like is formed on the gate insulating film 22. .. Next, using the gate insulating film 22, the gate electrode 23 and the field oxide film 61 as a mask, n-type high concentration diffusion regions 24 and 25 are formed on the surface of the substrate 21 on both sides thereof. Further, after removing only the gate insulating film 22 by etching from its side surface, an insulating film 30 covering the surface of the substrate 21 including the diffusion regions 24 and 25 and the surface of the gate electrode 23 is formed. Then, by forming the interlayer insulating film 31 by deposition or the like in a vacuum atmosphere or an inert gas atmosphere, the cavity region 60 filled with vacuum or an inert gas can be formed. After that, if the drain electrode 26 and the source electrode 27 are formed by penetrating the interlayer insulating film 31 and the insulating film 30, the MIS transistor as shown in FIGS. 4 and 5 can be manufactured.

In the structure as described above, the source electrode 2
When a positive high voltage is applied to the gate electrode 23 and the drain electrode 26 with 7 and the substrate terminal (not shown) being grounded, a current flows in the channel region 32, and the channel electrons are hot electrons due to the high electric field around the drain region 24. It is converted into carriers, and a part thereof is injected into the cavity region 60 in the vicinity of the drain region 24 over the energy barrier between the substrate and the insulating film. Alternatively, a large amount of hot carriers are generated near the drain region 24 due to impact ionization with channel electrons, and a part of the hot carriers are injected into the cavity region 60 near the drain region 24 over the barrier between the substrate and the insulating film. Then, the hot carriers injected into the cavity region 60 flow into the gate electrode 23 and the drain region 24 by the electric field formed inside the cavity region 60 by the gate electrode 23 or the drain region 24.

Therefore, according to the present embodiment, all the hot carriers generated near the drain region 24 and crossing the barrier between the substrate and the insulating film are injected into the cavity region 60.
As in the conventional case, hot carriers are generated in the gate electrode 23 and the substrate 2.
It does not cause a situation such as being fixed with 1,
It is possible to significantly suppress variations in element characteristics and reduction in element life. That is, in the first embodiment described above, most of the injected hot carriers are injected into the cavity region 28, but only a small portion may be injected into the gate oxide film 22, but in this embodiment, the barrier is formed. It can be considered that all the hot carriers that exceed the temperature are injected into the cavity region 60. Therefore, it is possible to suppress variations in device characteristics and reduction in device life due to injection of hot carriers into the gate oxide film as in the conventional case. You can do it.

-Modification of Second Embodiment- FIG. 6 shows an LDD (Lightly Do) configuration of the second embodiment.
FIG. 3 is a cross-sectional view showing an example applied to a MIS transistor having a ped drain structure.

In FIG. 6, 70 is an n-type low concentration diffusion region formed on the side of the drain region 24 on the side of the channel region 32, and 71 is an n-type low concentration concentration formed on the side of the source region 25 on the side of the channel region 32. It is a diffusion area. Also in this embodiment, the cavity region 60 is formed over the entire region sandwiched between the gate electrode 23 and the substrate 21. Note that 72 and 73 are the gate insulating film 22 and the gate electrode 2.
3 is a side wall made of SiO ₂ or the like formed on the side portion of 3.

Therefore, even in the embodiment shown in FIG. 6, it is possible to obtain the same effect as that of the first embodiment.

Next, FIG. 7 shows a DDD configuration of the first embodiment.
It is sectional drawing which shows an example applied to the MIS transistor of a (Double Diffused Drain) structure. In FIG. 3, 8
0 and 81 are the drain region 24 and the source region 25, n.
N-type low-concentration diffusion region formed by the double diffusion method together with the high-concentration diffusion region. Also in this embodiment, the cavity region 60 is formed over the entire region sandwiched between the gate electrode 23 and the substrate 21.

Therefore, even in the embodiment shown in FIG. 7, it is possible to obtain the same effect as that of the above-mentioned first embodiment.

The details of the MIS transistor of the present invention are not limited to those of the first and second embodiments described above, and various modifications are possible. As an example, in each of the above embodiments, n
The MIS transistor of the channel has been described, but p
The same effect can be obtained for the channel MIS transistor. The same applies when a substrate having an epitaxial layer is used instead of the low-concentration substrate.

Further, the present invention can be applied to a MIS transistor having a buried channel structure, a JMOSFET, and the like. Further, if the above-mentioned cavity region is provided only at least on the drain side, the desired effect can be achieved, and the cavity region on the source side can be omitted.

[0033]

As described in detail above, according to the present invention, a vacuum or an inert gas is filled between the substrate and the gate electrode so as to cover at least the boundary between the drain region and the channel region. Since the hollow region is formed, most of the hot carriers generated near the drain region are injected into this hollow region and flow to the gate electrode or the drain region. Therefore, it is possible to reduce the number of hot carriers that are injected and fixed in the gate insulating film across the barrier between the substrate and the insulating film, and it is possible to suppress variations in device characteristics and a decrease in device life. In particular, according to the invention of claim 2, since the cavity region is formed over the entire region sandwiched between the gate electrode and the substrate, all the hot carriers that cross the barrier are injected into the cavity region, Injection and fixation of hot carriers to the insulating film can be eliminated, and fluctuations in element characteristics and reduction in element life can be significantly suppressed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a MIS transistor which is a first embodiment of the present invention.

FIG. 2 is a MIS having an LDD structure, which is a modification of the first embodiment.
It is sectional drawing which shows a transistor.

FIG. 3 is an M of a DDD structure which is another modification of the first embodiment.
It is sectional drawing which shows an IS transistor.

FIG. 4 is a cross-sectional view taken along the channel length direction showing a MIS transistor which is a second embodiment of the present invention.

FIG. 5 is a sectional view taken along the channel width of the second embodiment.

FIG. 6 is a MIS having an LDD structure which is a modification of the second embodiment.
It is sectional drawing which shows a transistor.

FIG. 7 is an M of a DDD structure which is another modification of the second embodiment.
It is sectional drawing which shows an IS transistor.

FIG. 8 is a cross-sectional view showing an example of a conventional MIS transistor.

[Explanation of symbols]

 21 p-type substrate 22 gate insulating film 23 gate electrode 24 drain region 25 source region 28, 29, 60 cavity region 32 channel region

Claims (2)

[Claims] 1. A MIS including a source region and a drain region formed on a substrate, a channel region formed between the source region and the drain region, and a gate electrode provided in proximity to the channel region. In the transistor, there is provided a MIS cavity which is formed between the substrate and the gate electrode and which covers at least the boundary between the drain region and the channel region and which is filled with a vacuum or an inert gas. Transistor. 2. The MIS transistor according to claim 1, wherein the cavity region is formed over the entire region sandwiched between the gate electrode and the substrate.
IS transistor.