JPH0548054A - Master slice type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the number of input/output basic cells by electrically connecting metallic wirings for supplying a power supply arranged onto the input/output basic cells to metallic wirings for supplying a power supply disposed in other input/output basic cell regions through metallic wirings arranged to metallic wiring layers different from layers, to which the former metallic wirings are disposed. CONSTITUTION:Input/output basic cells 112-115 are arranged on the outer circumferential section of a basic cell region 102, and input/output basic cell regions 105-107, 104 are formed respectively. A corner region 108 shares the input/output basic cell regions 104 and 105, and the input/output basic cell 112 forming the input/output basic cell region 105 is disposed. A metallic wiring 128 connects metallic wirings 125 and 127 for supplying a power supply arranged in the input/output basic cell regions. Metallic wirings connecting the mutual metallic wirings for supplying the power supplies can be wired regardless of the input/ output basic cells disposed in the corner regions. Accordingly, a large number of the inout/output basic cells can be disposed, thus effectively utilizing chip corners.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice type semiconductor integrated circuit device, and more particularly to an arrangement structure of input / output basic cells and metal wiring for power supply.

[0002]

2. Description of the Related Art FIG. 4 shows an overall configuration of a conventional master slice type gate array. In the figure, 404, 405, 406 and 407 are basic cell areas 402.
Is an input / output basic cell row arranged outside of and parallel to each side, and forms an input / output basic cell region. 412 is V
DD (or VSS), 413 is VSS (or V
It is a metal wiring for power supply having a potential of DD). Further, 408, 409, 410, 411 are basic cell regions 4
It is a region shared by the input / output basic cell region (hereinafter, referred to as a corner region) located outside each side of two sides intersecting with four sides surrounding 02. The input / output basic cell column 40
4, 405, 406, 407 are the corner regions 408,
It does not extend to 409, 410, 411. Therefore, no input / output basic cell is arranged in the corner area. Also, FIG.
FIG. 1 shows a layout of metal wiring for power supply in the corner area in the conventional method. The input / output basic cells 503, 50
4 are arranged to form the input / output basic cell regions 505 and 506, and the input / output basic cell regions 505 and 506 form the corner region 507. The input / output basic cells 503 and 504 are not arranged in the corner region, and the power source metal wirings arranged on the input / output basic cell regions 505 and 506 intersect in the corner region and are continuous in the same wiring layer. The metal wirings 508 and 509 for power supply are formed. Fifty
Reference numeral 8 has a potential of VDD (or VSS), and reference numeral 509 has a potential of VSS (or VDD). Therefore, since the input / output basic cell is not arranged, the power supply metal wiring can be connected to the other power supply metal wiring in the same wiring layer.

[0003]

In the above prior art, the corner area of the master slice type semiconductor integrated circuit device is an area where the input / output basic cell cannot be arranged. When configuring a logic with a master slice type gate array, the chip size and cost are determined by two factors, the number of basic cells and the number of input / output basic cells. Therefore, there is a problem in that the cost of the chip increases if there is a region in the chip where the basic cell and the input / output basic cell cannot be arranged, such as the corner region.

Therefore, the present invention is intended to solve such a problem, and its object is to increase the number of input / output basic cells without reducing the number of basic cells in a master slice type gate array. It is an object of the present invention to provide an arrangement structure of and an arrangement structure of metal wiring for power supply.

[0005]

SUMMARY OF THE INVENTION On a semiconductor substrate, a basic cell forming logic, an input / output basic cell forming input / output logic, and an input / output terminal directly electrically connected to a package are regularly arranged. In the master-slice type gate array, the input / output basic cells are continuously arranged outside and parallel to each side of the four sides surrounding the basic cell, and the input / output basic cell region is provided for the side. One of the input / output basic cell regions is formed in a region shared by the input / output basic cell regions located outside each side of two sides intersecting with the four sides surrounding the basic cell. The input / output basic cells are arranged, and the metal wiring for power supply arranged on the input / output basic cells arranged continuously outside and parallel to each of the four sides is the other input / output. Metal wiring for power supply arranged on the basic cell area and Sources Unlike supplying metal wire arranged is a layer of, and characterized by connecting said electrically via metal wires arranged in a logical interconnect layer different from the metal wiring layers that make up the input and output basic cell.

[0006]

1 and 2 show an example of the overall configuration of a master slice type gate array having an input / output basic cell layout structure of the present invention. In FIG. 1, the input / output basic cells 112, 113, 114, 1 are provided on the outer peripheral portion of the basic cell region 102.
15 are arranged in the input / output basic cell regions 105 and 1 respectively.
06, 107 and 104 are formed. Reference numeral 108 denotes the corner area shared by the input / output basic cell areas 104 and 105.
The input / output basic cells 112 forming the above are arranged. Similarly, 109, 110, and 111 are corner regions shared by the input / output basic cell regions 105 and 106, the input / output basic cell regions 106 and 107, and the input / output basic cell regions 107 and 104, respectively. Basic cell 11
3, 114, 115 are arranged. Reference numeral 128 denotes the metal wiring of the present invention, which connects the power supply metal wirings 125 and 127 arranged in the input / output basic cell region. Similarly 1
29, 130, 131, 132, 133, 134, 13
The metal wirings 5 are metal wirings 124 and 126, 121 and 12 for power supply arranged in the input / output basic cell area, respectively.
7, 120 and 126, 121 and 123, 120 and 12
2, 123 and 125, 122 and 124 are connected via a connection terminal. Further, 116, 117, 118, and 119 are input / output terminals dedicated to the metal wiring for power supply.

In FIG. 2, the input / output basic cells 212, 213, 214 and 21 are provided on the outer peripheral portion of the basic cell area 202.
5, the input / output basic cell regions 204, 205,
Form 206 and 207. Reference numeral 208 denotes the corner region shared by the input / output basic cell regions 204 and 205, and the input / output basic cell 212 forming the input / output basic cell region 204 is arranged in the present invention. Similarly 2
Reference numerals 09, 210 and 211 denote the input / output basic cell regions 2 respectively.
05 and 206, the input / output basic cell regions 206 and 20
7, the corner regions shared by the input / output basic cell regions 207 and 204, and each of the input / output basic cell 21
4, 212 are arranged. As shown in FIG. 2, the input / output basic cells 213 and 215 arranged in the input / output basic cell regions 205 and 207 are not arranged in the corner regions. Reference numeral 228 denotes the metal wiring of the present invention, which is the metal wirings 216 and 21 for power supply arranged in the input / output basic cell region.
Connect 8 Similarly, 229, 230, 231, 23
The metal wirings 2, 233, 234, and 235 are the power supply metal wirings 21 arranged in the input / output basic cell regions, respectively.
7 and 219, 218 and 220, 219 and 221, 220
And 222, 221, 223, 216, 222, 217 and 223 are connected via the connection terminals. In the present invention, the metal wiring for connecting the metal wiring for power supply can be wired regardless of the input / output basic cell arranged in the corner area, and the input / output basic cell also has two pieces sharing the corner area. It is possible to freely select the input / output basic cell area in units of the corner areas. Further, the setting of the input / output terminal dedicated to the metal wiring for power supply is free.

FIG. 3 shows an example of the layout structure of the metal wiring for power supply of the present invention. The power supply metal wirings 308 and 310 arranged on the input / output basic cells 303 and 304 are VDD.
(Or VSS) potential is supplied and power supply wiring 30
9, 311 are supplied with the potential of VSS (or VDD). In FIG. 3, the input / output basic cell 304 forming the input / output basic cell region 306 in the corner region 307 is shown.
The power supply metal wirings 308 and 309 on the input / output basic cell are arranged and supplied to the input / output basic cell. The power supply metal lines 310 and 311 arranged in the input / output basic cell region 305 do not extend to the corner region where the input / output basic cell 303 in which the power supply metal line is arranged is not arranged. Further, by extending the metal wirings 310 and 311 for power supply on the input / output basic cell 304 in the corner area, the input / output basic cell 304 in the corner area becomes unable to form a logic, and thus becomes an input / output basic cell. I won't. In the present invention, the power supply metal wirings 308 and 310 are electrically connected to each other through the metal wiring layer 316 and the connection vias 313 and 314. Similarly, the power supply metal wirings 309 and 311 are electrically connected to each other through the metal wiring layer 317 and the connection vias 312 and 315. In the present invention, the connection metal wirings 316, 3
By arranging 17 in a wiring layer different from the metal wiring layer and the power supply metal wiring layer in which the input / output basic cell constitutes logic, connection between the power supply metal wirings and the arrangement of the input / output basic cell are possible. In addition, the power supply metal wiring 308
Is supplied with a potential from the outside by the input terminal 319,
The potential is the metal interconnection wiring 31 for power supply of the present invention.
6, through the connection vias 314, 313 to the power supply metal wiring 310. Therefore, the power supply metal wiring 3
It is not necessary to set a power supply input / output terminal for the power supply metal wiring 310 in the input / output basic cell region 305 in which 10 is arranged. Similarly, a potential is supplied to the power supply metal wiring 309 from the outside by the input terminal 318, and the potential is supplied through the power supply metal wiring connection wiring 317 and the connection vias 315 and 312 of the present invention. Is supplied to the metal wiring 311 for use.

In the embodiment of the present invention, a symmetrical structure is shown in four areas of the corner area.
It is also possible to combine the structures of FIG. 2, and it is also possible to form the structure of the present invention in units of one area among the four areas of the corner area.

[0010]

As described above, according to the present invention, in a master slice type gate array, a large number of input / outputs can be efficiently performed in a chip having the same area and a chip having the same number of basic cells. The basic cells can be arranged, and the chip corner area can be effectively used.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a master slice type gate array having an input / output basic cell arrangement structure of the present invention.

FIG. 2 is an overall configuration diagram of a master slice type gate array having an input / output basic cell arrangement structure of the present invention.

FIG. 3 is an arrangement structure diagram of a metal wire for power supply of the present invention.

FIG. 4 is an overall configuration diagram of a master slice type gate array in a conventional system.

FIG. 5 is a layout view of metal wiring for power supply in a corner area in the conventional method.

Description of reference numerals 101, 201, 401 ... Semiconductor substrates 102, 202, 301, 402, 501 ... Basic cell regions 103, 116, 117, 118, 119, 203, 3
02, 318, 319, 403, 502 ... I / O terminals (pads) 404, 405, 406, 407 ... I / O basic cell columns 112, 113, 114, 115, 212, 213, 2
14, 215, 303, 304, 503, 504 ...
Input / output basic cells 104, 105, 106, 107, 204, 205, 2
06, 207, 305, 306, 505, 506 ...
Input / output basic cell area 108, 109, 110, 111, 208, 209, 2
10, 211, 307, 408, 409, 410, 41
1, 507 ... Corner area 120, 121, 122, 123, 124, 125, 1
26, 127, 216, 217, 218, 219, 22
0, 221, 222, 223, 308, 309, 31
0, 311, 412, 413, 508, 509 ...
Power supply metal wires 128, 129, 130, 131, 132, 133, 1
34, 135, 224, 225, 226, 227, 22
8, 229, 230, 231 ... Metal wiring for connecting metal wiring for power supply Metal wiring 312, 313, 314, 315 ... Via 316, 317 ... Metal wiring layer

Claims (2)

[Claims] 1. A master slice system in which a basic cell forming a logic, an input / output basic cell forming an input / output logic, and an input / output terminal directly electrically connected to a package are regularly arranged on a semiconductor substrate. In the gate array, the input / output basic cells are continuously arranged outside and parallel to each of the four sides surrounding the basic cell to form an input / output basic cell region for the side. The input / output forming one input / output basic cell area in the area shared by the input / output basic cell areas located on the outer sides of the two sides intersecting the four sides surrounding the basic cell A master slice type semiconductor integrated circuit device, in which basic cells are arranged. 2. The master slice type semiconductor integrated circuit device according to claim 1, wherein the master slice type semiconductor integrated circuit device is arranged on the input / output basic cells continuously outside and parallel to each of the four sides. The metal wiring for power supply is different from the metal wiring for power supply arranged on the other input / output basic cell area and the layer in which the metal wiring for power supply is arranged, and the logic wiring formed by the input / output basic cell. A master slice type semiconductor integrated circuit device, wherein the master slice type semiconductor integrated circuit device is electrically connected via a metal wiring arranged in a metal wiring layer different from the layer.