JPH0542158B2 - - Google Patents
Info
- Publication number
- JPH0542158B2 JPH0542158B2 JP2936286A JP2936286A JPH0542158B2 JP H0542158 B2 JPH0542158 B2 JP H0542158B2 JP 2936286 A JP2936286 A JP 2936286A JP 2936286 A JP2936286 A JP 2936286A JP H0542158 B2 JPH0542158 B2 JP H0542158B2
- Authority
- JP
- Japan
- Prior art keywords
- hole
- layer
- multilayer
- printed wiring
- wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 14
- 230000002209 hydrophobic effect Effects 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000003054 catalyst Substances 0.000 claims description 7
- 238000005553 drilling Methods 0.000 claims description 6
- 238000007772 electroless plating Methods 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 6
- 230000003197 catalytic effect Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 239000007788 liquid Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 47
- 239000004020 conductor Substances 0.000 description 14
- 238000000034 method Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- BFKJFAAPBSQJPD-UHFFFAOYSA-N tetrafluoroethene Chemical group FC(F)=C(F)F BFKJFAAPBSQJPD-UHFFFAOYSA-N 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- PYVHTIWHNXTVPF-UHFFFAOYSA-N F.F.F.F.C=C Chemical compound F.F.F.F.C=C PYVHTIWHNXTVPF-UHFFFAOYSA-N 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多層印刷配線板およびその製造方法に
関し、特にスルホール導体層が分割して設けたス
ルホールを一部に有する高密度多層印刷配線板に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer printed wiring board and a method for manufacturing the same, and more particularly to a high-density multilayer printed wiring board in which a through-hole conductor layer has divided through-holes in some parts. .
従来の印刷配線板は、部品挿入用の孔形成は勿
論、経由孔(バイア・ホール)形成も貫通孔を穿
設させて無電解めつき等の手段により孔壁に導体
層を設けるのが一般的である。
In conventional printed wiring boards, not only holes for inserting components but also via holes are formed by drilling through holes and providing a conductive layer on the hole wall by means such as electroless plating. It is true.
また、多層印刷配線板(以後多層板と略称)の
高多層化に伴ない一部の内層に埋込み経由孔(イ
ンナーレイヤーバイア・ホール)を設ける設計も
採用されつつある。 Additionally, as multilayer printed wiring boards (hereinafter abbreviated as multilayer boards) become more multilayered, designs in which embedded via holes (inner layer via holes) are provided in some of the inner layers are also being adopted.
近年、電子機器の性能上および経済上のニーズ
から実装の高密度化の試みがなされている。この
ためIC,LSI等の電子デバイスの高集積化、高速
化が進められていることは勿論、これらを実装す
る印刷配線板についても高密度化が進められてい
る。 In recent years, attempts have been made to increase the packaging density of electronic devices due to performance and economical needs. For this reason, not only are electronic devices such as ICs and LSIs becoming more highly integrated and faster, but printed wiring boards on which these devices are mounted are also becoming more dense.
印刷配線板の高密度化のために2つの試みが設
計的になされている。すなわち、その第1の試み
は導体層数を増加させる高多層化の試みであり、
第2の試みは格子パターン間に多くの配線を通す
ことである。しかし、第1の試みでは層間の導体
層を接続するバイア・ホールの増加になる。特に
このバイア・ホールを印刷配線板に第2図のよう
にバイア・ホール5を貫通孔として設けた場合に
は、前述の第2の試みの配線性が著しく阻害され
る。そのためバイア・ホール5を小径化すること
で対応しているが、高多層化に伴つて板厚も増加
し、板厚/孔径の比(アスペクト比)が増加し、
印刷配線板の製造性を著しく阻害している。ま
た、超高密度化が必要な分野では10層以上の多層
化を図り、内層にバイア・ホールを設けたいわゆ
る埋め込みバイバ・ホールが採用されているが、
性能的には満足しても経済的にみると全てのニー
ズを満足するものではなかつた。 Two attempts have been made to increase the density of printed wiring boards. That is, the first attempt was to increase the number of conductor layers, increasing the number of layers.
The second attempt is to pass many wires between the grid patterns. However, the first attempt results in an increase in via holes connecting the interlayer conductor layers. Particularly, when the via hole 5 is provided as a through hole in the printed wiring board as shown in FIG. 2, the wiring performance of the above-mentioned second attempt is significantly impaired. This has been addressed by reducing the diameter of the via hole 5, but as the number of layers increases, the thickness of the plate also increases, and the ratio of plate thickness/hole diameter (aspect ratio) increases.
This significantly impedes the productivity of printed wiring boards. In addition, in fields that require ultra-high density, multi-layers of 10 or more are used, and so-called buried via holes with via holes in the inner layers are used.
Although it was satisfactory in terms of performance, it did not satisfy all needs economically.
また、多層板でも特に、オフイス・オートメー
シヨン機器(OA機器)等で需要の増大が予測さ
れる5〜10層の多層板において前述の問題を解決
する必要が生じている。 Furthermore, there is a need to solve the above-mentioned problems in multilayer boards, especially in multilayer boards with 5 to 10 layers, whose demand is expected to increase in office automation equipment (OA equipment) and the like.
このための一つの試みとして“メイキング
100000サーキツトフイツトホエアアツトモスト
6000フイツトビフオア(Making100000 Circuits
fit where at most 6000 fit before;
Electronic,August2,1979年)”第3図Cに示
すブラインド・バイア・ホール,すなわち非貫通
孔によつて配線の収容性を向上させている。 As an attempt to achieve this goal, “Making”
100000 Circuits Fastest Where Most
6000 Foot Bifor (Making100000 Circuits
fit where at most 6000 fit before;
Electronic, August 2, 1979)" The blind via hole shown in FIG. 3C, that is, the non-through hole improves the ability to accommodate wiring.
しかし製造上から考慮すると“レーザーインエ
レクトロニクス(Lasers in Electronics;
Circuit Manufacturing,July,1981年)”ある
いは、“カツパープレーテイングアドレストマル
チレイヤーボート(Copper Plating Advanced
Mutltilayer Boards;IPC,1976年Fall
Meeting)”で紹介されているように、レーザま
たはドリルによつて第3図Aの如き多層板1に第
3図Cのようにブラインド・バイヤ・ホール5−
1,5−2を片面ずつ穿設するという非能率が伴
なう。
However, from a manufacturing perspective, “Lasers in Electronics”
Circuit Manufacturing, July, 1981)” or “Copper Plating Advanced
Mutltilayer Boards; IPC, Fall 1976
Blind buyer holes 5-- as shown in FIG. 3-C are formed in the multilayer board 1 as shown in FIG.
This involves the inefficiency of drilling holes 1 and 5-2 on each side.
さらにレーザによる穿設では第3図Bのように
多層板1のバイア・ホールが穿設されるべき位置
P−2の最外層の銅箔をエツチング除去した後、
バイア・ホールを穿設するので工程が増える欠点
がある。 Furthermore, in laser drilling, as shown in FIG. 3B, after etching and removing the outermost copper foil at the position P-2 where the via hole is to be drilled in the multilayer board 1,
This method has the disadvantage that the number of steps increases because a via hole is drilled.
またバイア・ホールを穿設した後、その内壁を
含む全面に無電解めつきで導体層を形成するが、
第3図Dの最外層の絶縁層間1a−1,1a−2
が厚い場合、均一な導体層の形成が難しく信頼性
上好ましくない。 In addition, after drilling a via hole, a conductive layer is formed on the entire surface including the inner wall by electroless plating.
Between the outermost insulation layers 1a-1 and 1a-2 in Figure 3D
If it is thick, it is difficult to form a uniform conductor layer, which is unfavorable in terms of reliability.
本発明の目的は、このような従来多層板の製造
上の欠点を解消した多層印刷配線およびその製造
方法を提供することにある。 An object of the present invention is to provide a multilayer printed wiring and a method for manufacturing the same, which eliminates such drawbacks in manufacturing conventional multilayer boards.
本考案によれば、予め導体回路パターンを表裏
両面に設けた絶縁基板の1組をそれぞれ最外側に
配置し、その内側にプリプレグ層を配置し、更に
その内側に予め多層印刷配線板の表裏導通用の貫
通孔の位置に、その貫通孔の直径より大なる同心
円にくり抜いた孔部を設けた疎水性を有する絶縁
フイルムを配置し、加熱加圧して、前記疎水性を
有する絶縁フイルムのくり抜き孔部を前記プリプ
レグ層から流出した樹脂で充填し多層化基板を形
成する工程と、
前記多層化基板に前記表裏導通用の貫通孔と、
内層回路パターン接続用の貫通孔を穿設する工程
と、
前記多層化基板を無電解めつきに触媒作用をも
つ液に浸漬して触媒活性化する工程と、
前記多層化基板の表裏両面に、前記貫通孔の位
置に一定の逃げを設けて所望の部分に絶縁性を有
する永久マスク層を被着形成する工程と、
前記多層化基板を無電解めつきし、表裏両面の
永久マスク層から露出している部分と表裏導通用
貫通孔内壁と、内層回路パターン接続用貫通孔内
壁の疎水性フイルムの露出壁面を除く内壁に導体
層を形成する工程とを有することを特徴とする多
層印刷配線板の製造方法が得られる。
According to the present invention, a set of insulating substrates with conductor circuit patterns provided on both the front and back surfaces is placed on the outermost side, a prepreg layer is placed on the inside of the insulating substrates, and a prepreg layer is placed on the inside of the insulating substrates, and the front and back conductors of the multilayer printed wiring board are further placed on the inside. A hydrophobic insulating film with a hole hollowed out in a concentric circle larger than the diameter of the through hole is placed at the position of the general through hole, and heated and pressurized to form a hole in the hydrophobic insulating film. forming a multilayered substrate by filling the portion with resin that has flowed out from the prepreg layer; and providing a through hole for front and back conduction in the multilayered substrate;
a step of drilling a through hole for connecting an inner layer circuit pattern; a step of immersing the multilayer substrate in a liquid that has a catalytic action for electroless plating to activate the catalyst; A step of providing a certain clearance at the position of the through hole and depositing a permanent mask layer having insulating properties on a desired portion; and electroless plating of the multilayer substrate to expose the permanent mask layer on both the front and back surfaces. A multilayer printed wiring board comprising: the inner wall of the through hole for front and back conduction; and the step of forming a conductive layer on the inner wall excluding the exposed wall surface of the hydrophobic film on the inner wall of the through hole for connecting the inner layer circuit pattern. A manufacturing method is obtained.
以下、本発明の一実施例を図面で説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図Fは本実施例によつて得られる多層板
で、バイア・ホール(貫通孔)5内は、ガラス布
基材エポキシ樹脂等の絶縁基板1a−1,1a−
2およびプリプレグ層1bが、疎水性を有する絶
縁フイルム(例えば四フツ化エチレン樹脂フイル
ム等)3により上下に分離され、導体層がリング
状に除去して分離した導体層7−1,7−2を有
する構造となる。 FIG. 1F shows a multilayer board obtained according to this example, in which the via holes (through holes) 5 are filled with insulating substrates 1a-1, 1a-
2 and the prepreg layer 1b are vertically separated by a hydrophobic insulating film (for example, tetrafluoroethylene resin film, etc.) 3, and the conductor layer is removed in a ring shape to form conductor layers 7-1 and 7-2. The structure is as follows.
次に本発明多層板の製造方法を第1図A〜Fを
参照して詳細に説明する。 Next, the method for manufacturing the multilayer board of the present invention will be explained in detail with reference to FIGS. 1A to 1F.
第1図Aは積層構成を示し、ガラス布基材エポ
キシ樹脂積層板1a−1,1a−2の表裏両面に
公知の印刷・エツチング法により所望する回路パ
ターンを形成した多層板の1−2層(1a−1)
と3−4層(1a−2)を最外側に配し、その内
側にプリプレグ層1b−1,1b−2を配し、さ
らにその内側に多層板の部品挿入用の孔6が穿設
されるべき位置にP−1に部品挿入用の孔6の直
径より大きい同心円にくり抜いた孔を設けた疎水
性を有する四フツ化エチレン樹脂フイルム3を組
合せ、加熱・加圧して一体化成型し、多層化積層
板1を得る(第1図B)。 FIG. 1A shows a laminated structure, with 1-2 layers of a multilayer board having a desired circuit pattern formed on both the front and back surfaces of the glass cloth base epoxy resin laminates 1a-1 and 1a-2 by a known printing/etching method. (1a-1)
and 3-4 layers (1a-2) are arranged on the outermost side, prepreg layers 1b-1 and 1b-2 are arranged on the inner side, and holes 6 for inserting parts of the multilayer board are bored inside. A hydrophobic ethylene tetrafluoride resin film 3 having a concentric hole larger than the diameter of the hole 6 for inserting the component is combined at the desired position P-1, and integrally molded by heating and pressurizing. A multilayer laminate 1 is obtained (FIG. 1B).
次に、部品挿入用の貫通孔6および内層接続す
る貫通孔5をドリルにより穿設する(第1図C)。 Next, a through hole 6 for inserting the component and a through hole 5 for connecting the inner layer are drilled (FIG. 1C).
次に貫通孔5および6を導体化するためにパラ
ジウムなどの触媒を貫通孔5および6の内壁と多
層化積層板1の表面に吸着させ触媒層10を形成
するが、貫通孔5の内壁の四フツ化エチレン樹脂
フイルム端面のみ疎水性のため触媒層10は形成
されない(第1図D)。 Next, in order to make the through holes 5 and 6 conductive, a catalyst such as palladium is adsorbed onto the inner walls of the through holes 5 and 6 and the surface of the multilayer laminate 1 to form a catalyst layer 10. Since only the end face of the tetrafluoroethylene resin film is hydrophobic, no catalyst layer 10 is formed (FIG. 1D).
次に積層板1の表面に不必要な導体層が形成さ
れないように、絶縁性と耐薬品性とを有する永久
マスク層4を所望部分に被着形成する(第1図
E)。 Next, a permanent mask layer 4 having insulating properties and chemical resistance is deposited on desired portions so that unnecessary conductor layers are not formed on the surface of the laminate 1 (FIG. 1E).
次に、全面に無電解銅めつきを施すと露出した
導体層上および貫通孔5,6の内壁の触媒層10
に銅めつき導体層7が形成され、特に貫通孔5で
は、四フツ化エチレン樹脂フイルム3により銅め
つき導体層7が1−2層を接続する導体層7−1
と3−4を接続する7−2に離間した本発明の多
層プリント配線板が得られる(第1図F)。 Next, when electroless copper plating is applied to the entire surface, the catalyst layer 10 on the exposed conductor layer and on the inner walls of the through holes 5 and 6
A copper-plated conductor layer 7 is formed in the through hole 5, and the copper-plated conductor layer 7 connects layers 1-2 by the tetrafluoroethylene resin film 3, especially in the through hole 5.
A multilayer printed wiring board of the present invention is obtained in which 7-2 is connected to 3-4 (FIG. 1F).
以上説明したように、本発明により、レーザ等
の特殊な手段、あるいは一面ずつ非貫通孔を穿設
する非量産的な従来手段によらず孔を穿設できる
ので生産性が著しく向上する。さらに内層接続の
信頼性の向上が図れ、配線収容性が著しく向上し
た高密度な多層印刷配線が得られる効果がある。
As explained above, according to the present invention, productivity can be significantly improved since holes can be formed without using special means such as a laser or conventional means that are not suitable for mass production, such as forming non-through holes one surface at a time. Furthermore, the reliability of inner layer connections can be improved, and high-density multilayer printed wiring with significantly improved wiring capacity can be obtained.
第1図A,B,C,D,E,Fは本発明の位置
実施例を工程順に示す断面図、第2図は従来例の
一つの断面図、第3図A,B,C,Dは従来例の
他の一つを工程順に示す断面図である。
1……多層化積層板、1a−1……1−2層を
形成する積層板、1a−2……3−4層を形成す
る積層板、1b,1b−1,1b−2……プリプ
レグ層、2−1〜2−4……1〜4層の導体パタ
ーン、3……疎水性を有する絶縁フイルム、4…
…永久マスク層、5,6……貫通孔、5−1,5
−2……1−2層,5−6層間を接続するブライ
ンド・バイア・ホール、7,7−1,7−2……
無電解銅めつきによる銅めつき導体層、10……
触媒層、P−1……部品挿入用の貫通孔の穿設さ
れる位置、P−2……バイアホールが穿設される
位置。
Figures 1A, B, C, D, E, and F are sectional views showing the positional embodiment of the present invention in the order of steps, Figure 2 is a sectional view of one of the conventional examples, and Figure 3 A, B, C, and D. FIG. 2 is a sectional view showing another conventional example in the order of steps. 1... Multilayered laminate, 1a-1... A laminate forming 1-2 layers, 1a-2... A laminate forming 3-4 layers, 1b, 1b-1, 1b-2... Prepreg Layers, 2-1 to 2-4... conductor patterns of 1 to 4 layers, 3... hydrophobic insulating film, 4...
...Permanent mask layer, 5,6...Through hole, 5-1,5
-2...Blind via hole connecting layers 1-2 and 5-6, 7, 7-1, 7-2...
Copper-plated conductor layer by electroless copper plating, 10...
Catalyst layer, P-1...Position where a through hole for component insertion is formed, P-2...Position where a via hole is formed.
Claims (1)
縁基板の1組をそれぞれ最外側に配置し、その内
側にプリプレグ層を配置し、更にその内側に予め
多層印刷配線板の表裏導通用の貫通孔の位置に、
その貫通孔の直径より大なる同心円にくり抜いた
孔部を設けた疎水性を有する絶縁フイルムを配置
し、加熱加圧して、前記疎水性を有する絶縁フイ
ルムのくり抜き孔部を前記プリプレグ層から流出
した樹脂で充填し多層化基板を形成する工程と、 前記多層化基板に前記表裏導通用の貫通孔と、
内層回路パターン接続用の貫通孔を穿設する工程
と、 前記多層化基板を無電解めつきに触媒作用をも
つ液に浸漬して触媒活性化する工程と、 前記多層化基板の表裏両面に、前記貫通孔の位
置に一定の逃げを設けて所望の部分に絶縁性を有
する永久マスク層を被着形成する工程と、 前記多層化基板を無電解めつきし、表裏両面の
永久マスク層から露出している部分と表裏導通用
貫通孔内壁と、内層回路パターン接続用貫通孔内
壁の疎水性フイルムの露出壁面を除く内壁に導体
層を形成する工程とを有することを特徴とする多
層印刷配線板の製造方法。[Claims] 1. A set of insulating substrates on which conductive circuit patterns are provided on both the front and back sides is placed on the outermost side, a prepreg layer is placed on the inside of the insulating substrates, and further inside the set, the front and back sides of a multilayer printed wiring board are placed in advance. At the location of the through hole for continuity,
A hydrophobic insulating film having a hole hollowed out in a concentric circle larger than the diameter of the through hole was placed, and heated and pressurized to cause the hollowed out hole part of the hydrophobic insulating film to flow out from the prepreg layer. a step of filling with resin to form a multilayered substrate; providing the through-hole for front and back conduction in the multilayered substrate;
a step of drilling a through hole for connecting an inner layer circuit pattern; a step of immersing the multilayer substrate in a liquid that has a catalytic action for electroless plating to activate the catalyst; A step of providing a certain clearance at the position of the through hole and depositing a permanent mask layer having insulating properties on a desired portion; and electroless plating of the multilayer substrate to expose the permanent mask layer on both the front and back surfaces. A multilayer printed wiring board comprising: the inner wall of the through hole for front and back conduction; and the step of forming a conductive layer on the inner wall excluding the exposed wall surface of the hydrophobic film on the inner wall of the through hole for connecting the inner layer circuit pattern. manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2936286A JPS62186595A (en) | 1986-02-12 | 1986-02-12 | Multilayer printed wiring board and manufacture of the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2936286A JPS62186595A (en) | 1986-02-12 | 1986-02-12 | Multilayer printed wiring board and manufacture of the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62186595A JPS62186595A (en) | 1987-08-14 |
JPH0542158B2 true JPH0542158B2 (en) | 1993-06-25 |
Family
ID=12274067
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2936286A Granted JPS62186595A (en) | 1986-02-12 | 1986-02-12 | Multilayer printed wiring board and manufacture of the same |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62186595A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0691320B2 (en) * | 1988-03-08 | 1994-11-14 | シャープ株式会社 | Through-hole plating joining method for hard substrate and flexible substrate |
JPH0537722U (en) * | 1991-08-13 | 1993-05-21 | 株式会社椿本チエイン | Attachment structure for conveyor supporting elastic ring and conveyor drive structure having the structure |
JPH0516718U (en) * | 1991-08-13 | 1993-03-02 | 株式会社椿本チエイン | Conveyor drive structure |
TWI389205B (en) * | 2005-03-04 | 2013-03-11 | Sanmina Sci Corp | Partitioning a via structure using plating resist |
-
1986
- 1986-02-12 JP JP2936286A patent/JPS62186595A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS62186595A (en) | 1987-08-14 |
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