JP2003168868A - Method for manufacturing printed circuit board - Google Patents
Method for manufacturing printed circuit boardInfo
- Publication number
- JP2003168868A JP2003168868A JP2001368204A JP2001368204A JP2003168868A JP 2003168868 A JP2003168868 A JP 2003168868A JP 2001368204 A JP2001368204 A JP 2001368204A JP 2001368204 A JP2001368204 A JP 2001368204A JP 2003168868 A JP2003168868 A JP 2003168868A
- Authority
- JP
- Japan
- Prior art keywords
- laminate
- ivh
- carrier
- copper foil
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、プリント配線板の
製造方法に係り、特に高精細パターンを要求されるプリ
ント配線板の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a printed wiring board that requires a high-definition pattern.
【0002】[0002]
【従来の技術】一般に、多層プリント配線板の高密度化
は、配線層を増加させることによって行われているが、
単に配線層を増加させると各層の配線を接続するための
貫通孔(スルーホール)が増加して貫通孔の占める面積
が増加し、配線の収容量が低下する。そこで、接続の必
要な箇所のみ接続孔を設け、非貫通孔IVH(インター
ステイシャルバイアホール)とする方法が行われてい
る。2. Description of the Related Art In general, the densification of a multilayer printed wiring board is performed by increasing the number of wiring layers.
If the number of wiring layers is simply increased, the number of through holes (through holes) for connecting the wirings of the respective layers increases, the area occupied by the through holes increases, and the amount of wiring accommodated decreases. Therefore, a method is used in which a connection hole is provided only in a portion where connection is required and a non-through hole IVH (interstitial via hole) is formed.
【0003】図3に多層プリント配線板の表層にバイア
ホールSVHを設ける場合の従来方法を示す。図3
(a)に示すごとく内層回路板1の両面にプリプレグ2
を介して銅箔3を積層し一次積層体4を得る。次いで図
3(b)に示すごとくこの一次積層体4の所定位置にこ
の一次積層体4を貫通する孔5を穿設し、この貫通孔5
の内面を含む一次積層体4の全面をめっきしてめっき層
6を形成することにより、一次積層体4の表裏を電気的
に接続する(図3(c))。更に、この一次積層体4の
被積層面側に回路7を形成しSVH層8を得る(図3
(d))。FIG. 3 shows a conventional method for providing a via hole SVH on the surface layer of a multilayer printed wiring board. Figure 3
As shown in (a), prepregs 2 are provided on both sides of the inner circuit board 1.
The copper foil 3 is laminated via the above to obtain a primary laminate 4. Next, as shown in FIG. 3B, a hole 5 penetrating the primary laminate 4 is formed at a predetermined position of the primary laminate 4, and the through hole 5 is formed.
By plating the entire surface of the primary laminate 4 including the inner surface thereof to form the plating layer 6, the front and back of the primary laminate 4 are electrically connected (FIG. 3C). Further, a circuit 7 is formed on the surface to be laminated of the primary laminate 4 to obtain an SVH layer 8 (FIG. 3).
(D)).
【0004】このようにして作成されたSVH層8はそ
の回路7の形成面と、片面に銅箔9を積層した回路基板
10の他方の回路11の形成面とを、プリプレグ12を
介して積層し二次積層体13を得る(図3(e))。そ
してこの二次積層体13を貫通する孔14を所定位置に
穿設し(図3(f))、この貫通孔14の内面を含む二
次積層体13の全面をめっきしてめっき層15を形成す
ることにより二次積層体13の表裏を電気的接続する
(図3(g))。その後二次積層体13の両面に回路1
6および17を形成して、SHVを有する多層プリント
配線板を得ている。The SVH layer 8 thus formed has the circuit 7 forming surface and the other circuit 11 forming surface of the circuit board 10 having the copper foil 9 laminated on one surface thereof, with the prepreg 12 interposed therebetween. Then, the secondary laminated body 13 is obtained (FIG. 3E). Then, a hole 14 penetrating the secondary laminate 13 is formed at a predetermined position (FIG. 3 (f)), and the entire surface of the secondary laminate 13 including the inner surface of the through hole 14 is plated to form a plating layer 15. By forming it, the front and back of the secondary laminate 13 are electrically connected (FIG. 3 (g)). After that, the circuit 1 is formed on both surfaces of the secondary laminated body 13.
6 and 17 are formed to obtain a multilayer printed wiring board having SHV.
【0005】[0005]
【発明が解決しようとする課題】このようにして作成さ
れたSVHを有する多層プリント配線板は、銅箔3上に
SVHのめっき層6およびスルーホールのめっき層15
が累積して被着されるため、回路16および17の形成
において導体厚が厚くなり、狭ピッチの高精細パターン
を形成すのが困難であった。この表面導体厚を薄膜化し
回路形成を容易にする工法としてハーフエッチング技術
を用いるのが一般的であるが、表面導体のめっき厚のば
らつきもあってエッチング量の制御が困難であるという
問題点があった。In the multilayer printed wiring board having SVH thus formed, the SVH plating layer 6 and the through-hole plating layer 15 are formed on the copper foil 3.
However, the conductor thickness is increased in forming the circuits 16 and 17, and it is difficult to form a high-definition pattern with a narrow pitch. The half-etching technique is generally used as a method for reducing the thickness of the surface conductor to facilitate circuit formation, but there is a problem that it is difficult to control the etching amount due to variations in the plating thickness of the surface conductor. there were.
【0006】本発明は、上記課題を解決するためになさ
れたもので、SVHを含むIVHを有する多層プリント
配線板において、表面導体層を薄膜化して高密度で精細
なパターンが得られる多層プリント配線板の製造方法を
提供することを目的とする。The present invention has been made to solve the above problems, and in a multilayer printed wiring board having IVH including SVH, the surface conductor layer is thinned to obtain a high density and fine pattern. It is an object to provide a method for manufacturing a plate.
【0007】[0007]
【課題を解決するための手段】第1の発明になるプリン
ト配線板の製造方法は、a.内層回路基板の両面にプリ
プレグを介してキャリア付き銅箔の銅箔面を重ねて積層
し積層体を得る工程、b.前記積層体を貫通するIVH
用孔を所定位置に穿設し、この貫通孔内を含む積層体の
全面をめっきして積層体の表裏をIVHにて電気的接続
する工程、c.前記積層体の両面のキャリアを該キャリ
ア上のめっき層と共に除去する工程、d.前記キャリア
を除去した積層体の全面をめっきする工程、e.前記積
層体の両面に回路を形成する工程、を有することを特徴
としている。この場合、IVHを導電ペーストで充填し
てIVHの接続信頼性を確保し、またIVH上に回路を
形成することができる。A method for manufacturing a printed wiring board according to the first invention comprises a. A step of stacking the copper foil surfaces of the carrier-attached copper foil on both surfaces of the inner layer circuit board via a prepreg to obtain a laminate, b. IVH penetrating the laminate
A step of forming a working hole at a predetermined position, plating the entire surface of the laminated body including the inside of the through hole, and electrically connecting the front and back of the laminated body by IVH; c. Removing the carriers on both sides of the laminate together with the plating layers on the carrier, d. Plating the entire surface of the laminate from which the carrier has been removed, e. And a step of forming circuits on both surfaces of the laminate. In this case, the IVH can be filled with a conductive paste to secure the connection reliability of the IVH, and a circuit can be formed on the IVH.
【0008】また第2の発明になるプリント配線板の製
造方法は、a.内層回路基板の両面にプリプレグを介し
てキャリア付き銅箔の銅箔面を重ねて積層し一次積層体
を得る工程、b.前記一次積層体を貫通するIVH用孔
を所定位置に穿設し、この貫通孔内を含む一次積層体の
全面をめっきして一次積層体の表裏をIVHにて電気的
接続する工程、c.前記一次積層体のキャリア除去面側
に回路を形成しIVH層を得る工程、d.前記iVH層
の回路形成面と片面にキャリア付き銅箔を積層した回路
基板の他方の面とをプリプレグを介して積層し二次積層
体を得る工程、e.前記二次積層体を貫通する孔を所定
位置に穿設する工程、f.前記二次積層体の両面のキャ
リアを該キャリア上のめっき層と共に除去する工程、
g.前記二次積層体の全面をめっきして二次積層体の表
裏を電気的接続する工程、h.前記二次積層体の両面に
回路を形成する工程、を有することを特徴としている。
この場合、IVHを導電ペーストで充填してIVHの接
続信頼性を確保し、またIVH上に回路を形成すること
ができる。A method of manufacturing a printed wiring board according to the second invention is a method for manufacturing a printed wiring board comprising: a. A step of stacking the copper foil surfaces of the carrier-added copper foil on both surfaces of the inner layer circuit board via prepregs to obtain a primary laminate, b. A step of forming an IVH hole penetrating the primary laminate at a predetermined position, plating the entire surface of the primary laminate including the inside of the through hole, and electrically connecting the front and back of the primary laminate with IVH; c. Forming a circuit on the carrier removal surface side of the primary laminate to obtain an IVH layer, d. A step of laminating a circuit forming surface of the iVH layer and the other surface of a circuit board having a copper foil with a carrier laminated on one surface via a prepreg to obtain a secondary laminate, e. Forming a hole penetrating the secondary laminate at a predetermined position, f. Removing the carrier on both sides of the secondary laminate together with the plating layer on the carrier,
g. Plating the entire surface of the secondary laminate to electrically connect the front and back of the secondary laminate, h. And a step of forming circuits on both surfaces of the secondary laminated body.
In this case, the IVH can be filled with a conductive paste to secure the connection reliability of the IVH, and a circuit can be formed on the IVH.
【0009】本発明になるプリント配線板の製造方法に
よれば、キャリア付き銅箔上に積層体の表裏を電気的接
続する際のめっきを被着させた後キャリア上のめっきと
共にキャリアを除去し、残った銅箔上にめっきして回路
を形成するようにしたので、プリント配線板の表面導体
(回路)厚を薄膜化することができ、高密度で精細なパ
ターンが得られる。According to the method for producing a printed wiring board according to the present invention, a plating for electrically connecting the front and back of the laminate is applied on the copper foil with a carrier, and then the carrier is removed together with the plating on the carrier. Since the circuit is formed by plating on the remaining copper foil, the thickness of the surface conductor (circuit) of the printed wiring board can be reduced, and a high-density and fine pattern can be obtained.
【0010】[0010]
【発明の実施の形態】以下、本発明の実施形態を図面を
参照して説明する。図1は第1の発明になるプリント配
線板の製造過程の一実施形態を示す断面の模式図であ
る。DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing an embodiment of a process for manufacturing a printed wiring board according to the first invention.
【0011】まず、図1(a)に示すようにFR−4等
のガラス布基材エポキシ樹脂銅張積層板を公知のサブト
ラクティブ法等によって所要箇所に導体パターンを形成
してなる内層回路基板20の両面にプリプレグ21を介
して、銅箔22をキャリア23に被着させたキャリア付
き銅箔24の銅箔22側の面を重ねて積層し、積層体2
5を得る。このキャリア付き銅箔24は各種市販されて
いるが、本実施例においては70μm厚の銅箔からなる
キャリア(担持体)23に厚さ9μmに電解銅箔を被着
させた古河サーキットフォイル社製ピーラブル電解銅箔
(商品名)を使用した。プリプレグ21としてはガラス
布基材エポキシ樹脂を半硬化させたBステージ状態の適
宜の厚さのものを用いることができる。First, as shown in FIG. 1 (a), an inner layer circuit board formed by forming a conductor pattern at a required position on a glass cloth base material epoxy resin copper clad laminate such as FR-4 by a known subtractive method or the like. A copper foil 22 is attached to a carrier 23 via a prepreg 21 on both sides of the carrier 20 and the copper foil 22 side surface of a copper foil with a carrier 24 is laminated and laminated.
Get 5. Various types of the copper foil with carrier 24 are commercially available, but in the present embodiment, a carrier (carrier) 23 made of copper foil with a thickness of 70 μm is coated with electrolytic copper foil with a thickness of 9 μm, and manufactured by Furukawa Circuit Foil Co. A peelable electrolytic copper foil (trade name) was used. As the prepreg 21, it is possible to use one having an appropriate thickness in a B stage state in which a glass cloth base material epoxy resin is semi-cured.
【0012】次いで図1(b)に示すごとく、この積層
体25の所定位置にこの積層体25を貫通するIVH用
孔26をドリルで穿設して、この貫通孔26の内面を含
む積層体25の全面を無電解銅めっきおよび電解銅めっ
きして銅めっき層27を形成することにより、積層体2
5の表裏を電気的に接続するIVH28を得る(図1
(c))。Next, as shown in FIG. 1B, an IVH hole 26 penetrating the laminated body 25 is drilled at a predetermined position of the laminated body 25, and the laminated body including the inner surface of the through hole 26 is drilled. 25 is formed by electroless copper plating and electrolytic copper plating on the entire surface of 25 to form a copper plating layer 27.
An IVH 28 that electrically connects the front and back of No. 5 is obtained (Fig. 1
(C)).
【0013】これらのIVH28をスキージ法等によっ
て銀ペースト等の導電性ペースト29で充填する(図1
(d))。次いで積層体25の表裏の銅めっき層27を
含むキャリア23を機械的に引き剥がして除去し、銅箔
22面から盛り上がって残存する導電性ペースト29
を、バフ研磨等によって研磨して平滑な表面を得る(図
1(e))。この場合、キャリア23を剥離する際にI
VH28部分のめっきをも切断するため、IVH28の
接続信頼性を損ねる虞がある。従って本実施形態では、
めっき後に導電性ペースト29で穴埋めを行い接続信頼
性を確保しているが、信頼性を損なうことなくキャリア
23を剥離できれば、この穴埋めは省略してもよい。These IVHs 28 are filled with a conductive paste 29 such as a silver paste by a squeegee method or the like (see FIG. 1).
(D)). Next, the carrier 23 including the copper plating layers 27 on the front and back sides of the laminated body 25 is mechanically peeled off and removed, and the conductive paste 29 that rises from the surface of the copper foil 22 and remains.
Is polished by buffing or the like to obtain a smooth surface (FIG. 1 (e)). In this case, when the carrier 23 is peeled off, I
Since the plating of the VH28 portion is also cut off, the connection reliability of the IVH28 may be impaired. Therefore, in this embodiment,
After the plating, the conductive paste 29 is filled in to ensure the connection reliability. However, if the carrier 23 can be peeled off without impairing the reliability, this filling may be omitted.
【0014】その後、キャリア23を除去した積層体2
5の全面を前記銅めっき層27よりも薄く電解銅めっき
して銅めっき層41を形成し(図1(f))、サブトラ
クティブ法等によってIVH29上を含む所要箇所に回
路(導体パターン)42を形成してプリント配線板40
を得ている(図1(g))。図1においては銅箔22上
にパネルめっきを施して回路42を形成したが、パター
ンめっきによって回路42を形成してもよい。Thereafter, the laminated body 2 from which the carrier 23 has been removed
The entire surface of 5 is electrolytically copper-plated thinner than the copper-plated layer 27 to form a copper-plated layer 41 (FIG. 1 (f)), and a circuit (conductor pattern) 42 is formed on a required portion including the IVH 29 by a subtractive method or the like. Forming a printed wiring board 40
(FIG. 1 (g)). Although the circuit 42 is formed by performing panel plating on the copper foil 22 in FIG. 1, the circuit 42 may be formed by pattern plating.
【0015】この実施形態によれば、キャリア付き銅箔
上に積層体の表裏を電気的接続する際のめっきを被着さ
せた後、キャリア上のめっきと共にキャリアを除去し、
残った銅箔上にめっきして回路を形成するようにしたの
で、プリント配線板の表面導体(回路)厚を薄膜化する
ことができ、高密度で精細なパターンが得られる。According to this embodiment, after the plating for electrically connecting the front and back of the laminated body is applied on the copper foil with the carrier, the carrier is removed together with the plating on the carrier,
Since the circuit is formed by plating on the remaining copper foil, the thickness of the surface conductor (circuit) of the printed wiring board can be reduced, and a high-density and fine pattern can be obtained.
【0016】図2は第2の発明になるIVH(SVH)
構造を有する多層プリント配線板の製造過程の一実施形
態を示す断面の模式図である。図2において図1の構成
要素と同一または同等の部分には、同一参照番号を付し
てその詳細な説明は省略する。FIG. 2 shows the IVH (SVH) according to the second invention.
FIG. 7 is a schematic cross-sectional view showing one embodiment of a manufacturing process of a multilayer printed wiring board having a structure. 2, parts that are the same as or equivalent to those in FIG. 1 are assigned the same reference numerals and detailed explanations thereof are omitted.
【0017】まず、図2(a)に示すように所要箇所に
導体パターンを形成してなる内層回路基板20の両面に
プリプレグ21を介して、キャリア付き銅箔24の銅箔
22側の面を重ねて積層し、一次積層体25を得る。次
いで図1(b)に示すごとく、この一次積層体25の所
定位置にこの一次積層体25を貫通する孔26をドリル
で穿設した後、一方の面(図において下面側)のキャリ
ア23を機械的に引き剥がすことによって除去し、この
貫通孔26の内面を含む一次積層体25の全面を無電解
銅めっきおよび電解銅めっきして銅めっき層27を形成
することにより、一次積層体25の表裏を電気的に接続
するIVH28を得る(図1(c))。First, as shown in FIG. 2A, the copper foil 22 side surface of the copper foil with carrier 24 is placed on both sides of the inner layer circuit board 20 having conductor patterns formed at required positions via the prepreg 21. The first laminate 25 is obtained by stacking and stacking. Then, as shown in FIG. 1B, a hole 26 penetrating the primary laminated body 25 is drilled at a predetermined position of the primary laminated body 25, and then the carrier 23 on one surface (the lower surface side in the drawing) is attached. It is removed by mechanical peeling, and the entire surface of the primary laminated body 25 including the inner surface of the through hole 26 is electrolessly copper-plated and electrolytic copper-plated to form a copper-plated layer 27. An IVH 28 that electrically connects the front and back is obtained (FIG. 1 (c)).
【0018】これらのIVH28を銀ペースト等の導電
性ペースト29で充填し(図1(d))、この一次積層
体25の前記キャリア除去面側の所要箇所に導体パター
ン30を形成しIVH層31を得る(図1(e))。こ
のようにして作成されたIVH層31はその回路30の
形成面と、片面にキャリア付き銅箔24を積層した回路
基板32の他方の面の回路33の形成面とを、プリプレ
グ21を介して積層し二次積層体34を得る(図1
(f))。These IVHs 28 are filled with a conductive paste 29 such as a silver paste (FIG. 1 (d)), a conductor pattern 30 is formed at a required portion on the carrier removal surface side of the primary laminate 25, and an IVH layer 31 is formed. Is obtained (FIG. 1 (e)). The IVH layer 31 thus formed has the circuit 30 forming surface and the circuit 33 forming surface of the other surface of the circuit board 32 having the carrier-attached copper foil 24 laminated on one surface thereof via the prepreg 21. A secondary laminated body 34 is obtained by laminating (see FIG. 1).
(F)).
【0019】そしてこの二次積層体34を貫通する孔
(スルーホール)35を所定位置に穿設した後(図1
(g))、二次積層体34の回路基板32側のキャリア
23とIVH層31側の銅めっき層27を含むキャリア
23を機械的に引き剥がして除去し(図1(h))、銅
箔22面から盛り上がって残存する導電性ペースト29
をバフ研磨等によって研磨して平滑な表面を得る。本実
施形態においてもIVH28の接続信頼性を確保できれ
ば、IVH28の穴埋めを省略することができる。After forming a hole (through hole) 35 penetrating the secondary laminated body 34 at a predetermined position (see FIG. 1).
(G)), the carrier 23 on the circuit board 32 side of the secondary laminate 34 and the carrier 23 including the copper plating layer 27 on the IVH layer 31 side are mechanically peeled and removed (FIG. 1 (h)), Conductive paste 29 rising from the surface of the foil 22 and remaining
Is polished by buffing or the like to obtain a smooth surface. Also in this embodiment, if the connection reliability of the IVH 28 can be secured, the filling of the IVH 28 can be omitted.
【0020】その後、貫通孔35の内面を含む二次積層
体34の全面を無電解銅めっきおよび電解銅めっきして
銅めっき層36を形成することにより、二次積層体34
の表裏を電気的に接続するスルーホール37を得る(図
1(i))。次いで、二次積層体34の両面にサブトラ
クティブ法等によってIVH28上を含む所要箇所に回
路38および39を形成して、IHVを有するプリント
配線板50を得る(図1(j))。Thereafter, the entire surface of the secondary laminated body 34 including the inner surface of the through hole 35 is electrolessly copper-plated and electrolytic copper-plated to form a copper plating layer 36, whereby the secondary laminated body 34 is formed.
A through hole 37 for electrically connecting the front and back sides of is obtained (FIG. 1 (i)). Next, the circuits 38 and 39 are formed on both surfaces of the secondary laminate 34 by a subtractive method or the like at required locations including on the IVH 28 to obtain a printed wiring board 50 having IHV (FIG. 1 (j)).
【0021】この実施形態によれば、IVH層表面のキ
ャリアをスルーホールめっき後にキャリア上のめっきと
共にキャリアを除去し、残った銅箔上にめっきして回路
を形成するようにしたので、プリント配線板の表面導体
(回路)厚を薄膜化することができ、高密度で精細なパ
ターンを有するIVH構造を有するプリント配線板が得
られる。According to this embodiment, since the carrier on the surface of the IVH layer is plated with the through-hole, the carrier is removed together with the plating on the carrier, and the remaining copper foil is plated to form a circuit. The thickness of the surface conductor (circuit) of the board can be reduced, and a printed wiring board having an IVH structure having a high-density and fine pattern can be obtained.
【0022】[0022]
【発明の効果】本発明によれば、IVHやスルーホール
等の積層体の表裏を電気的接続する際のめっきをキャリ
アに被着させた後、このめっきと共にキャリアを除去
し、残った銅箔上にめっきして回路を形成するようにし
たので、銅箔上にIVHやスルーホール形成時のめっき
層が累積して被着されることがなく、回路の形成におい
て導体厚が厚くならず、プリント配線板の表面導体(回
路)厚を薄膜化することができ、高密度で精細なパター
ンを有するプリント配線板を得ることができる。EFFECTS OF THE INVENTION According to the present invention, after the plating for electrically connecting the front and back of the laminate such as IVH and through holes is applied to the carrier, the carrier is removed together with this plating, and the remaining copper foil is removed. Since the circuit is formed by plating on the copper foil, the plating layer at the time of forming the IVH or the through hole is not accumulated and deposited on the copper foil, and the conductor thickness does not become thick in forming the circuit. The thickness of the surface conductor (circuit) of the printed wiring board can be reduced, and a printed wiring board having a high density and fine pattern can be obtained.
【図1】図1は本発明の1実施の形態であるプリント配
線板の製造工程を示す模式図である。FIG. 1 is a schematic view showing a manufacturing process of a printed wiring board which is an embodiment of the present invention.
【図2】図2は本発明の他の実施の形態であるプリント
配線板の製造工程を示す模式図である。FIG. 2 is a schematic view showing a manufacturing process of a printed wiring board which is another embodiment of the present invention.
【図3】図3は従来の多層プリント配線板の製造工程を
示す模式図である。FIG. 3 is a schematic view showing a manufacturing process of a conventional multilayer printed wiring board.
20 内層回路基板 22 銅箔 23 キャリア 24 銅箔付きキャリア 25 (一次)積層体 26、35 孔 27、36 めっき層 28 IVH 29 導電ペースト 30、38、39、42 回路 31 IVH層 34 二次積層体 37 スルーホール 20 inner layer circuit board 22 Copper foil 23 career 24 Carrier with copper foil 25 (Primary) laminate 26, 35 holes 27, 36 Plating layer 28 IVH 29 Conductive paste 30, 38, 39, 42 circuits 31 IVH layer 34 Secondary stack 37 Through hole
Claims (3)
介してキャリア付き銅箔の銅箔面を重ねて積層し積層体
を得る工程 b.前記積層体を貫通するIVH用孔を所定位置に穿設
し、この貫通孔内を含む積層体の全面をめっきして積層
体の表裏をIVHにて電気的接続する工程 c.前記積層体の両面のキャリアを該キャリア上のめっ
き層と共に除去する工程d.前記キャリアを除去した積
層体の全面をめっきする工程 e.前記積層体の両面に回路を形成する工程 を有することを特徴とするプリント配線板の製造方法。1. A. Step of obtaining a laminate by stacking and laminating the copper foil surfaces of the carrier-added copper foil on both surfaces of the inner layer circuit board via prepregs b. IVH hole penetrating the laminate is formed at a predetermined position, the entire surface of the laminate including the inside of the through hole is plated, and the front and back of the laminate are electrically connected by IVH. C. Removing the carriers on both sides of the laminate together with the plating layers on the carrier d. A step of plating the entire surface of the laminate from which the carrier has been removed e. A method of manufacturing a printed wiring board, comprising a step of forming circuits on both surfaces of the laminate.
介してキャリア付き銅箔の銅箔面を重ねて積層し一次積
層体を得る工程 b.前記一次積層体を貫通するIVH用孔を所定位置に
穿設し、この貫通孔内を含む一次積層体の全面をめっき
して表裏をIVHにて電気的接続する工程 c.前記一次積層体のキャリア除去面側に回路を形成し
IVH層を得る工程 d.前記IVH層の回路形成面と片面にキャリア付き銅
箔を積層した回路基板の他方の面とをプリプレグを介し
て積層し二次積層体を得る工程 e.前記二次積層体を貫通する孔を所定位置に穿設する
工程 f.前記二次積層体の両面のキャリアを該キャリア上の
めっき層と共に除去する工程 g.前記二次積層体の全面をめっきして表裏を電気的接
続する工程 h.前記二次積層体の両面に回路を形成する工程を有す
ることを特徴とするプリント配線板の製造方法。2. A. A step of stacking the copper foil surfaces of the carrier-added copper foil on both surfaces of the inner layer circuit board via prepregs to obtain a primary laminate b. Step of forming an IVH hole penetrating the primary laminate at a predetermined position, plating the entire surface of the primary laminate including the inside of the through hole, and electrically connecting the front and back sides by IVH. C. Step of forming a circuit on the carrier removal surface side of the primary laminate to obtain an IVH layer d. A step of laminating a circuit forming surface of the IVH layer and the other surface of a circuit board having a copper foil with a carrier laminated on one surface via a prepreg to obtain a secondary laminate e. Step of forming a hole penetrating the secondary laminated body at a predetermined position f. Removing the carriers on both sides of the secondary laminate together with the plating layers on the carrier g. Step of plating the entire surface of the secondary laminate to electrically connect the front and back sides h. A method of manufacturing a printed wiring board, comprising a step of forming a circuit on both surfaces of the secondary laminate.
ことを特徴とする請求項1または2に記載のプリント配
線板の製造方法。3. The method for manufacturing a printed wiring board according to claim 1, wherein the IVH is filled with a conductive paste.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001368204A JP2003168868A (en) | 2001-12-03 | 2001-12-03 | Method for manufacturing printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001368204A JP2003168868A (en) | 2001-12-03 | 2001-12-03 | Method for manufacturing printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2003168868A true JP2003168868A (en) | 2003-06-13 |
Family
ID=19177829
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001368204A Pending JP2003168868A (en) | 2001-12-03 | 2001-12-03 | Method for manufacturing printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2003168868A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7597929B2 (en) | 2006-02-10 | 2009-10-06 | Shinko Electric Industries Co., Ltd. | Method of manufacturing a wiring substrate |
KR100952483B1 (en) | 2008-02-18 | 2010-04-13 | 삼성전기주식회사 | Printed Circuit Board and Manufacturing Method Thereof |
JP2011210811A (en) * | 2010-03-29 | 2011-10-20 | Kyocer Slc Technologies Corp | Method for manufacturing wiring board |
-
2001
- 2001-12-03 JP JP2001368204A patent/JP2003168868A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7597929B2 (en) | 2006-02-10 | 2009-10-06 | Shinko Electric Industries Co., Ltd. | Method of manufacturing a wiring substrate |
KR100952483B1 (en) | 2008-02-18 | 2010-04-13 | 삼성전기주식회사 | Printed Circuit Board and Manufacturing Method Thereof |
JP2011210811A (en) * | 2010-03-29 | 2011-10-20 | Kyocer Slc Technologies Corp | Method for manufacturing wiring board |
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