JPH05343658A - Package structure for solid-state image sensor - Google Patents
Package structure for solid-state image sensorInfo
- Publication number
- JPH05343658A JPH05343658A JP4176085A JP17608592A JPH05343658A JP H05343658 A JPH05343658 A JP H05343658A JP 4176085 A JP4176085 A JP 4176085A JP 17608592 A JP17608592 A JP 17608592A JP H05343658 A JPH05343658 A JP H05343658A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor chip
- solid
- mounting portion
- protrusions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ビデオカメラや電子ス
チールカメラ等に搭載される固体撮像装置に係わり、特
にそのパッケージ構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device mounted on a video camera, an electronic still camera or the like, and more particularly to a package structure thereof.
【０００２】[0002]
【従来の技術】図４は従来の固体撮像装置を示す側断面
図である。図示した固体撮像装置５０において、５１は
パッケージであり、このパッケージ５１には実装部５２
が設けられている。また、パッケージ５１の実装部５２
には所定量の接着剤５３が塗布されており、この接着剤
５３を介して半導体チップ５４が接合されている。一
方、パッケージ５１の両側にはそれぞれリード片５５が
配置されており、各々のリード片５５はワイヤ５６を介
して半導体チップ５４の電極パッド（不図示）に接続さ
れている。さらに、パッケージ５１の上側開口部には透
明ガラス５７が接合されている。2. Description of the Related Art FIG. 4 is a side sectional view showing a conventional solid-state image pickup device. In the illustrated solid-state imaging device 50, reference numeral 51 denotes a package, and the package 51 has a mounting portion 52.
Is provided. In addition, the mounting portion 52 of the package 51
A predetermined amount of adhesive 53 is applied to the semiconductor chip 54, and the semiconductor chip 54 is bonded via the adhesive 53. On the other hand, lead pieces 55 are arranged on both sides of the package 51, and each lead piece 55 is connected to an electrode pad (not shown) of the semiconductor chip 54 via a wire 56. Further, transparent glass 57 is joined to the upper opening of the package 51.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら上記従来
の固体撮像装置５０においては、パッケージ５１の実装
部５２が平面で形成されているため、チップ基準面（裏
面）に対する実装部５２の平行度、並びに実装部５２全
体の平面度が高精度に得られず、半導体チップ５４が傾
いて実装されてしまうという問題があった。また、同じ
理由から、半導体チップ５４を固定するための接着剤５
３の厚みがその粘度や塗布ムラによって不均一になり、
これが半導体チップ５４に傾きを生じさせる一つの要因
になっていた。However, in the above-mentioned conventional solid-state imaging device 50, since the mounting portion 52 of the package 51 is formed as a flat surface, the parallelism of the mounting portion 52 with respect to the chip reference surface (back surface), and There is a problem in that the flatness of the entire mounting portion 52 cannot be obtained with high accuracy, and the semiconductor chip 54 is inclined and mounted. For the same reason, the adhesive 5 for fixing the semiconductor chip 54 is also used.
The thickness of 3 becomes uneven due to its viscosity and coating unevenness,
This has been one of the factors that cause the semiconductor chip 54 to tilt.
【０００４】その結果、固体撮像装置５０を光学系に組
み込んだ際に、光学系の基準軸Ｚに対する半導体チップ
５４の垂直度が許容範囲から外れてしまい、組み合わせ
後に垂直度の補正作業を必要としたり、そのための補正
機構が必要になるなど、種々の不都合が生じていた。そ
こで、半導体チップ５４の実装精度を上げる対策として
は、パッケージ５１の実装部５２に研磨加工を施して上
述の平行度及び平面度を高める方法が考えられる。しか
し、この方法では、実装部５２全面を均一にしかも精度
良く研磨するのに多大な手間と時間を必要とし、大幅な
コストアップを招いてしまう。As a result, when the solid-state image pickup device 50 is incorporated into an optical system, the verticality of the semiconductor chip 54 with respect to the reference axis Z of the optical system deviates from the permissible range, and it is necessary to correct the verticality after combination. In addition, various inconveniences have occurred, such as a need for a correction mechanism for that. Therefore, as a measure for increasing the mounting accuracy of the semiconductor chip 54, a method of polishing the mounting portion 52 of the package 51 to increase the parallelism and flatness can be considered. However, this method requires a great deal of time and labor to uniformly and accurately polish the entire surface of the mounting portion 52, resulting in a significant cost increase.
【０００５】本発明は、上記問題を解決するためになさ
れたもので、半導体チップを精度良く実装させることが
できる固体撮像装置のパッケージ構造を提供することを
目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to provide a package structure of a solid-state imaging device in which a semiconductor chip can be mounted with high accuracy.
【０００６】[0006]
【課題を解決するための手段】本発明は、上記目的を達
成するためになされたもので、上面に撮像面が形成され
た半導体チップと、この半導体チップを実装するための
実装部が設けられたパッケージと、このパッケージの両
側に配置されたリード片とを有する固体撮像装置におい
て、上記パッケージの実装部に所定高さの突起が形成さ
れ、且つこの突起は少なくとも上記半導体チップの外周
部を支持する状態に配置されたものである。The present invention has been made in order to achieve the above object, and is provided with a semiconductor chip having an image pickup surface formed on the upper surface and a mounting portion for mounting the semiconductor chip. In a solid-state imaging device having a package and lead pieces arranged on both sides of the package, a protrusion having a predetermined height is formed on a mounting portion of the package, and the protrusion supports at least an outer peripheral portion of the semiconductor chip. It is arranged in the state of doing.
【０００７】[0007]
【作用】本発明の固体撮像装置のパッケージ構造におい
ては、パッケージの実装部に形成された突起の先端部に
半導体チップが載置され、この状態で半導体チップが接
着剤により接合されるため、突起の高ささえ一定に形成
されていれば半導体チップが傾いて実装されることはな
い。さらに、パッケージの実装部に塗布された接着剤
は、半導体チップの裏面側に確保される空間にスムース
に流れ広がるので、接着剤の粘度や塗布ムラによって半
導体チップが傾くこともない。In the package structure of the solid-state image pickup device of the present invention, the semiconductor chip is placed on the tip of the protrusion formed on the mounting portion of the package, and the semiconductor chip is bonded by the adhesive in this state. As long as the height is constant, the semiconductor chip will not be inclined and mounted. Further, the adhesive applied to the mounting portion of the package smoothly spreads in the space secured on the back surface side of the semiconductor chip, so that the semiconductor chip does not tilt due to the viscosity of the adhesive or uneven application.
【０００８】[0008]
【実施例】以下、本発明の固体撮像装置のパッケージ構
造に係わる実施例を図面に基づいて詳細に説明する。図
１は本発明の一実施例を示す側断面図であり、図２は同
部分平面図である。図示した固体撮像装置１０におい
て、１１はパッケージであり、このパッケージ１１に
は、半導体チップを実装するための実装部１２が設けら
れている。また、パッケージ１１の両側にはそれぞれリ
ード片１３が配置されており、各々のリード片１３は、
ワイヤ１４を介して半導体チップ１５の電極パッド（不
図示）に接続されている。さらに、半導体チップ１５の
上面には図示せぬ撮像面が形成されており、この撮像面
の上方を覆うかたちでパッケージ１１の上側開口部に透
明ガラス１６が接合されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments relating to the package structure of the solid-state image pickup device of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a side sectional view showing an embodiment of the present invention, and FIG. 2 is a partial plan view of the same. In the illustrated solid-state imaging device 10, reference numeral 11 denotes a package, and the package 11 is provided with a mounting portion 12 for mounting a semiconductor chip. Further, the lead pieces 13 are arranged on both sides of the package 11, and each lead piece 13 is
It is connected to the electrode pad (not shown) of the semiconductor chip 15 via the wire 14. Further, an imaging surface (not shown) is formed on the upper surface of the semiconductor chip 15, and the transparent glass 16 is bonded to the upper opening of the package 11 so as to cover the imaging surface.
【０００９】本実施例のパッケージ構造においては、パ
ッケージ１１の実装部１２に所定高さの突起１７、１７
・・が形成されている。これらの突起１７は、例えばパ
ッケージ１１の実装部１２において略半球状に突出して
形成されており、半導体チップ１５の外周部に８個と、
その中心部に１個位置するようにして、合計９個で構成
されている。この構成により突起１７は少なくとも半導
体チップ１５の外周部を支持する状態となる。また、こ
れらの突起１７は、パッケージ１１の基準面（下面）１
１ａからの高さが全て一定となるように、パッケージ１
１と一体に形成されている。In the package structure of this embodiment, the mounting portion 12 of the package 11 has protrusions 17, 17 having a predetermined height.
.. is formed. These protrusions 17 are formed, for example, in a substantially hemispherical shape on the mounting portion 12 of the package 11, and eight protrusions 17 are formed on the outer peripheral portion of the semiconductor chip 15.
A total of nine pieces are arranged so that one piece is located in the central portion. With this configuration, the protrusion 17 is in a state of supporting at least the outer peripheral portion of the semiconductor chip 15. Further, these protrusions 17 serve as the reference surface (lower surface) 1 of the package 11.
Package 1 so that the height from 1a is constant.
It is formed integrally with 1.
【００１０】続いて、上記構造をなすパッケージ１１の
実装部１２に半導体チップ１５を実装する場合の手順に
ついて、図１、図２を参照しながら説明する。まず第１
の工程では、パッケージ１１の実装部１２に、ディスペ
ンサ等を使用して接着剤１８を塗布する。続いて第２の
工程では、コレット或いは専用チャックを用いて半導体
チップ１５をピックアップし、そのままパッケージ１１
の上方まで半導体チップ１５を移動させる。次いで第３
の工程では、パッケージ１１の実装部１２に形成された
各突起１７の先端部に半導体チップ１５を載置するとと
もに、所定の圧力で半導体チップ１５を突起１７側に押
圧する。この時、実装部１２に塗布された接着剤１８
は、半導体チップ１５の裏面側に確保される空間に流れ
広がる。以上の手順によって半導体チップ１５はパッケ
ージ１１に実装される。Next, a procedure for mounting the semiconductor chip 15 on the mounting portion 12 of the package 11 having the above structure will be described with reference to FIGS. First of all
In the step (2), the adhesive 18 is applied to the mounting portion 12 of the package 11 using a dispenser or the like. Subsequently, in the second step, the semiconductor chip 15 is picked up by using a collet or a dedicated chuck, and the package 11 is directly used.
The semiconductor chip 15 is moved to above. Then the third
In the step (1), the semiconductor chip 15 is placed on the tip of each protrusion 17 formed on the mounting portion 12 of the package 11, and the semiconductor chip 15 is pressed toward the protrusion 17 with a predetermined pressure. At this time, the adhesive 18 applied to the mounting portion 12
Flows and spreads in a space secured on the back surface side of the semiconductor chip 15. The semiconductor chip 15 is mounted on the package 11 by the above procedure.
【００１１】このように本実施例のパッケージ構造にお
いては、パッケージ１１の実装部１２に形成された突起
７の先端部に半導体チップ１５が載置されるとともに、
その実装部１２に塗布された接着剤１８によって半導体
チップ１５が接合される。したがって、基準面１１ａか
ら各突起１７までの高ささえ一定に形成されていれば、
半導体チップ１５が傾いて実装されることはない。さら
に、半導体チップ１５の実装時には、実装部１２に塗布
された接着剤１８が半導体チップ１５の裏面側に確保さ
れる空間にスムースに流れ広がるため、接着剤１８の粘
度や塗布ムラによって半導体チップ１５が傾くこともな
い。以上のことから、半導体チップ１５はパッケージ１
１の実装部１２に精度良く実装されるようになる。As described above, in the package structure of this embodiment, the semiconductor chip 15 is placed on the tip of the protrusion 7 formed on the mounting portion 12 of the package 11, and
The semiconductor chip 15 is joined by the adhesive 18 applied to the mounting portion 12. Therefore, as long as the height from the reference surface 11a to each protrusion 17 is constant,
The semiconductor chip 15 is never mounted tilted. Furthermore, at the time of mounting the semiconductor chip 15, the adhesive 18 applied to the mounting portion 12 smoothly spreads into the space secured on the back surface side of the semiconductor chip 15, so that the semiconductor chip 15 may have viscosity or uneven application. Does not tilt. From the above, the semiconductor chip 15 is the package 1
The first mounting unit 12 can be mounted with high accuracy.
【００１２】なお、本実施例のパッケージ構造では、半
導体チップ１５が９個の突起１７で支持されるようにな
っているが、実装部１２に形成される突起１７の構成と
しては、例えば図２においてハッチングが描かれた４個
の突起１７だけで半導体チップ１５の外周部の４隅を支
持するものであってもよい。つまり、突起１７の構成と
しては、半導体チップ１５を安定且つ確実に支持できる
ものであればよく、そのための条件としては、少なくと
も突起１７が半導体チップ１５の外周部を支持すること
が挙げられる。In the package structure of this embodiment, the semiconductor chip 15 is supported by the nine protrusions 17, but the protrusions 17 formed on the mounting portion 12 can be configured, for example, as shown in FIG. It is also possible to support the four corners of the outer peripheral portion of the semiconductor chip 15 only by the four projections 17 with hatching. That is, the structure of the protrusion 17 may be one that can stably and reliably support the semiconductor chip 15, and the condition therefor is that at least the protrusion 17 supports the outer peripheral portion of the semiconductor chip 15.
【００１３】よって、本発明に係わるパッケージ構造と
しては、突起１７の形状や数に限定されないことは言う
までもなく、その他の実施例としては、例えば図３に示
すように、パッケージ１１の実装部１２に細長半円状の
突起１７、１７・・を形成するとともに、これらの突起
１７で半導体チップ１５の外周部を支持するようにした
ものなど、種々の態様が考えられる。Therefore, it goes without saying that the package structure according to the present invention is not limited to the shape and the number of the protrusions 17, and as another embodiment, for example, as shown in FIG. Various modes are conceivable, such as forming elongated semicircular projections 17, 17 ... And supporting the outer peripheral portion of the semiconductor chip 15 by these projections 17.
【００１４】[0014]
【発明の効果】以上、説明したように本発明によれば、
半導体チップがパッケージに精度良く実装されるように
なるため、固体撮像装置を光学系に組み込んだ後に位置
的な精度補正を行う必要がなくなる。よって、そのため
の時間と手間が取り除かれるとともに、その補正作業用
に設けられる機構も不要となってトータル的な部品点数
の削減が可能となる。また、より高い実装精度を得るた
めに研磨加工を行う場合でも、突起の先端部を研磨する
だけで済むようになるため、精度的にも、またそれに費
やされる手間や時間の面でも非常に有利である。As described above, according to the present invention,
Since the semiconductor chip is mounted on the package with high accuracy, it is not necessary to perform positional accuracy correction after incorporating the solid-state imaging device into the optical system. Therefore, the time and labor for that are eliminated, and the mechanism provided for the correction work is not required, and the total number of parts can be reduced. Also, even when polishing is performed to obtain higher mounting accuracy, it is only necessary to polish the tip of the protrusion, which is very advantageous in terms of accuracy and the labor and time spent there. Is.
【図１】本発明の一実施例を示す側断面図である。FIG. 1 is a side sectional view showing an embodiment of the present invention.
【図２】図１の部分平面図である。FIG. 2 is a partial plan view of FIG.
【図３】他の実施例を説明する図である。FIG. 3 is a diagram illustrating another embodiment.
【図４】従来例を示す側断面図である。FIG. 4 is a side sectional view showing a conventional example.
１０ 固体撮像装置 １１ パ
ッケージ １２ 実装部 １３ リ
ード片 １５ 半導体チップ １７ 突
起10 Solid-state imaging device 11 Package 12 Mounting part 13 Lead piece 15 Semiconductor chip 17 Protrusion
Claims (1)
と、この半導体チップを実装するための実装部が設けら
れたパッケージと、このパッケージの両側に配置された
リード片とを有する固体撮像装置において、 前記パッケージの実装部に所定高さの突起が形成され、
且つ前記突起は少なくとも前記半導体チップの外周部を
支持する状態に配置されたことを特徴とする固体撮像装
置のパッケージ構造。1. A solid-state imaging device having a semiconductor chip having an imaging surface formed on an upper surface thereof, a package provided with a mounting portion for mounting the semiconductor chip, and lead pieces arranged on both sides of the package. In, the protrusion of a predetermined height is formed in the mounting portion of the package,
Further, the package structure of the solid-state imaging device, wherein the protrusion is arranged so as to support at least an outer peripheral portion of the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4176085A JPH05343658A (en) | 1992-06-09 | 1992-06-09 | Package structure for solid-state image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4176085A JPH05343658A (en) | 1992-06-09 | 1992-06-09 | Package structure for solid-state image sensor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05343658A true JPH05343658A (en) | 1993-12-24 |
Family
ID=16007459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4176085A Pending JPH05343658A (en) | 1992-06-09 | 1992-06-09 | Package structure for solid-state image sensor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05343658A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5773323A (en) * | 1995-04-27 | 1998-06-30 | Lg Semicon Co., Ltd. | Package for solid state image sensing device and method for manufacturing thereof |
| WO2001059828A2 (en) * | 2000-02-14 | 2001-08-16 | Epcos Ag | Building component with constant distorsion-free bonding, and method for bonding |
| WO2002091474A1 (en) * | 2001-05-09 | 2002-11-14 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device and its manufacturing method |
| JP2006332686A (en) * | 2006-07-03 | 2006-12-07 | Matsushita Electric Ind Co Ltd | Solid-state imaging device |
| JP2007180164A (en) * | 2005-12-27 | 2007-07-12 | Fujifilm Corp | Package for solid state imaging element |
| JP2008205057A (en) * | 2007-02-19 | 2008-09-04 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
| US7586529B2 (en) | 2003-10-23 | 2009-09-08 | Panasonic Corporation | Solid-state imaging device |
| JP2013240043A (en) * | 2012-05-14 | 2013-11-28 | Samsung Electro-Mechanics Co Ltd | Apparatus and method of manufacturing camera module |
| JP2017011217A (en) * | 2015-06-25 | 2017-01-12 | シャープ株式会社 | Solid-state imaging device and camera module |
-
1992
- 1992-06-09 JP JP4176085A patent/JPH05343658A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5773323A (en) * | 1995-04-27 | 1998-06-30 | Lg Semicon Co., Ltd. | Package for solid state image sensing device and method for manufacturing thereof |
| WO2001059828A2 (en) * | 2000-02-14 | 2001-08-16 | Epcos Ag | Building component with constant distorsion-free bonding, and method for bonding |
| WO2001059828A3 (en) * | 2000-02-14 | 2002-02-28 | Epcos Ag | Building component with constant distorsion-free bonding, and method for bonding |
| WO2002091474A1 (en) * | 2001-05-09 | 2002-11-14 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device and its manufacturing method |
| US7125754B2 (en) | 2001-05-09 | 2006-10-24 | Shindengen Electric Manufacturing Co., Ltd. | Semiconductor device and its manufacturing method |
| US7719585B2 (en) | 2003-10-23 | 2010-05-18 | Panasonic Corporation | Solid-state imaging device |
| US7586529B2 (en) | 2003-10-23 | 2009-09-08 | Panasonic Corporation | Solid-state imaging device |
| JP2007180164A (en) * | 2005-12-27 | 2007-07-12 | Fujifilm Corp | Package for solid state imaging element |
| JP2006332686A (en) * | 2006-07-03 | 2006-12-07 | Matsushita Electric Ind Co Ltd | Solid-state imaging device |
| JP2008205057A (en) * | 2007-02-19 | 2008-09-04 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
| JP2013240043A (en) * | 2012-05-14 | 2013-11-28 | Samsung Electro-Mechanics Co Ltd | Apparatus and method of manufacturing camera module |
| CN103428413A (en) * | 2012-05-14 | 2013-12-04 | 三星电机株式会社 | Apparatus and method for manufacturing camera module |
| JP2017011217A (en) * | 2015-06-25 | 2017-01-12 | シャープ株式会社 | Solid-state imaging device and camera module |
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