JPH052882A - Large-scale integrated circuit - Google Patents

Abstract

PURPOSE:To attain a higher integration scale and to allow a memory wigh high reliability by forming the elements of a 1st circuit responding with signals of large amplitude to such a large size of high breakdown voltage and forming the elements of a 2nd circuit responding with the output signals of this circuit to a small size. CONSTITUTION:The MOS transistor (MOST) Qm of the 1st circuit part 40 consisting of a memory array and direct peripheral cirucits affecting the high integration scale is formed to the small size and the MOST QP of the 2nd circuit part 50 consisting of the indirect peripheral cirucits is formed to the large size. The operation of the MOST QP can be made by setting the power source voltage VCC from the outside of the chip at an operating voltage and the operation of the Qm can be made by convering the voltage VCC to a low voltage VDP. The voltage VDP is lowered as well if the gate oxide film t0X1 is made small. The operating speed of the 1st circuit part 40 occupying the greater part on the operating speed of the memory is thus increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high density integrated circuit, and more particularly to an integrated circuit suitable for a high density semiconductor memory.

[0002]

2. Description of the Related Art Conventionally, for high integration of a semiconductor memory, JP-A-51-104276 discloses a technique in which two kinds of gate oxide film thicknesses and two kinds of gate region surface concentrations are combined. In addition, Japanese Patent Laid-Open No. 50-119543 discloses that
A technique has been proposed in which the Si surface of the memory array portion is ion-implanted at a high concentration to make the channel length of the transistors in the memory array portion smaller and the diffusion layer interval smaller to improve the degree of integration. However, when the dimensions of circuit elements such as transistors are reduced by such a technique, the withstand voltage against dielectric breakdown of these circuit elements must be reduced. Therefore, the power supply voltage applied to these circuit elements or the signal voltage generated by these circuits needs to be reduced along with the reduction in the size of the circuit elements.

[0003]

On the other hand, from the viewpoint of user's ease of use, the voltage applied from the outside (voltage applied to the power supply pin of the package of the memory LSI) depends on the size of the transistor constituting the memory. There is a desire to keep it constant. Therefore, it is not desirable to reduce the voltage applied from the outside. Therefore, the above-mentioned conventional technique cannot realize a highly integrated memory that can use a high external voltage. This applies not only to the memory but also to other integrated circuits.

It is therefore an object of the present invention to provide a highly integrated circuit which can use a high external voltage, has a small size, and internally has a circuit element which operates at a low operating voltage.

[0005]

Therefore, in the present invention,
We paid attention to the following features of the integrated circuit.

(1) Generally, in an integrated circuit, a circuit element connected to an external input terminal must have a high breakdown voltage.
This is to prevent the element from being destroyed even when a high voltage is externally supplied to this terminal or when an electrostatic force is generated. Therefore, it is practically necessary to increase the size of the circuit element connected to this external input terminal.

(2) In the integrated circuit, as described above, the internal circuit has a small size, and in order to prevent the breakdown even if the breakdown voltage becomes small, a power supply voltage supplied to them or a voltage generated by them is generated. It is desirable to reduce the value of the signal voltage applied. In consideration of these points, in the present invention, the circuit element in the first circuit that responds to a signal with a large amplitude is formed to have a large size so as to have a high withstand voltage, and responds to the output signal of this circuit. The circuit element of the second circuit is formed in a small size for high integration. Further, a power supply circuit including a large-sized circuit element for supplying a high first power supply voltage and supplying a second power supply voltage lower than the first power supply voltage to the second circuit is provided. The first power supply voltage is input to the circuit of 1,
It is configured to generate an internal signal having a voltage corresponding to the second power supply voltage. The second circuit receives the second power supply voltage and is activated by this internal signal,
Is configured to output a signal having a voltage having a magnitude corresponding to the power supply voltage.

[0008]

As a result, the first and second circuits have no problem with respect to withstand voltage, and the second circuit is formed of circuit elements having a small size. Since the area occupied by the second circuit is large, high integration can be achieved in the integrated circuit as a whole.

[0009]

EXAMPLES The present invention will be described below according to examples.

FIG. 1 is a cross-sectional view of a memory chip for a dynamic memory composed of a P-type substrate 10 to show the concept of this method. N-type MOS transistor (MOST) Q
a gate oxide film t _ox2 for _p MOST, is thicker than the gate oxide film t _ox1 of Q _m, MOST, the drain D _p of Q _p, high drain voltage, for example, an external voltage V _cc (e.g. 5 v) is supplied, The internal power supply voltage generation circuit 3 to which this voltage V _cc is input to the drain D _m of the MOST and Q _m
0 (which is actually formed in substrate 10) provides a voltage V _DP (eg, 3.5V) that is less than V _cc .

The external voltage V _cc is input to the substrate voltage generating circuit 20, where the bias voltage of the substrate 10 is, for example, -3.
V is generated. Although the circuit 20 is shown outside the substrate 10, it is actually provided inside the substrate 10. Normally, the degree of integration of the memory is defined by peripheral circuits (direct peripheral circuits) directly connected to the memory array, such as a memory array and a sense amplifier (not shown) that drives the memory array or amplifies a minute signal output from the memory array. ) Of the first circuit unit 40. Therefore MOST of this part, the dimensions of Q _m is desirable to reduce. This dimension is M
In general, it is possible to reduce the operating voltage by lowering the operating voltage in view of the breakdown voltage of OST and Q _m , the hot electrons, the substrate current, and the like. Here, MOS
The gate oxide film t _ox1 of T and Q _m is thinned, the drain voltage is set to a voltage V _DP lower than V _cc , and the channel length is shortened.
It is possible to reduce the dimensions of ST and Q _m . Of course, the maximum value of the voltage of the gate G _m also needs to be generally V _DP . On the other hand, the other circuit, that is, the second circuit section 50 including a circuit (indirect peripheral circuit) that directly controls the peripheral circuit, occupies about 10% of the entire chip area. You don't even have to use it. Rather, the indirect peripheral circuit is connected to an external input terminal, and therefore must have a sufficiently high electrostatic breakdown voltage. Generally for this purpose thickened gate oxide film t _ox2 the individual MOST Q _p, it is necessary to use a large MOST Q _p of Ban no dimension (e.g. channel length). Here, the gate oxide film t _ox2 thicker than the gate oxide film t _ox1, In conjunction to the long channel length, drain voltage of Q _p, and V _cc higher than the drain voltage V _DP of Q _m. Of course, the maximum voltage of the gate G _p is generally V _cc
And The sources S _p and S _m of Q _p and Q _m are held at the ground potential. As shown in FIG. 1, the size of the MOST Q _m of the first circuit section 40 including the memory array and the direct peripheral circuit, which affects the high integration degree, is reduced, and the MOST Q _m of the second circuit section 50 including the indirect peripheral circuit is reduced. The size of _p is made larger. By doing this also, the power supply voltage from the outside of the chip: I'll be the operating voltage (V _cc, for example 5V), MOST, Q _p becomes operational. Further, Q _m can be operated at a lower operating voltage (V _DP : eg 3.5 V) by converting V _cc into a voltage within the chip. Generally, the lower the operating voltage, the more V
It is desirable that _{th be} also low in terms of high speed. This point, M
According to the general characteristics of OST, if the gate oxide film _tox becomes smaller, _Vth also becomes lower, so that the operating speed of the first circuit portion, which occupies a large part in the operating speed of the memory, can be increased.

Therefore, this method is also convenient in terms of speeding up. It is obvious that V _th can be adjusted appropriately by the ion implantation technique depending on the application.

When this method is applied to an actual dynamic N-MOS memory consisting of one-transistor type memory cells, it can be used more effectively by taking some considerations. An example of this is shown in FIG. This is a memory having a folded data line. To this memory, an external power supply voltage _Vcc (5V) is input, a substrate bias generating circuit 20 of about -3V and an external power supply voltage _Vcc are input,
The internal power supply generation circuit 30 for generating the internal power supply voltage V _{DP of} 3.5 V and the DC voltage V'of about 3 V, the external power supply voltage V _cc , the external addresses Ai to Aj, Ai 'to Aj', and the external control signal are used. The received internal address signals a _{i to} a _j , a
_i ′ to a _j ′, internal control pulses φ ₀ , φ ₁ , φ ₃ , φ _x , φ _y
And an indirect peripheral circuit for outputting the voltages V _DP , V ′, address signals a _{i to} a _j , a _i ′ to a _j ′, control pulses φ ₀ , φ ₁ , φ.
Memory hole MA and direct peripheral circuit 40 controlled by ₃
Consists of. The direct peripheral circuits include an X decoder XD, a Y decoder YD, a precharge circuit PC, and a sense up SA.
And are included. In FIG. 2, the circuit 50A
In the indirect peripheral circuit 50, a portion for generating a word line drive pulse is separately extracted and shown. In this circuit 50A, the pulses φ ₁ ′ and φ _x ′ are circuits generated in the indirect peripheral circuit 50.

Here, both the external address signal and the external control signal input to the indirect peripheral circuit 50 are signals that change between the external power supply voltage V _cc and the ground potential. Of the pulses output from this circuit 50, φ ₁ , a _{i to} a _j ,
Each of a _i ′ to a _j ′ is a pulse that changes between the internal power supply voltage V _DP and the ground potential, and the pulse φ ₀ is a precharging transistor Q _p , Q _{p −} , Q _DP , Q _YO , Q _XO. , The pulse having a level higher than V _DP + V _th is taken as the threshold value of V _th , and the pulse φ ₃ is the transistor Q _A , Q.
_This pulse has a level lower than V _DP by the threshold value of _A. The pulses φ _x and φ _y are pulses having a level of about 1.5 V _DP .

The operation of this circuit is as follows.

The read signal voltage appearing on the data line D from the selected memory cell MC in the memory array MA according to the stored information is read by the sense amplifier SA using the reference voltage appearing on the data line D from the dummy cell DC. Although it is determined as 1 ”or“ 0 ”, the process is as follows. That is, each data line pair D, D- is precharged to V _DP (<V _cc ) by the precharge signal φ ₀ , then φ ₀ is turned off, and D, D- is held at V _DP . The amplitude of the precharge signal φ _c is affected by the variation in V _th of the MOSTs Q _p and Q _p in the data line precharge circuit PC, and the precharge levels of D and D are unbalanced (( This is the equivalent noise at the time of reading) of sufficiently greater than V _DP to prevent (> V _DP + V
_th ) _Any amplitude will do. Next, the memory cell M on the selected word line W which is cleared to OV at the time of precharging by Q _CL
To read C, a word activation pulse φ _x ′ (with an amplitude of the external power supply voltage V _cc ) is applied to the word voltage generation circuit WG. At this time, since the decoder XD has already been selected by the addresses a _{i to} a _j , the word driver MOST
The gate of Q _XS is held at a high level, ie Q
_XS is on. The word voltage generating circuit WG receives the pulse φ _x ′ and outputs the pulse φ _x having the amplitude V _DP , and the output φ _x is transmitted from W ′ to W as it is.
In this case, depending on the purpose, for example, a read voltage to D¯ from MC to the voltage applied to the W to the large to the large, via the boot la strap capacitor C _B phi ₁ (Fuhaba V
_DP ) is also applied. The booster circuit VU receives the pulse φ ₁ ′ (width V _cc ) and outputs the pulse φ ₁ . The boosted voltage in this case is determined by the parasitic capacitance of the sum of C _B , W ′ and W and the amplitude of φ ₁ , but can be about 0.5 V _DP . Therefore, a pulse having an amplitude of about 1.5 V _DP is generated on W. At the same time, although omitted in FIG. 2, a pulse voltage of 1.5 V _DP is generated also in the dummy word line DW by a circuit of almost the same type. As a result, the storage voltage corresponding to the information held in the storage capacitance C _s appears in D as a minute voltage determined by the relationship between C _s and the data line capacitance.

On the other hand, the intermediate level (reference voltage) of the signal voltage appearing at D in correspondence with the stored information always appears at D, and these are amplified by the sense amplifier SA. Incidentally amplification to precharge the data line D, is precharged V _DP -V _th (where V _th from D¯ is Q _A, Q _A
It is carried out by setting φ ₃ which is V _th ) to OV. The thus-amplified differential signals of D and D are selected by the predetermined Y decoder YD by the addresses a _i ′ to a _j ′ (thus, the gate voltage of Q _YS is at a high level), and φ _y (amplitude) by to 1.5V _DP) is applied, a common I / O to the data line pair, and is output to the I / O¯¯¯ data output.

Now, in the ordinary memory, as described above,
When high integration is performed while maintaining _Vcc at 5V, that is, when MC is reduced, the breakdown voltage naturally becomes a problem, but as in the present invention, it is directly related to the integration degree. Memory cells MC, dummy cells DC, and direct peripheral circuits and MOSTs laid out at substantially the same pitch as MC
(For example, SA, PC, XD, YD, Q _XS , Q _YS ,
If the operating voltage of Q _D , Q _D ￣, DC, Q _CL ) is lowered, the problem of withstand voltage will be eliminated, and it will be possible to lay out in a small area by using small size elements (MOST, capacitors, resistors). . On the other hand, the area of the indirect peripheral circuit is small in view of the entire chip area. Therefore, a device having a larger size can be used so as to operate stably even at a high operating voltage. That is, a highly integrated memory that operates at a high voltage when viewed from the outside becomes possible.

Next, specific examples for reducing the size will be listed below.

The oxide film is selectively thinned; generally, as the gate oxide film thickness of the MOST becomes smaller, normal transistor characteristics are exhibited even with a smaller channel length L. Therefore, in order to reduce the channel length and lay out in a small area, it is necessary to reduce the gate oxide film. However, as described above, the breakdown voltage (between the drain and the source) decreases. Therefore, it is important to properly use the operating voltage according to L as in the present invention. Further, in MOS LSI, this thin oxide film is often used as a capacitor (C _B , C _{S in} FIG. 2). Also in this case, a thin gate oxide film can be used to form a capacitor having a large value in a small area, so that such a capacitor can be used in a place operating at a low voltage. Therefore, it is essentially important for high integration that the thin oxide film is used in the memory array or directly in the peripheral circuit section.

The L and V _{th of the} MOST having a small gate oxide film are made smaller; as the thin oxide film can be selectively used, as is clear from the general characteristics of the MOST, the L and V _th are small. You can Therefore, by actively using this possibility, high integration can be achieved without reducing the speed. This is because the thin oxide region has a low operating voltage, and if it is left as it is, it operates only at a low speed. Fortunately, however, L and _Vth can be made small in this region. This is because positively reducing L or V _th leads to high-speed operation.

Element isolation can be more easily performed in a region operated at a low voltage. Therefore, the element isolation width can be reduced by this amount. In other words, high integration is possible. Alternatively, the interlayer film thickness that contributes to element isolation characteristics can be thinned.
Therefore, it is flattened by this amount, and wiring (for example, Al)
The number of wire breakages will decrease and the yield will increase.

That is, as shown in FIG.
It is assumed that, for example, an Al wiring WA runs above the ST Q _m1 and Q _{m2 and} a high voltage is applied to it. Further, it is assumed that a high voltage is applied to the drain D _m1 of one MOST and a low voltage is applied to the source S _m2 of the other MOST. Q _m1 and Q
_The element separation width L _p that can electrically separate _m2 depends on the voltage V _DP applied to the WA and the film thickness t _DP of the film, and is generally V _DP.
The smaller is, the larger is t _OP , the smaller can be L _P.
Therefore, if the present invention is adopted under the condition that t _{OP is} constant, V _DP is small, so that L _P can be made small and high integration can be achieved. Further, since t _OP can be made small under the condition that L _{P is} constant, a cross section having a small step can be formed. Therefore, the breakage of Al can be reduced,
High yield.

In order to further enhance the advantages of the above method, the depth x _j of the diffusion layer in the main part of the memory array and the direct peripheral circuit is made smaller than that of the indirect peripheral circuit part.
That is, the smaller x _j is, the smaller size MOST can be used.

Incidentally, it may be considered that, depending on the operating state, the element size in the peripheral circuit may be selectively increased to be used in some cases. For example, a high voltage of 1.5 V _DP is applied between the drain and the source of Q _CL or the like, so that it is necessary to devise a large size MOST.

In the sense amplifier SA, Q _A and Q _A
If the value is made too small, these threshold values may not match due to manufacturing variations, resulting in memory cell read noise. Therefore, it is necessary to selectively increase the dimensions of Q _A and Q _A.

A specific example of dimensions in the memory of FIG. 2 is as shown in FIG. The combination of these various dimensions can be selected according to the application.

For example, it is possible to maximize the advantages of the present invention by using two types of x _j and t _OP as shown in the figure, but it is also possible to use one type for ease of manufacturing.

Further, FIG. 3 shows the word voltage generating circuit W of FIG.
The circuit configurations of G and the voltage boosting circuit VU are shown. Both WG and VU are depletion type N-channel MOST (V
_th = −3.5V) Q _DN and a conventional pulse generation circuit PG using the source voltage of this MOST as the power supply voltage. The amplitude of the input pulse voltages φ _x ′ and φ ₁ ′ is V _cc , but the voltage at point a is held at −3.5 V by the depletion MOST and Q _DN . Pulse generator PG in the word voltage generating circuit WG in response to the rise of the input pulse phi _x ', and outputs a pulse phi _x voltage V _DP (= 3.5V). Further, thereafter, the pulse generating circuit PG in the voltage boosting circuit VU outputs the pulse φ ₁ of the voltage V _DP in response to the rising of the input pulse φ ′ (the swing width V _cc ). As a result,
Line W'is boosted by the action of capacitance C _B ~
It becomes 1.5V _DP . (FIG. 4) The output voltage of the circuit PG is V
_{Even if cc} is changed (for example, 5 → 8V), MOST Q
It is almost constant because it is uniquely determined by the _{Vth of DN} (FIG. 5). That is, as shown in FIG. 5, when the external voltage V _cc changes, when the external voltage V _cc is below a predetermined voltage and above the predetermined voltage, that is, below the threshold voltage V _th The fact that the internal power supply voltage V _DP changes with respect to the change of the external voltage V _cc is different from the case of the voltage V _th or more. This means that even if V _cc is excessively large, the memory array MA and the fine MOSTs frequently used directly around the memory array MA are protected from destruction.

As in the circuits WG and VU shown in FIG. 3, a D-type NMOS and a pulse generator are used to respond to an input pulse having a swing equal to the external voltage V _cc , and a voltage V _DP smaller than this voltage V _DP. The method of generating the amplitude equal to is not limited to these circuits WG and VU, and is also used for the indirect peripheral circuit 60.

Since the transistor Q _DN shown in FIG. 3 receives the V _cc power supply and outputs the V _DP voltage, the internal power supply voltage generation circuit 30 can also be constructed using this transistor.
That is, as shown in FIG. 3, in the portion generating V _DP , V _cc to which the drain and gate are respectively applied, and V to which the ground potential is applied.
If a depletion type transistor of _th = −3.5V is used, the power supply voltage V _DP can be obtained from its source,
Further, the source of the transistor having the same structure is connected to the drain and the gate of the enhancement type transistor at the portion where V'is generated, and the threshold value of this transistor is set to 0.
If the voltage is 5V, the power supply voltage V'can be obtained from the source of this transistor.

Next, a specific example of the method of applying the power supply voltage converted into the low voltage will be described.

FIG. 8 shows a common voltage converter 30 for all indirect peripheral circuits (PG1, PG2, etc.) in the chip.
This is a method of supplying a voltage V _DP from The output pulses from these PGs are φ ₁ ′, φ _x ′, φ ₃ , a _{i to} a _{j in FIG} .
a _i ′ to a _j ′. In this case, if the current supply capacity of 30 is sufficient, even if each pulse generating circuit constituting the indirect peripheral circuit drives each load capacitance C ₁ , C ₂ , C ₃ , the power fluctuation of V _DP is not a particular problem. Absent. However, if the current supply capacity of 30 is small, V _DP fluctuates each time each pulse generation circuit PG operates, and this fluctuation lasts for a long time if the power supply line capacitance C _DP is large. That is, a plurality of PGs interfere with each other in the form of fluctuations in V _DP , and an ideal pulse waveform cannot be obtained from each PG. FIG. 9 solves this drawback. Since a voltage converter is provided for each PG, the above drawbacks are eliminated. Actually, FIG. 3 was a concrete example.

FIG. 10 shows an application method in the case where PGs that require low-voltage output pulses and PGs that do not require them are used together. For example, the output pulse of PG1 or PG4 is applied to a direct peripheral circuit or memory array which requires a low voltage pulse, as described above.

FIG. 11 shows another embodiment for reducing mutual interference via V _DP , which is a drawback of FIG. When each PG forming the indirect peripheral circuit is classified, a certain plurality of PGs are classified.
It can be classified into a plurality of PG groups according to the operating time zone, such that it operates only in a certain time zone and the other plurality of PGs operate only in different time zones. For example, like a dynamic memory of the address multiplex system, two PG groups that operate corresponding to _two externally applied clocks (φ ₁ , φ ₂ ) exist inside the chip. case, the voltage converter, phi _1, the use every phi _2, via a V _DP, interference between PG related to phi ₁ and phi ₂ are not. Alternatively, as shown in FIG. 12, the input signal φ
PG that operates when is ON (PG1, PG2, PG
3, ...) and PG (PG1 ', P that operates when OFF)
G2 ′, PG3 ′, ...), that is, two types of PG groups that operate in accordance with the logical state of φ, and connect the voltage converter 30 to each.
As an example of the dynamic memory, when φ is ON, it corresponds to the time zone in which the memory operation is performed, and when φ is OFF, it corresponds to the time zone in which the precharge operation is performed.

Next, the circuit system of the voltage converter itself will be described with reference to an embodiment other than FIG. In order to simplify the description, a dynamic pulse generator circuit that is normally used will be described. For details of the operation of this pulse circuit PG, see
It is written in the annual conference No.69 of the Institute of Electronics and Communication Engineers Semiconductor and Materials Division. The outline will be described with reference to FIG. That is, when the input phi ₁ is applied, the gate voltage of Q _D are discharged from the high potential to the low potential, Q _D goes to OFF, a high potential (bootstrap capacitor from the gate voltage of the low potential simultaneously Q _L to) to become the result charged V _cc or more high potential using, Q _L becomes oN, the output phi ₀ is a high potential from the low potential (OV) (V _cc). In order to obtain a low-voltage output pulse in such a circuit form, there is an embodiment as shown in FIG. However, in some cases, as shown in FIG. 14, when a pulse φ _i having an amplitude equal to V _cc , which is an external power supply, is input, the amplitudes of the outputs φ _{01 to} φ ₀₄ of each PG are also V _cc. Only specific outputs (eg φ ₀₁ ′, φ ₀₄ ′) are additionally output, and pulses of lower voltage amplitude (V _DP ) are also output,
In some cases, it may be desired to directly apply this low voltage pulse to the peripheral circuit or the memory array. The 15th and 16th embodiments of the voltage converter in this case are shown.

FIG. 15 shows an example in which inverters Q _L ′ and Q _D ′ for φ ₀ ′ are added in parallel to the output stage of FIG. Q _DN
Is the same depletion MOST as in FIG. See also FIG.
6 is the same depletion MO as in FIG. 3 in series with Q _D and Q _L
In this example, STQ _DN is added and output is extracted from both ends. Obviously, φ ₀ has an amplitude up to V _cc, and φ ₀ ′ which is regulated by the threshold voltage of the depletion MOST and has an amplitude of V _DP is obtained at the same time as φ ₀ .

FIG. 17 shows an example in which φ ₀ ′ in FIG. 16 is boosted as shown in FIG.

Although the pulse generating circuit that takes a low level as described above has been described, a highly reliable integrated circuit cannot be obtained as it is. That is, in a normal integrated circuit, after the final manufacturing process, a voltage sufficiently higher than the power supply voltage used in normal operation is intentionally applied to each transistor in the chip, which is called an aging test. Reliability is guaranteed by finding a transistor that is likely to fail at an early stage.
However, as described in this example, if the voltage is made constant, even if the external power supply voltage is increased, a sufficiently high voltage is not applied to each transistor, so a sufficient aging test is impossible. Therefore, only in the case of the aging test, for example, the gate voltage of the depletion MOST may be set higher than the ground potential. By doing so, as is clear from the well-known property of the depletion MOST, the output voltage increases as the gate voltage increases. As a means for applying during aging, as shown in FIG. 18, the gate voltage of the depletion MOST Q _DN may be set to the ground potential during normal operation and to an appropriate voltage V _E during aging, as shown in FIG. FIG. 19 shows a concrete example thereof. That is, the gates of the multiple Q _{DNs in} the chip are connected to ground in the chip by the resistors R in the chip. On the other hand, the gate is connected to the pin PN of the package via the bonding pad PD. If this pin is left open during normal operation, the gate of each Q _DN will be at ground potential.
If a voltage is applied to this pin during aging, Q _DN
Therefore, a voltage as high as that applied to the source can be obtained.

FIG. 20 shows an embodiment for achieving the same effect by adjusting the phase relationship of the external clock applied to the chip only during aging, without providing the aging pin as described above. For example, in dynamic RAM,
As is well known, two types of external clock RAS
(Row Address Strobe) and CAS (Column Address Strobe)
obe) operates at the proper timing. Usually RA
Since it is not used in a combination in which S is at a high level and CAS is at a low level, this combination may be used at the time of aging. That is, by taking the logic as shown in FIG.
Only in the above combination, the gate of Q _DN can have a potential higher than the ground potential.

Although the above embodiment is a depletion MOST embodiment for convenience of explanation, it is obviously possible to use an enhanced MOST. However, in order to obtain the same effect as that of the depletion MOST, it is necessary to apply a constant voltage to the gate. For example, in order to obtain a constant voltage V _DP to the source of the enhancement MOST is a constant voltage V _DP + V _th to the gate of the enhancement MOST: it is necessary to apply the (V _th the threshold voltage of enhancement MOST). Since it is generally possible to keep V _DP + V _th constant on the chip regardless of fluctuations in the external power supply voltage, the above enhanced MOST can be used.

[0042]

As described above, a highly integrated and highly reliable memory becomes possible. It is obvious that this system can be applied to not only the dynamic MOS memory but also, for example, a static MOS memory, a bipolar memory and other memories, or an integrated logic circuit to which the above concept can be applied.

[Brief description of drawings]

FIG. 1 is a chip cross-sectional view of an example in which the present invention is applied to a DRAM.

FIG. 2 is a circuit diagram of an example in which the present invention is applied to a DRAM.

FIG. 3 is an embodiment of a word voltage generating circuit and a voltage boosting circuit in FIG.

FIG. 4 is a diagram for explaining the operation of FIG.

FIG. 5 is a diagram showing a relationship between inputs and outputs of an internal power supply generation circuit.

FIG. 6 is a diagram illustrating an element configuration.

FIG. 7 is an example of specific dimensions of an element.

FIG. 8 is an example of a supply system of a voltage converter.

FIG. 9 is an example of a supply system of a voltage converter.

FIG. 10 is an example of a supply system of a voltage converter.

FIG. 11 is an example of a supply system of a voltage converter.

FIG. 12 is an example of a supply system of a voltage converter.

FIG. 13 is a diagram showing a dynamic pulse generation circuit.

FIG. 14 is a diagram showing an embodiment of a pulse generation circuit of the present invention.

FIG. 15 is a diagram showing an embodiment of the voltage converter in FIG.

16 is a diagram showing an example of the voltage converter in FIG. 14. FIG.

17 is an example in which FIG. 16 is applied to FIG.

FIG. 18 is a diagram showing a voltage application method during aging.

FIG. 19 is an example showing a method for applying a voltage during aging.

FIG. 20 is an example showing a method for applying a voltage during aging.

[Explanation of symbols]

V _DP ... Internal power supply voltage, Q ... Transistor, MC ... Memory cell, SA ... Sense amplifier, PC ... Precharge circuit.

Claims (19)

[Claims] 1. A semiconductor integrated circuit having a plurality of voltage drop means and a plurality of circuits on a chip, wherein the plurality of voltage drop means have a function of generating a predetermined internal voltage equal to or lower than an external power supply voltage. The rate of change of the internal voltage with respect to the change of the external power supply voltage changes at a predetermined voltage, the plurality of voltage drop means are connected to the plurality of circuits, and the plurality of circuits are provided at predetermined times. A semiconductor integrated circuit which operates in a band. 2. The semiconductor integrated circuit according to claim 1, wherein
A semiconductor integrated circuit, wherein other circuits do not operate during a time period when a specific circuit among the plurality of circuits is operating. 3. The semiconductor integrated circuit according to claim 1, wherein when the external power supply voltage is equal to or lower than the predetermined voltage, the rate of change of the internal voltage with respect to the external voltage is the external voltage. A semiconductor integrated circuit characterized by being approximately equal to the rate of change of the power supply voltage. 4. The semiconductor integrated circuit according to claim 1, wherein when the external power supply voltage is equal to or higher than the predetermined voltage, the rate of change of the internal voltage with respect to the external voltage is the predetermined voltage. A semiconductor integrated circuit characterized by having a smaller rate of change when the voltage is less than or equal to the voltage. 5. The semiconductor integrated circuit according to claim 1, wherein, when the external power supply voltage is equal to or higher than the predetermined voltage, the rate of change of the internal voltage with respect to the external voltage is substantially zero. Is a semiconductor integrated circuit. 6. The semiconductor integrated circuit according to claim 1, wherein the plurality of circuits output a first circuit and a signal having an amplitude larger than the output of the first circuit. And a third circuit to which the signal with the large amplitude is input, the semiconductor integrated circuit. 7. The semiconductor integrated circuit according to claim 6, wherein the third circuit includes a plurality of data lines, a plurality of word lines, and desired intersections of the plurality of data lines and the plurality of word lines. And a memory element disposed in the memory element, the larger voltage appearing on the data line is generated with reference to the internal voltage generated by the first voltage drop means. .. 8. The memory according to claim 7, wherein the second circuit has a function of supplying a voltage to the word line, and the larger voltage appearing on the word line is the second voltage. A memory which is generated on the basis of an internal voltage generated by the voltage drop means. 9. The semiconductor integrated circuit according to claim 7, wherein a voltage having a larger voltage appearing on the data line is smaller than a voltage having a larger voltage appearing on the word line. A semiconductor integrated circuit characterized by the above. 10. The semiconductor integrated circuit according to claim 7, wherein the plurality of circuits include a fourth circuit that selects the data line, and the fourth circuit includes the fourth circuit. A semiconductor integrated circuit to which a second voltage drop means is connected. 11. The semiconductor integrated circuit according to claim 7, wherein the first circuit is a circuit that supplies a voltage to the data line. 12. The semiconductor integrated circuit according to claim 11, wherein the first circuit is a sense amplifier that amplifies a signal from the memory element. 13. The semiconductor integrated circuit according to claim 12, wherein the voltage drop means is connected to a power supply terminal of the sense amplifier. 14. The semiconductor integrated circuit according to claim 7, wherein the plurality of circuits include a fifth circuit for precharging the data line, and the fifth circuit includes: A semiconductor integrated circuit, to which a voltage generated based on the internal voltage is supplied. 15. The semiconductor integrated circuit according to claim 7, wherein the memory device is a dynamic RAM device. 16. The semiconductor integrated circuit according to any one of claims 1 to 15, wherein the substrate voltage of the chip is
A semiconductor integrated circuit, which is generated based on an external power supply voltage. 17. The semiconductor integrated circuit according to claim 1, wherein the output voltage of the first voltage drop means and the output voltage of the second voltage drop means are equal voltages. A semiconductor integrated circuit characterized by being present. 18. The semiconductor integrated circuit according to claim 1, wherein the plurality of circuits include a first circuit group to which a first voltage drop means is connected, and a second voltage group. A second circuit group to which the lowering means is connected;
The semiconductor integrated circuit is characterized in that the circuit group (1) does not operate while the second circuit group (2) is operating. 19. The semiconductor integrated circuit according to claim 1, wherein the predetermined time zone is controlled by an external signal.