JPH07111825B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, it can raise the potential of a selected word line at high speed and with high amplitude, and also by a signal from the outside. The present invention relates to a semiconductor memory device capable of reducing power consumption by controlling a voltage generation circuit.

[Background of the Invention]

Conventionally, as a circuit using a bipolar transistor and a MIS transistor, there is a semiconductor device disclosed in JP-A-59-25423.

FIG. 17 is a block diagram of the semiconductor device. The operation of the circuit and its problems will be described with reference to FIG. In this semiconductor device, a combination circuit of CMOS (complementary MOS) and a bipolar transistor 7, a combination circuit of an MIS transistor 6 and a bipolar transistor 8 are connected in parallel. Hereinafter, description will be given assuming that the voltage Vss of the negative power supply is 0V. When the potential of the input terminal 1 is 0V, the P-channel MIS transistor 4 turns on, a current flows through the base of the bipolar transistor 7, and the bipolar transistor 7 turns on.
On the other hand, the bipolar transistor 8 has a base potential of 0V.
Therefore, it does not turn on. As a result, a current flows to the output terminal 2 and the potential of the output terminal 2 rises. The potential of the output terminal 2 finally becomes a value obtained by subtracting the base-emitter forward voltage V _BE of the bipolar transistor 7 from the voltage Vcc of the positive power supply. Thus, in the conventional circuit shown in FIG. 17, the potential of the output terminal 2 does not rise to the voltage Vcc of the positive power supply.

As a semiconductor device including a circuit in which a MIS transistor and a bipolar transistor are combined, there is a drive circuit disclosed in Japanese Patent Laid-Open No. 59-8431 in addition to the above-mentioned circuit.

FIG. 18 is a diagram showing the structure of the semiconductor device. 18th
The circuit shown in the figure is a combination of an inverted CMOS circuit and a bipolar transistor connected in parallel between input and output terminals. While the circuit of FIG. 17 described above outputs an inverted signal of the input, the circuit of FIG. 18 outputs an affirmative signal in phase with the input. That is, when input terminal 10 goes high, MI
S transistor 13 turns on and bipolar transistor 17
A current flows through the base of this bipolar transistor 17
Turns on. On the other hand, since the P-channel MIS transistor 15 is turned off and the N-channel MIS transistor 16 is turned on, the base potential of the bipolar transistor 18 becomes 0V and the bipolar transistor 18 is turned off. As a result, a current flows to the output terminal 11 and the potential of the output terminal 11 rises. At this time, the potential of the output terminal 11 is higher than the threshold voltage V _T of the N-channel MIS transistor 13 from the positive power source Vcc.
The base-emitter forward voltage V _BE of the bipolar transistor 17 is increased to a value V cc −V _T −V _BE . Thus, the output level of the circuit shown in FIG. 18 becomes even lower than the output level shown in FIG.

As described above, the conventional circuit cannot raise the output level sufficiently. If the output level is low, the input level of the next-stage circuit will be low, and the operation of the next-stage circuit will be slow, and the high-speed performance of the bipolar transistor cannot be fully exhibited in the LSI as a whole. Also, this problem is
This becomes remarkable when the conventional device is miniaturized and it becomes necessary to lower the power supply voltage. Therefore, it is desired to have a circuit capable of producing a sufficiently large output level while fully utilizing the high driving capability of the bipolar transistor.

[Object of the Invention]

An object of the present invention is to provide a semiconductor memory device having a circuit capable of obtaining a large output level at high speed and reducing power consumption by studying these conventional problems. .

[Outline of Invention]

In a typical embodiment of the present invention, in a semiconductor memory device having a word line drive circuit (XD) for supplying a voltage to a selected word line, the word line drive circuit (XD) has an operation reference voltage of the circuit. (V _A) voltage greater than _{(V A + Vα + V bE} )
Further, the word line drive circuit (XD) supplies a voltage (V _A + V α) higher than the operation reference voltage (V _A ) to the selected word line.

In addition, in particular, the voltage generating means is provided with a plurality of voltage generating circuits (CP1, CP2) having a common output, and some of the voltage generating circuits (CP2) are Signals from outside the semiconductor memory device (chip select signal,
The operation / non-operation is controlled by the CAS signal or the RAS signal) (see FIGS. 12 to 16).

As described above, since the power supply of the word line drive circuit is set to a voltage higher than the operation reference voltage, the potential of the selected word line can be increased faster and higher than that of the word line drive circuit that uses the conventional operation reference voltage as the power supply. The amplitude can be raised. In addition, in the standby state, etc., some of the voltage generation circuits can be controlled to the inactive state by a signal from outside the semiconductor memory device, resulting in significant power consumption compared to the case where all the voltage generation circuits are constantly operating. Down is possible.

Example of Invention

First, the operation principle of the semiconductor circuit technology (hereinafter referred to as the present technology), which is the basis of the present invention, will be described with reference to FIGS. 1 to 11, and then the semiconductor of the present invention will be described with reference to FIGS. 12 to 16. An embodiment of the storage device will be described.

FIG. 1 is a configuration diagram of a semiconductor device for explaining the principle of the present technology. FIG. 1 exemplifies the case of a one-input and one-output circuit. In FIG. 1, D is a combinational circuit including a bipolar transistor and a MIS transistor, and C
Is a pre-stage circuit for controlling the circuit D, A is a terminal for applying a voltage serving as a reference for the operation of the circuit C, and B _{1 to} Bn are terminals for applying a voltage serving as a reference for the operation of the circuit D. Further, E is an input terminal of the circuit C, G is an output terminal of the circuit D, and a connection line F
Is a signal line for transmitting a signal for controlling the circuit D from the circuit C.

In the present technology, by setting at least one of the voltages applied to B _{1 to} Bn higher than the voltage applied to the terminal A, the level of the signal output to the terminal G is
The level is higher than the level of the signal input to the circuit D via the signal line F. As a result, it is possible to generate a high level signal while still utilizing the high speed of the bipolar transistor.

Here, the voltage applied to the terminal A or the terminals B _{1 to} Bn may be of a constant level or may be a pulse as required, and in some cases, a plurality of voltages may be used as a reference for the circuit C. May be supplied as. Further, the signal line F may be plural. The present technology is not limited to FIG. 1 and can be applied to a multi-input / multi-output circuit. However, in order to simplify the description, the same configuration as that in FIG. The original application example is shown below. A CMOS inverter as shown in FIG. 2 is used as the circuit C. In FIG. 2, terminal A
Is connected to the positive power supply V _A , but is not limited to this, as described above.

FIG. 3 is a configuration diagram of a semiconductor device showing a first application example of the present technology. In this application example, a pulse voltage serving as a reference for the operation of the circuit D is applied to the terminal B ₁ , and a level higher than the operation reference voltage V _A of the preceding circuit C is output to the output terminal G.

The operation of FIG. 3 will be described below using the voltage waveforms of FIG. When the input terminal E is set to 0V, the potential of the signal line F becomes high level by the pre-stage circuit C shown in FIG. 2 and becomes steady at the voltage V _A. Although the potential of the terminal B ₁ at this time is the summer and V _A in Figure 4, the threshold voltage of the P-channel MIS transistor 25 as _{V T25, V A + | V} T25 | P -channel MIS set below The transistor 25 should be turned off. When the potential of the signal line F becomes high level, the N-channel MIS transistor 27 turns on, the base of the bipolar transistor 26 becomes 0V, the bipolar transistor 26 turns off, and N
Since the channel MIS transistor 29 is turned on, the potential of the output terminal G becomes 0V. Next, the potential of the input terminal E is raised to V _A , the potential of the signal line F is lowered (see FIG. 2), and the potential of the terminal B ₁ is raised to V _A or higher. At this time, P
The channel MIS transistor 25 turns on, the N channel MIS transistor 27 turns off, a base current flows through the bipolar transistor 26, and the bipolar transistor 26 turns on.
Since the N-channel MIS transistor 29 is turned off, current flows to the output terminal G and the potential of the output terminal G rises. The potential of the output terminal G reaches the potential obtained by subtracting the base-emitter forward voltage V _BE from the potential of the base of the bipolar transistor 26, so that the desired output level is V _A + Vα.
When (Vα ≧ 0), the potential of terminal B ₁ is V _A + Vα + V _BE
A desired output level can be obtained at the output terminal G by boosting to.

The potential of the input terminal E to transition to 0V, and when returning the potential of the terminal B ₁ to V _A, the potential of the signal line F as described above is increased to V _A, bipolar transistor 26 is turned off, N-channel MIS
The transistor 29 is turned on and the potential of the output terminal G becomes 0V. The potential of B ₁ at this time is V _A + | V
It can be set to any value as long as it is _T25 | or less, for example, it can be equal to V _A.

As described above, according to this application example, by arbitrarily setting the potential of B ₁ when the signal input from the signal line F is a low voltage, the high speed performance of the bipolar transistor can be maintained, A high voltage output can be obtained.

Note that, in FIG. 3, the N-channel MIS transistor 29 for lowering the potential of the output terminal G can be configured as shown by 30 in FIG. That is, the circuit D has a configuration in which a combination of reverse CMOS and bipolar transistors is connected in parallel. In this case, the current flowing through the N-channel MIS transistor 40 is amplified by the bipolar transistor 42, so that the potential of the output terminal can be lowered at high speed. However, in this case, the potential of the output terminal G is equal to that of the bipolar transistor 42.
Since it is limited by the forward voltage between the base and emitter of, it does not completely drop to 0V. When it is necessary to completely reduce the potential of the output terminal G to 0 V, the N-channel MIS shown in FIG.
30 in FIG. 5 may be installed in parallel with the transistor 29. Note that, in FIG. 5, the P-channel MIS transistor 41 is for accumulating at the base of the bipolar transistor 42 and extracting the electric charge when the signal line F becomes 0 V, to surely turn off the bipolar transistor 42. It is a thing.

FIG. 6 is a configuration diagram of a semiconductor device showing a second application example of the present technology.

The difference between this application example and the application example of FIG. 3 is that in FIG. 3, the collector of the bipolar transistor 26 and the source of the P-channel MIS transistor 25 are connected to the terminal B ₁ , whereas in FIG. Only the source of the P-channel MIS transistor 51 is connected to the terminal B ₁ and the bipolar transistor 52
It is not connected to the collector terminal B _{2 of} . That is, in the configuration of FIG. 6, only the base current of the bipolar transistor 52 needs to be supplied from the terminal B ₁ . Therefore, as compared with the case where both the base and collector currents of the bipolar transistor 26 are supplied from B ₁ as shown in FIG.
Since the load on the circuit that drives the terminal B ₁ is reduced, high-speed operation is possible. Other operations are the same as those in FIG.

In FIG. 6, the collector of the bipolar transistor 52 is connected to the terminal B ₂ , and the potential can be set independently of the terminal B ₁ that supplies the current to the base 55. Therefore, by keeping the potential of the terminal B ₂ higher than the potential of the base 55 of the bipolar transistor 52, it is possible to reliably prevent the bipolar transistor 52 from being saturated. For that purpose, a pulse voltage having an amplitude equal to or higher than the base voltage may be applied to B ₂ in synchronization with the potential fluctuation of the base 55, or the potential of B ₂ may be kept at a constant value higher than the upper limit of the potential of the base 55. May be. In the latter case, a high voltage is applied between the collector and the emitter of the bipolar transistor 52 when the signal line F goes high and the potential of the output terminal G changes to low level. Since it is grounded by the MIS transistor 53, the breakdown voltage of the bipolar transistor 52 is determined by BV _CES (collector-emitter breakdown voltage when the base is grounded), which is higher than when the base is in a floating state. Absent. In FIG. 6, when there is a possibility that the bipolar transistor 52 may be temporarily deeply saturated due to fluctuations in the power supply voltage, etc., the terminals B ₁ and B ₂ are connected as shown in FIG.
A diode DIO may be inserted between the two to prevent the bipolar transistor 52 from being deeply saturated by causing a current to flow through the diode when the potential of the terminal B ₁ becomes abnormally high. In FIG. 6, the circuit 30 for lowering the potential of the output terminal G may be composed of only the MIS transistor 29 as shown in FIG. 3 if necessary, or as shown in FIG. As described above, the transistors may be used, or both may be used in parallel.

FIG. 7 is a configuration diagram of a semiconductor device showing a third application example of the present technology.

The major difference between the circuits of FIGS. 7 and 6 is that in FIG. 6, the circuit D outputs an inverted signal of the signal input from the signal line F, that is, the so-called inverter operation, whereas the circuit of FIG. The point is that a so-called non-inverter operation is performed, which outputs a signal in phase with the input F.

In FIG. 7, a bipolar transistor 83 supplies a current to the output terminal G to raise the potential of the terminal G, and an N-channel MIS transistor 84 causes a current to flow from the output terminal G to Vss. The other MIS transistors are transistors for lowering the potential of G, and the other MIS transistors are for controlling ON / OFF of the bipolar transistor 83 and the MIS transistor 84.

The operation of the application example of FIG. 7 will be described below using the voltage waveforms of FIG.

In the figure, for simplification of explanation, it is assumed that the potential of the terminal B ₂ is kept at a constant value higher than the upper limit value of the potential of the base 76 of the bipolar transistor 83. A pulse voltage synchronized with the potential fluctuation of 76 may be applied. When the potential of the input terminal E is V _A , the potential of the signal line F becomes 0 V by the circuit C, so that the N-channel MIS transistor 75 is turned off, the P-channel MIS transistor 80 is turned on, and the N-channel MIS transistor 81 is turned off. , 87 becomes V _A. As a result, N
Since the channel MIS transistor 77 turns on, the bipolar transistor 83 turns off, and the N-channel MIS transistor 84 turns on, the output terminal G becomes 0V. Next, when the input terminal E is lowered to 0V, the potential of the signal line F becomes V _A , and as a result, the gate 88 of the N-channel MIS transistor 75 becomes V _A
As a result, the N-channel MIS transistor 74 is charged to a voltage less the threshold voltage. On the other hand, since the P-channel MIS transistor 80 is off and the N-channel MIS transistor 81 is on, the potential of 87 becomes 0V and the N-channel MIS transistors 84 and 77 are off.

When the potential of the terminal B ₁ is boosted to V _A or higher in this state, the gate 88 of the MIS transistor 75 is charged in advance to a voltage obtained by subtracting the threshold voltage of the N-channel MIS transistor 74 from V _A. Channel MIS transistor 75
88 is boosted to a potential higher than B ₁ by the self-capacitance between the gate 88 and B ₁ of B ₁ . Therefore, the bipolar transistor 83
A current flows through the base 76 of the N-channel MIS transistor 75, the potential of the base 76 is not limited to the threshold voltage of the N-channel MIS transistor 75, and
_It rises to the potential of ₁ . As a result, the potential of the output terminal G rises to a value obtained by subtracting the base-emitter forward voltage V _BE of the bipolar transistor 83 from the potential of B ₁ . If the desired output level is V _A + Vα, the potential of B ₁ is
Set it to V _A + Vα + V _BE . Since the voltage of the gate 73 of the N-channel MIS transistor 74 is V _A ,
Turns off when gate 88 is boosted above V _A and gate 88
It also plays a role of preventing current from flowing backward to the signal line F. Next, when the potential of the input terminal E is raised to V _A and the potential of the terminal B ₁ is lowered, the signal line F becomes 0 V and the gate 87 becomes V _A, and the N-channel MIS is turned off while the bipolar transistor 83 is off. The transistor 84 is turned on and the output terminal G becomes 0V. At this time, the base 76 of the bipolar transistor 83
Is grounded through the N-channel MIS transistor 77, the withstand voltage of the bipolar transistor 83 becomes high,
Similar to the case of FIG. 6, the bipolar transistor 83 is less likely to be destroyed even when the high voltage of B ₂ is still applied. As described above, according to this application example,
It is possible to generate a high output level signal similar to the input.

As the circuit 86 for lowering the potential of the output terminal G, the circuit of FIG. 9 may be used if necessary.
The circuit shown in the figure and the N-channel MIS transistor 84 may be used in parallel. Also, if the like change in power supply voltage at risk of bipolar transistor 83 is temporarily deep saturation, as shown in FIG. 6, by connecting a diode between B ₁ and B _2, the B ₁ It suffices to prevent the potential from rising abnormally with respect to B ₂ .

FIG. 10 is a configuration diagram of a semiconductor device showing a fourth application example of the present technology.

The biggest difference between the circuits of FIGS. 7 and 10 is that the collector and base of the bipolar transistor 83 are electrically separated in FIG. 7, whereas the bipolar transistor 104 of FIG. The point is that the N-channel MIS transistor 103 is inserted between the collector and the base to supply the base current and the collector current from B ₂ .

The operation of this application example will be described below. It is assumed that the desired output level is V _A + Vα and the voltage of V _A + Vα + V _BE is applied to the terminal B ₂ . Here, V _BE is the forward voltage between the base and emitter of the bipolar transistor 104. With the terminal B ₁ at 0V, change the potential of the input terminal E from V _A
When the voltage is lowered to 0V, the gate of the N-channel MIS transistor 103 is changed from V _A to N-channel as in the case of FIG.
The MIS transistor 102 is charged to a potential less the threshold voltage. At this time, the N-channel MIS transistor 10
Since 5, 108 are off, a current flows from the terminal B ₂ to the base of the bipolar transistor 104, the bipolar transistor 104 is turned on, a current flows to the output terminal G, and the potential of the terminal G rises. The base potential of the bipolar transistor 104 is V _A −V _T102 −V, where the threshold voltages of the N channel MIS transistors 102 and 103 are V _T102 and V _T103 , respectively.
_Since it rises only up to _T103 and the potential of the output G further drops by V _BE , it is impossible to obtain an output level higher than V _A as it is. Therefore, while the gate 112 is charged, a pulse voltage is applied to the terminal B ₁ to boost the potential of the gate 112 to V _A + V α + V _BE + V _T103 or higher by the capacitor 100.
As a result, the base potential of the bipolar transistor 104 rises to V _A + Vα + V _BE, and the potential of the output terminal G reaches the desired output level V _A + Vα. In this application example,
The base potential of the bipolar transistor 104, since not rise only up to a level equal to the terminal B _2, the potential of the terminal B ₂ is never bipolar transistor 104 is saturated even dropped for some reason. Next, when the potential of the input terminal E is raised from 0V to V _A , the signal line F becomes 0V,
Since the N-channel MIS transistors 103 and 107 are turned off, the P-channel MIS transistor 106 is turned on, and the N-channel MIS transistor 105 is turned on, the bipolar transistor 1
04 is turned off, the N-channel MIS transistor 108 is turned on, and the potential of the output terminal G becomes 0V. Note that, also in this application example, the circuit 113 that causes the output terminal G to fall as necessary is
The configuration shown in FIG. 11 may be used, and the circuit shown in FIG.
The N-channel MIS transistor 108 of FIG. 10 may be connected in parallel as in the case of the application of FIG. In the above description, the potential of the terminal B ₂ is V _A + Vα +
Although the constant level of V _BE is set, a pulse voltage reaching 0 V to V _A + Vα + V _BE may be applied to the terminal B ₂ after the gate 112 is charged. At this time, since the potential of the gate 112 is boosted by the self-capacitance between the gate 112 of the N-channel MIS transistor 103 and the terminal B ₂ , the capacitor 100 and the terminal B ₁ are not always necessary.

Thus, in this application example, a bipolar transistor and
In the circuit including the MIS transistor, the high-driving capability of the bipolar transistor is maximized by setting the reference voltage of the operation to a value different from the reference voltage of the preceding circuit controlling the circuit. A semiconductor device having a high output amplitude equal to or higher than the reference voltage of the preceding circuit can be realized.

By the way, in the application examples described so far, it is necessary to apply the pulse voltage to the terminal B ₁ . There are various types of circuits that generate a pulse voltage, and their circuit configurations are well known. Therefore, although not explicitly shown here, for example, a circuit that generates a pulse voltage as shown in the voltage waveform of FIG. Ishihara, Miyazawa, Sakai, "Static with a cycle time of 50 ns
The 256K CMOS dynamic RAM with column mode ", Nikkei Electronics, February 11, 1985, PP243-263 has the circuit shown in Figure 7. In addition, in the application examples described so far, the P-channel MIS transistor (for example, the third
Some of the sources in 25) have a high potential, but the potential of the well of the P-channel MIS transistor is kept higher than the potential of the source, and an excessive forward current flows between the source and the well, so-called latch-up occurs. It goes without saying that it is necessary to prevent this. Further, in the above application example, there is an N-channel MIS transistor in which a high voltage is applied between the drain and the source (for example, 29 in FIG. 3). channel
Between the drain of the MIS transistor and the terminal to which the drain is connected, the N-channel MI whose gate potential is V _A
The voltage applied between the drain and source of the N-channel MIS transistor, which is problematic in terms of withstand voltage, may be reduced by inserting the S transistor in series.

The present technology has various possible uses, but is particularly suitable as a word driver for a dynamic semiconductor memory device. This is because in order to realize a high-speed dynamic semiconductor memory device, the selected word line is driven at high speed and with high amplitude, the signal voltage is increased to increase the S / N, and the accumulated charge is increased. This is because it is necessary to increase the soft error resistance. For the above circumstances, see ITOH, K.and
SUNAMI, H. "High density one-device"
dynamic MOS memory cells', IEEPROC., vol.130, Pt.IN
o.3, JUNE 1983, pp 127-135 for details.

Next, an embodiment of the present invention in which the present technology is applied to a word driver of a dynamic semiconductor memory device will be described.

FIG. 12 is a block diagram of a dynamic semiconductor memory, showing an N-bit memory cell array MCA and a peripheral circuit group.

The memory cell array MCA has i word lines WL and j.
The data lines DL are arranged in a crossed manner, and N memory cells MC are arranged at the intersections of the word lines and the data lines. Address input to the address buffer circuits ABX and ABY X _{0 to} Xn,
Y _{0 to} Ym are applied, and the output is transmitted to the decoder / driver circuits XD and YD. Of these decoder driver circuits XD, YD, the circuit XD drives the word line, and the circuit YD drives the write / read circuit RC, respectively, to write information to the selected memory cell MC in the memory cell array MCA, or Information is read from the memory cell MC. CC is a write / read control circuit, and this circuit CC has a chip select signal CS and a write operation control signal.
WE, the address buffer circuit ABX,
It controls ABY, decoder / driver circuits XD and YD, write / read circuit RC, and output circuit OC. The output circuit OC is a circuit for outputting the information read by the write / read circuit RC to the outside.

By applying the present technology described above to the decoder / driver circuit XD in the above configuration, it becomes possible to drive the level of the word line WL at high speed and with high amplitude, and a dynamic memory with high speed and high stability can be obtained. realizable.

In FIG. 12, the write / read circuit RC is
It is also possible to arrange a part thereof at the end of the merlicell array MCA on the side opposite to the decoder driver circuit YD and control the control signal from the decoder driver circuit YD through the memory cell array MCA. Further, in FIG. 12,
X system address input X _{0 to} Xn and Y system address input Y ₀ to
Ym and Ym are input from different input terminals.
77 ISSCC “Digest of Technical Papers” As described in “Digest of Technical Papers” P.12-13, these input terminals are shared and input with a time difference, so-called'address'. It is also possible to adopt the'multiplex method '.

In that case, the write / read control circuit may be driven by using signals for controlling address fetching, so-called RAS and CAS, instead of the chip select signal CS.

FIG. 13 is an embodiment diagram in which FIG. 12 is further embodied,
The memory cell array MCA and a part of the decoder driver circuit XD are shown in more detail.

In FIG. 13, DEC ₀ and DEC ₁ are decoders, WD ₀ and WD ₁ are word drivers, WL ₀ and WL ₁ are word lines, DL ₀ and ▲ ▼ are paired data lines, and MC ₀ and MC ₁ are memories. It is a cell. Note that E
Q is an equalizer for balancing the potentials of the data lines, and SA is a sense amplifier.

For the circuit configuration of the equalizer EQ and the sense amplifier SA, see 1984 ISSCC “Digest of Technical Papers”, P.276.
It is detailed here, so I will omit it here. The decoders DEC ₀ and DEC ₁ are the voltages applied to the terminals 130 and 137, respectively.
The word drivers WD ₀ and WD ₁ to which the present invention is applied, which operate based on V _A , are pulse voltages φ _X applied to terminals 154 and 157, voltage V _H applied to terminals 155 and 158, and terminals 156 and 159, respectively. It operates based on the pulse voltage φ _L. Here, it goes without saying that the voltage V _{H is set} to a potential that does not saturate the bipolar transistor 150 and the like.

The circuit configurations of the word drivers WD ₀ and WD ₁ are N-channel MIS transistors 151 and 165 in parallel with each other.
It is the same as the circuit D in FIG. 7 except that 152 and 166 are installed. The read operation in FIG. 13 will be described below using the voltage waveforms in FIG.

When starting the read operation, the data line pair D _L0 , ▲
Set ▼ to the equal potential of about 1/2 V _A by the equalizer EQ, and then put them in a floating state. On the other hand, when all the address buffer outputs A _X0 , A _X0 ... A _XR are all set to 0V, the precharge signal φ _{P is set} to 0V, and the gates of the N-channel MIS transistors 148 and 164 are respectively set to V _A from the N-channel MIS.
Precharge to the voltage obtained by subtracting the threshold voltage of the transistors 145 and 163. Although only two word drivers are shown here, in reality, all word drivers are precharged at the same time. Next, the precharge signal φ _P
Then, either the positive or negative of the address buffer output rises, and accordingly, a part of the N-channel MIS transistor in the decoder DEC is turned on to select one of the gates of the precharged MIS transistors. The gates of non-selected word drivers other than the word driver connected to the selected word line become 0V. Here, the case where the word line WL ₀ is selected is shown, and the gate of the N-channel MIS transistor 148 remains precharged. On the other hand, the gate of the N-channel MIS transistor 164 is 0V because it is not selected. Further, since the output of DEC ₁ is 0V, the non-selected word line WL ₁ is the same as N in the word driver WD _1.
The channel MIS transistor 165 is turned on and fixed at 0V. Next, the word latch signal φ _L is lowered and the signal φ _X
When 0 is raised from 0 V to V _A + Vα + V _BE , the gate of the N-channel MIS transistor 148 in WD ₀ is precharged so that the voltage is boosted and the potential of the word line WL ₀ is changed in the same manner as the circuit operation of FIG. 7. , V _A + V α. On the other hand, the gate of the N-channel MIS transistor 164 in WD ₁ is not boosted because it is 0V, the N-channel MIS transistor 164 is off, and the potential of the word line WL ₁ remains 0V. When the potential of the selected word line WL ₀ rises, the memory cell M
The N-channel MIS transistor 160 in C ₀ is turned on, a signal is read from the memory cell MC ₀ to the data line DL ₀ ,
A minute potential difference is generated between DL ₀ and the paired data line ▲ ▼.

The potential difference between the pair of data lines is amplified by the sense amplifier SA, information is rewritten in the memory cell, and is transmitted to the subsequent circuit. Next, set the pulse signal φ _X to 0V.
Fall in, the word line WL ₀ launched a latch signal φ _L
One that was lowered to 0V equipotential about 1 / 2V _A data line pair by the equalizer EQ, performs precharge to fall from the fall all the address buffer outputs a precharge signal phi _P to 0V Prepare for the next operation. In the above read operation, the word drivers WD ₀ , WD ₁ , ...
In addition, since the circuit shown in the above application example is applied, the potential of the selected word line can be raised at high speed and with high amplitude. As a result, the signal voltage and the storage voltage of the memory cell can be increased, and both high speed and high reliability can be achieved. In FIG. 13, the pulse signal φ
_As the circuit for generating _X , the circuit described in the Nikkei Electronics magazine referred to above may be used, or the application example of FIG. 6 may be used to further increase the speed. Further, in FIG. 13, a decoder is provided for each word driver, and the pulse signal φ _X is commonly applied to all word drivers. However, if necessary, one decoder is provided commonly to a plurality of word drivers and the decoder is Of course, various modifications such as decoding and applying a pulse signal of only one of the shared word drivers are possible.

Further, although the example in which the precharge voltage of the data line is set to V _A / 2 is shown here, the precharge voltage is not limited to this and can be arbitrarily set in the range of 0 to V _A.

In the above reading operation, the bipolar transistor in the non-selected word driver, for example, in WD ₁ 168
0V base, depending on the phi _X when the signal phi _X is 0V, also inserted MIS transistor between the base and Vss of the bipolar transistor when the signal phi _X rises, for example, by 167 in the WD ₁ Kept in. Therefore, since the breakdown voltage of the bipolar transistor is determined by BV _CES as described above, there is no problem even if the collector remains at the high voltage V _H.

By the way, the configuration of FIG. 13 requires two positive power sources, a power source for supplying the voltage V _A and a power source for supplying the voltage V _H. It is of course possible to separately supply these power supplies from the outside of the chip, but only one of them is supplied from the outside and the other is generated and supplied inside the chip with reference to this, or both are supplied to the chip. It can also be generated internally with reference to another power supply. Therefore, in FIG. 13 or the embodiment described above, one requiring two positive power supplies is supplied under one external positive power supply, for example, the higher one of the two voltages is directly supplied from the external positive power supply. For the lower ones, the voltage of the external positive power supply is set to Japanese Patent Application No. 56-168698 and Japanese Patent Application No. 57-220083.
It is also possible to lower the voltage and supply it by a voltage limiter circuit as shown in the specification or the like. In some cases, the lower one of the required two power supplies may be supplied from the external positive power supply, and the higher one may be supplied by raising the voltage of the external positive power supply by a circuit for boosting the voltage.

FIG. 15 is an embodiment of a booster circuit used in the present invention.

In this circuit, the voltage V _A is supplied from an external positive power supply to generate the high voltage V _H. The circuit of FIG. 15 is basically a so-called charge pump type booster circuit CP1 and CP2 arranged in parallel. The operation principle of the charge pump type booster circuit is well known and will not be described here. here,
The Zener diode 192 is for preventing current from leaking when the voltage at the terminal 194 rises above a desired level V _H and preventing further rise in potential, but it can be removed if unnecessary. Good. In addition, the Zener diode 19
Instead of 2, an ordinary diode or a plurality of MIS diode circuits in which the gates and drains of MIS transistors are connected in the forward direction may be used. Further, as CP ₁ and CP ₂ , an example is shown in which diodes composed of MIS capacitors and MIS transistors are connected in three stages. Generally, the number of stages is n, MIS
Transistor threshold voltage is V _T , φ _S1 ~ φ _S3 , φ _T1 ~ φ _T3
If the pulse amplitude of is V _A , the obtained voltage is about (n +
1) (V _A −V _T ), and the value of n may be selected according to the required value of V _H.

When this circuit is applied to FIG. 13, the current that must be supplied from the terminal 194 of FIG. 15 becomes large when the word line is selected. Therefore, it is possible to operate both CP1 and CP2 to obtain a large supply current during the active period of the dynamic semiconductor memory and to operate only CP1 during the standby period. As a result, a large output current can be obtained with low power consumption.

FIG. 16 is an example diagram of voltage waveforms of pulses applied to CP1 and CP2 in FIG.

In the figure, t1 is CP1 during standby.
Only works and top, ie CP during active time
An example is shown where both 1 and CP2 work. To synchronize the activation time of CP2 with the time of selecting the word line, for example, the chip select signal CS or RAS signal may be used. Further, in the case of an operation of continuously reading information of memory cells on one word line like a so-called page mode, it is necessary to keep the potential of the selected word line at a high potential for a long time. In this case, it goes without saying that CP2 may be activated using the CAS signal or the like even after the word line potential reaches the high level.

Although an example using two charge pump circuits is shown here, it goes without saying that more circuits may be used. Further, if the potential of the word line is raised very quickly, the potential of the terminal 194 in FIG. 15 may temporarily drop. In that case, to prevent saturation of the bipolar transistor whose terminal 194 is connected to the collector,
It is necessary to increase the capacitance of the terminal 194 to reduce the decrease in potential. For that purpose, the collector capacitance of the bipolar transistor for supplying V _H can be all connected to the terminal 194, so that the parasitic capacitance of the terminal 194 can be increased by the collector capacitance of the bipolar transistor. Also, here, φ _S1 and φ _S3 and φ _T1 and φ _T3 are shown as separate signals, but they may be driven by the same signal in some cases.

If there is a possibility that the bipolar transistor will be saturated temporarily due to fluctuations in the power supply voltage, the pulse signal φ
_A diode is connected between the output terminal of the circuit that generates _X and the V _H terminal 194 of FIG. 15 as previously described, and when the potential of φ _X is higher than V _H , the diode is connected. Should be turned on to prevent saturation.

〔The invention's effect〕

According to the present invention, since a high voltage from the voltage generating means is applied to the selected word line, the voltage of the selected word line can be raised at high speed and with high amplitude. In addition, since a part of the voltage generating circuits can be controlled to the inoperative state by a signal from the outside of the semiconductor memory device, it is possible to change the current supply capacity as needed and to significantly reduce power consumption.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor device for explaining the principle of the present invention, FIG. 2 is a diagram showing a specific example of the upstream circuit of FIG. 1, and FIG. 3 is a first application example of the present technology. FIG. 4 is a configuration diagram of the semiconductor device shown in FIG. 4, FIG. 4 is a voltage waveform diagram of FIG. 3, FIG. 5 is a configuration example diagram of the circuit 30 of FIG. 3, and FIG. 6 is a semiconductor device showing a second application example of the present technology. 7 is a configuration diagram of a semiconductor device showing a third application example of the present technology, FIG. 8 is a diagram showing voltage waveforms of FIG. 7, and FIG. 9 is a configuration of the circuit 86 of FIG. Example figure, 10th
The figure is a block diagram of a semiconductor device showing a fourth application example of the present technology,
11 is a configuration example diagram of the circuit 113, FIG. 12 is a configuration example diagram of a dynamic semiconductor device to which the present invention is applied, FIG.
FIG. 13 is a diagram showing an example of the configuration in which the present invention is applied to a word driver, FIG. 14 is a diagram showing the voltage waveform of FIG. 13, FIG. 15 is a charge pump type booster circuit used in the present invention, and FIG. 15th
FIG. 17 is a diagram showing voltage waveforms in the figure, FIG. 17 is a first conventional example diagram, and FIG.
The figure is a second conventional example. A: Terminal that applies the voltage that is the reference for the operation of circuit C, B ₁ ~
Bn: Terminal for applying a voltage that is the reference for the operation of circuit D, C:
Circuit for controlling circuit D, D: Circuit including MIS transistor and bipolar transistor, E: Input terminal, F: Signal line, G:
Output terminal, V _A : Reference voltage for circuit C operation, 30,86,1
13: Circuit for lowering the potential of the output terminal G, X _{0 to} Xn: X address, Y _{0 to} Ym: Y address, MCA: Memory cell array, MC, M
C ₀ , MC ₁ : Memory cell, DL, DL ₀ , DL ₁ : Data line, WL, WL ₀ , W
L ₁ : Word line, ABX, ABY: Address buffer circuit, XD, YD:
Decoder, driver circuit, RC: write / read circuit, CC: write / read control circuit, OC: output circuit, D
O: Output, CS: Chip select signal, WE: Write operation control signal, DI: Input, A _X0 , A _XR , A _X0 : Address buffer output, D
EC ₀ , DEC ₁ : Decoder, WD ₀ , WD ₁ : Word driver, SA: Sense amplifier, EQ: Equalizer, φ _P : Precharge signal,
φ _L : Latch signal, φ _X : Pulse signal, CP1, CP2: Charge pump circuit, 192: Zener diode, φ _S1 , φ _S2 , φ _S3 : C
P1 active pulse, φ _T1 , φ _T2 , φ _T3 : CP2 active pulse.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kiyoo Ito 1-280, Higashi Koigakubo, Kokubunji City, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-58-188388 (JP, A) JP-A-SHO 55-59756 (JP, A) JP-A-60-59818 (JP, A) JP-A-59-25424 (JP, A)

Claims (9)

[Claims] 1. A plurality of memory cells, a plurality of word lines respectively connected to the gates of MOS transistors in each memory cell of the plurality of memory cells, and a selected word line of the plurality of word lines is driven. A semiconductor memory device including a word line driving circuit for supplying the operating voltage to the word line driving circuit, the word line driving circuit further comprising a voltage generating means for supplying a voltage higher than the operating voltage to the word line driving circuit. Forming a current path between the output of the voltage generating means and the selected word line to cause the selected word line to have a first voltage higher than the operating voltage;
Voltage is supplied to the voltage generating means, the voltage generating means outputs a voltage substantially the same as the first voltage and has a first current supply capability, and the first voltage is substantially the same. A second state in which the same voltage is output and a second current supply capacity larger than the first current supply capacity is provided, and the second state is set when the word line is selected. A semiconductor memory device characterized by: 2. The semiconductor memory device according to claim 1, wherein the voltage generating means changes from the first state to the second state in response to a signal input from the outside of the semiconductor memory device. A semiconductor memory device characterized by being switched to a state. 3. A semiconductor memory device according to claim 2, wherein the voltage generating means comprises a plurality of voltage generating circuits, and some of the plurality of voltage generating circuits have the voltage generating circuit. A semiconductor memory device characterized in that operation / non-operation can be connected by a signal from outside the semiconductor memory device. 4. The semiconductor memory device according to claim 3, wherein each of the plurality of voltage generating circuits comprises a charge pump circuit. 5. The semiconductor memory device according to claim 3, wherein the part of the voltage generating circuits among the plurality of voltage generating circuits is the semiconductor memory device. A semiconductor memory device, which is controlled to be in an inactive state during a standby period of. 6. The semiconductor memory device according to claim 2, wherein the signal from outside the semiconductor memory device is a chip select signal, a CAS signal, or a RAS signal. A semiconductor memory device characterized by the above. 7. A semiconductor memory device according to any one of claims 1 to 6, wherein a voltage rise prevention for preventing the output of the voltage generating means from becoming larger than a predetermined voltage. A semiconductor memory device having circuits connected thereto. 8. The semiconductor memory device according to claim 7, wherein the voltage rise prevention circuit comprises a diode, a Zener diode or a MIS diode. 9. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a dynamic semiconductor memory device.