JPH05191734A - Ccd solid-state image pickup element - Google Patents

Abstract

PURPOSE:To improve the read efficiency of a signal charge by supplying a timing pulse synchronously with a timing pulse fed to an output gate via a capacitor so as to deepen a potential of the detection capacitor. CONSTITUTION:A timing pulse is fed to a detection capacitor CS converting a transfer signal charge into a voltage through an output gate OG provided to an output section of a solid-state image pickup element CCD transfer path synchronously with a timing pulse phi fed to an output gate OG through a capacitor CB. Then the signal voltage is efficiently read without increasing the operating voltage by deepen the potential of the output gate. Furthermore, the timing pulse fed to the detection capacitor and the output gate is used in common to simplify the circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD type solid-state image pickup device, for example, a technique effective when used in a device provided with a floating diffusion amplifier (hereinafter, simply referred to as FDA).

[0002]

2. Description of the Related Art FDA is used for a charge-voltage conversion circuit and a voltage amplification circuit of a CCD type solid-state image pickup device. For such FDA, see, eg, US Pat. No. 4,646,1.
There is number 19.

[0003]

In order to efficiently read the signal charge from the CCD transfer path, the potential of the reset drain of the detection capacitor for converting the signal charge into a voltage signal is increased to deepen the read potential. It is necessary to. However, if the potential of the reset drain is increased, it is necessary to increase the operating power supply voltage, and problems such as reliability and heat generation occur.

An object of the present invention is to provide a CCD solid-state image pickup device capable of efficiently reading out signal charges from the CCD transfer path without raising the operating voltage. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, with respect to the detection capacitor which converts the signal charge transferred through the output gate provided in the output part of the CCD transfer path into a voltage signal, the capacitor is connected in synchronization with the timing pulse supplied to the output gate. A timing pulse is supplied to deepen the potential.

[0006]

According to the above means, the potential can be deepened by the charge dispersion between the detection capacitor and the capacitor, so that the signal charge from the CCD transfer path can be efficiently read out without raising the operating voltage.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a schematic circuit diagram of an embodiment of a CCD type solid-state image pickup device to which the present invention is applied. In the figure, photodiodes D1 to D4 each consisting of a total of four in two rows and two columns are exemplarily shown as a representative in order to facilitate understanding of the CCD type solid-state imaging device itself. In an actual CCD type solid-state imaging device, photodiodes are arranged in a matrix in a plurality of rows and a plurality of columns, and as is well known, a large number of photodiodes of about 200,000 to about 400,000 are provided.

The anode side of the photodiode D1 is connected to the ground potential point of the circuit, and the cathode side is provided with a photogate (hereinafter simply referred to as PG gate) so that the photoelectrically converted signal charges are vertical CCD (hereinafter abbreviated as VCCD). V1
Transferred to the gate. Another photodiode D2 in the same row
Are transferred to the V3 gate of the VCCD via the PG gate. The photodiodes D3 and D4 in the other columns are also connected to the corresponding V1 and V of the VCCD via the PG gate similarly to the above.
Transferred to 3 gates.

The signal charge at the final stage of the VCCD is a horizontal CC.
D (hereinafter abbreviated as HCCD). HCCD
Is a high-speed charge transfer operation within 1H period in synchronization with the transfer pulses H1 and H2 until the next signal charge is transferred from the VCCD to the detection capacitor CS which converts the signal charge into a voltage signal. Tell. The OG provided at the output part of the HCCD is an output gate, and acts so that the signal charge of the HCCD is smoothly transferred to the detection capacitor CS. The timing pulse VG is supplied to the output gate OG.

Signal charges are converted into voltage signals by the capacitance CS. This voltage signal is FDA (Floating Diffu
The signal is amplified by a preamplifier PA called a sion amplifier) and transmitted from the output terminal OUT. When the signal charge transferred to the detection capacitor CS is output as a voltage signal through the preamplifier PA as described above, the reset gate RG and the reset drain shown in the form of a MOSFET (insulated gate field effect transistor) Q1. By RD, it is reset every one pixel, in other words, it is swept out. The reset gate RG
The reset drain has substantially the same structure as the MOSFET. A reset timing pulse is supplied to the reset gate RG, and a constant voltage such as an operating voltage is supplied to the reset drain RD.

An outline of the signal charge reading operation of the CCD solid-state image pickup device will be described below. When the timing pulse supplied to the PG gate is set to the high level, the V1 gate and the V3 gate of the VCCD connected to the PG gate are set to the high level. As a result, the photodiode D1,
The photoelectric conversion charge of D2 (D3, D4) is V1 of VCCD.
It is read by the V3 gate.

For example, in the odd field, the V2 gate is set to the high level. As a result, the signal charges under the V1 and V3 gates are mixed and temporarily collected under the V2 gate. Thereafter, the V3 gate is set to the high level at the next timing, and the V4 gate is set to the high level at the next timing, so that the signal charges are transferred downward. Below, V1
Each gate is set to a high level in the order of .about.V4, and the photoelectric conversion charges converted by the photodiode arranged above the gate are transferred in the same manner as above.

In the even field, V4 is set to the high level in place of the above V2 gate. As a result, the signal charges under the V3 and V1 gates are mixed with a shift of one row, and V4 is mixed.
Collected once under the gate. Hereinafter, the V1 gate becomes high level at the next timing, and V1 at the next timing.
The two gates are set to the high level and the signal charges are transferred downward. In this way, interlaced readout is equivalently performed by shifting the combination of signal charges in the odd field and the even field by one row.

The signal charges thus read out by the VCDD are transferred in parallel to the HCCD by the transfer operation, and the charge transfer operation is performed at high speed in the HCCD within a 1H period until the next signal charge is transferred. , Preamplifier P
A voltage signal is output through A.

FIG. 1 shows a circuit diagram of an embodiment of the FDA according to the present invention. The FDA of this embodiment is composed of the following circuits. The signal charge transferred via the output gate OG provided in the output part of the HCCD is transmitted to the detection capacitor CS. The voltage signal converted by the detection capacitor CS is supplied to the amplification MOSFET Q.
2 and current is amplified by the source follower circuit of the first stage consisting of the load MOSFET Q3 provided on the source side. The output signal of the first stage source follower circuit is an amplification MOSFET.
It is sent from the external terminal OUT via an output stage source follower circuit consisting of Q4 and the load MOSFET Q5.

The load MOSFETs Q3 and Q5 are composed of depletion type MOSFETs, and act as a constant current load by supplying the ground potential of the circuit to their gates and sources. Although not particularly limited, the amplification MOSFET Q4 in the output stage is a depletion type MOSFET.
It is also possible to use T. As described above, when the depletion type MOSFET is used, since there is no DC level loss due to the threshold voltage between the gate and the source, the operating voltage VDD can be lowered accordingly.
Alternatively, the output dynamic range with respect to the operating voltage VDD can be increased.

The detection capacitor CS has a MOSF.
A reset circuit composed of ETQ1 is provided. That is, when the timing pulse supplied to the reset gate RG is set to the high level, the MOSFET Q1 is turned on, and the potential of the reset drain RD is transmitted to the detection capacitor CS to sweep out the signal. That is, the diffusion layer forming the capacitor CS has a deep potential due to the signal charges to be transferred next. In this case, the voltage of the capacitor CS is VA = VR−, where VR is the reset voltage supplied to the reset drain RD.
Vth. Here, Vth is the threshold voltage of the MOSFET Q1.

The potential depth of the diffusion layer forming the capacitor CS is determined by the voltage VA (VR-Vth) supplied to the reset drain RD. CC
Operation voltage VD for low power consumption of solid-state image sensor
It is desirable to set D etc. low. Therefore, the reset voltage supplied to the reset drain RD tends to be lowered as the operating voltage of the CCD solid-state imaging device is lowered.

However, when the reset potential as described above is lowered, the potential depth of the diffusion layer forming the detection capacitor CS becomes shallow in the relative relationship with the output gate OG, and the efficient transfer of signal charges is achieved. May not be possible.

Therefore, in this embodiment, the capacitor CB is provided in order to increase the potential of the diffusion layer forming the detection capacitor CS without increasing the voltage of the reset drain RD. This capacitor CB
The timing pulse φ is supplied via the output gate OG in synchronization with the output timing of the output gate OG.

FIG. 2 is a timing chart for explaining an example of the operation of the FDA according to the present invention. When the timing pulse supplied to the reset gate RG is set to high level, the MOSFET Q1 is turned on as described above, and the potential V of the diffusion layer of the output capacitor CS is increased.
A has a potential depth corresponding to a potential such as VR-Vth.

When the timing pulse supplied to the reset gate RG is set to low level, the MOSFET Q1 is turned off. As a result, the diffusion layer of the detection capacitor CS holds the potential VA in the floating state. After the end of the reset timing, the timing pulse φ is set to the high level. As a result, the voltage VA can be raised by dV due to the charge distribution between the capacitors CB and CS.

The dv is calculated by the following equation (1). dv = VR · CB / (CB + CS) (1) where VR is the level of the timing pulse φ,
The same voltage as the voltage of the reset drain RD is used. The timing pulse φ and the reset voltage VR
Is formed by the operating voltage VDD, dv = VD
It becomes D · CB / (CB + CS). In this way, the detection capacitor C can be provided without increasing the operating voltage VDD.
The potential depth of S can be deepened.

This timing pulse φ is a timing pulse VG supplied to the output gate OG at the output timing.
Is also held high while is driven high. As a result, the potential of the detection capacitor CS is made to have a deeper potential as the voltage dv is raised, so that the output gate OG is increased.
It is possible to receive all the signal charges efficiently and surely via. This enables high-speed reading of FDA if necessary. After the output operation of the signal charge as described above, the timing pulse φ is set to the low level.

The potential of the detection capacitor CS formed by the capacitor CB as described above is deepened only when the signal charge is read out through the output gate OG.
Therefore, the timing pulse VG supplied to the output gate OG can be shared with the timing pulse φ. In other words, the capacitor CB may be provided between the output gate OG and the diffusion layer of the detection capacitor CS. In this case, since the special timing pulse φ is unnecessary, the circuit can be simplified and the number of external terminals can be reduced.

The operational effects obtained from the above embodiment are as follows. That is, (1) the detection capacitor that converts the signal charge transferred through the output gate provided in the output section of the CCD transfer path into a voltage signal is synchronized with the timing pulse supplied to the output gate. By supplying the timing pulse through the capacitor to deepen its potential, the effect that the signal charge from the CCD transfer path can be efficiently read out without increasing the operating voltage is obtained.

(2) The timing pulse transmitted to the detection capacitor via the above-mentioned capacitor shares the timing pulse supplied to the output gate, so that the circuit can be simplified and an increase in external terminals can be prevented. Is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, as an amplifier circuit connected in cascade form to the first stage source follower circuit, various embodiments such as those in which similar source follower circuits are connected in multiple stages in cascade form and those provided with an inverting amplifier circuit can be adopted. Is. The CCD transfer path may be a one-dimensional one other than the above two-dimensional CCD. That is, the photodiodes may be arranged in a line, and the signal charges thereof may be transferred to the HCCD in parallel and serially output.
Although the operating voltage VDD is shown as the operating voltage of the preamplifier PA, the operating voltage VDD is not limited thereto, and the operating voltage VDD is the highest voltage transmitted by the internal circuit that constitutes the CCD solid-state imaging device, and based on this The potential of the reset drain RD, the timing pulse supplied to the output gate OG and the reset gate RG, and the timing pulse φ supplied via the capacitor CB are formed. Therefore, each of the above potentials may be the same as the operating voltage VDD or may be a potential lower than that. The present invention can be widely used as a CCD type solid-state imaging device.

[0029]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, for the detection capacitor that converts the signal charge transferred through the output gate provided in the output section of the CCD transfer path into a voltage signal, the capacitor is connected in synchronization with the timing pulse supplied to the output gate. By supplying a timing pulse via the above to make the potential deeper, the signal charge from the CCD transfer path can be efficiently read out without raising the operating voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an FDA according to the present invention.

FIG. 2 is a timing chart for explaining an example of the operation of the FDA of FIG.

FIG. 3 is a schematic circuit configuration diagram showing an embodiment of a CCD solid-state imaging device to which the present invention is applied.

[Explanation of symbols]

VCCD ... Vertical CCD, HCCD ... Horizontal CCD, PG ...
Photogate, OG ... Output gate, RG ... Reset gate, RD ... Reset drain, PA ... Preamplifier (FD)
A), D1 to D4 ... Photodiodes, Q1 to Q5 ... MO
SFET, CS ... Detection capacitor, CB ... Capacitor, φ ... Timing pulse.

Claims (3)

[Claims] 1. An output gate provided at an output portion of a CCD transfer path, a detection capacitor for converting a signal charge transferred through the output gate into a voltage signal, and a signal charge of the detection capacitor is swept. A CCD-type solid-state device comprising a reset gate and a reset drain for outputting, and supplying a timing pulse through a capacitor in synchronization with a timing pulse supplied to the output gate to deepen the potential of the detection capacitor. Image sensor. 2. The CCD type solid-state image pickup device according to claim 1, wherein the timing pulse transmitted to the detection capacitor via the capacitor shares the timing pulse supplied to the output gate. 3. The CCD transfer path comprises a plurality of vertical CCDs, which receive the signal charges of a plurality of vertically arranged photodiodes of the photodiodes arranged two-dimensionally, and transfer from the plurality of vertical CCDs. Horizontal C that receives the signal charges to be transferred in parallel and transfers them serially
The CCD type solid-state image pickup device according to claim 1 or 2, which comprises a CD.