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JPH05198701A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPH05198701A
JPH05198701A JP3275592A JP3275592A JPH05198701A JP H05198701 A JPH05198701 A JP H05198701A JP 3275592 A JP3275592 A JP 3275592A JP 3275592 A JP3275592 A JP 3275592A JP H05198701 A JPH05198701 A JP H05198701A
Authority
JP
Japan
Prior art keywords
semiconductor device
metal base
package
die pad
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3275592A
Other languages
Japanese (ja)
Inventor
Minoru Yoshida
稔 吉田
Jiro Osedo
治郎 大施戸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3275592A priority Critical patent/JPH05198701A/en
Publication of JPH05198701A publication Critical patent/JPH05198701A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a package with high heat-dissipation effect by arranging a metal base via adhesive in the lower part of a die pad and lead. CONSTITUTION:A die pad 4 fitted with a semiconductor device 1 is mounted on a metal base 11 via adhesive 12 and the top face of the pad is sealed by sealing resin 5. Also, the electrode and lead 3 of the semiconductor device 1 are bonded electrically and mechanically by a small-gage metal wire 2. Further, the rear face of the metal base 11 is provided with an insulating layer 13 to play the role of preventing the short of a substrate circuit when the bottom face of a package is mounted on a substrate but mounting of the insulating layer can be done freely. Moreover, the metal base 11 improved in the adhesion to the sealing resin 5 by provision of irregularity 14 in the top face is sealed by the resin 5 while a space is given to such a degree that it does not adhere to the die pad 4 and lead 3. When the metal base 11 is arranged in this manner, it is possible to heighten a heat dissipation effect.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体素子を実装す
るパッケージに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for mounting a semiconductor device.

【0002】[0002]

【従来の技術】図6は従来の半導体装置用パッケージを
示す断面図であり、図において、1は半導体素子、2は
金属細線、3はリード部、4はダイスパッド部、5は封
止樹脂である。
2. Description of the Related Art FIG. 6 is a sectional view showing a conventional semiconductor device package. In the figure, 1 is a semiconductor element, 2 is a fine metal wire, 3 is a lead portion, 4 is a die pad portion, and 5 is a sealing resin. Is.

【0003】次に動作について説明する。ダイスパッド
部4に半導体素子1が接合され、半導体素子1表面の電
極とリード部3は金属細線2で電気的・機械的に接続さ
れる。最後に半導体素子1保護のため封止樹脂5にて封
止される。
Next, the operation will be described. The semiconductor element 1 is joined to the die pad portion 4, and the electrode on the surface of the semiconductor element 1 and the lead portion 3 are electrically and mechanically connected by the thin metal wire 2. Finally, the semiconductor element 1 is sealed with a sealing resin 5 for protection.

【0004】[0004]

【発明が解決しようとする課題】従来の半導体装置用パ
ッケージは樹脂により封止されているので、半導体素子
が発する熱を放熱させるうえにおいて、効率が悪いなど
の問題点があった。
Since the conventional semiconductor device package is sealed with resin, there is a problem in that it is inefficient in radiating the heat generated by the semiconductor element.

【0005】この発明は上記のような問題点を解消する
ためになされたもので、放熱効果の優れたパッケージを
提供することを目的としている。
The present invention has been made to solve the above problems, and an object thereof is to provide a package having an excellent heat dissipation effect.

【0006】[0006]

【課題を解決するための手段】この発明に係る半導体装
置用パッケージは、パッケージの底面部に金属ベースを
設けたものである。
A semiconductor device package according to the present invention has a metal base provided on the bottom surface of the package.

【0007】[0007]

【作用】この発明における半導体装置用パッケージは、
金属ベースを介して半導体素子の発する熱の放熱効果を
高める。
The semiconductor device package according to the present invention comprises:
The heat radiation effect of the heat generated by the semiconductor element via the metal base is enhanced.

【0008】[0008]

【実施例】実施例1.以下、この発明の一実施例を図に
ついて説明する。図1において、従来技術と同一部分に
ついては同一符号により示すものとする。11は金属ベ
ース、12は接着剤、13は絶縁層である。なお絶縁層
13は必要に応じて無くてもよい。
EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same parts as those in the prior art are designated by the same reference numerals. Reference numeral 11 is a metal base, 12 is an adhesive, and 13 is an insulating layer. The insulating layer 13 may be omitted if necessary.

【0009】次に作用について説明する。半導体素子1
を取り付けたダイスパッド部4が接着剤12を介して金
属ベース11に取り付けられてあり、その上面は封止樹
脂5にて封止される。又、半導体素子1の電極とリード
部3とは金属細線2で電気的、機械的に接合されてい
る。また金属ベース11の裏面には絶縁層13が設けら
れ、パッケージ底面が基板実装時に基板回路のショート
を防止する役目を持っているが、その取付は自由であ
る。以上のように金属ベース11を配置することによ
り、放熱効果を高めることができる。
Next, the operation will be described. Semiconductor element 1
The die pad portion 4 to which is attached is attached to the metal base 11 via the adhesive 12, and the upper surface thereof is sealed with the sealing resin 5. Further, the electrode of the semiconductor element 1 and the lead portion 3 are electrically and mechanically joined by a thin metal wire 2. Further, an insulating layer 13 is provided on the back surface of the metal base 11, and the bottom surface of the package has a role of preventing a short circuit of the board circuit when mounting on the board, but the mounting is free. By disposing the metal base 11 as described above, the heat dissipation effect can be enhanced.

【0010】実施例2.実施例2による半導体装置用パ
ッケージを図2について説明する。半導体素子1が直接
金属ベース11に接合された後、樹脂5により封止され
る。
Embodiment 2. A semiconductor device package according to the second embodiment will be described with reference to FIG. After the semiconductor element 1 is directly bonded to the metal base 11, it is sealed with the resin 5.

【0011】実施例3.実施例3による半導体装置用パ
ッケージを図3により説明する。上面に凹凸14を設け
て封止樹脂5との密着性を向上させた金属ベース11
を、ダイスパッド部4及びリード部3と接着しない程度
の間隔を持たせて樹脂5により封止する。
Embodiment 3. A semiconductor device package according to the third embodiment will be described with reference to FIG. A metal base 11 in which unevenness 14 is provided on the upper surface to improve adhesion with the sealing resin 5.
Are sealed with a resin 5 with a space such that they are not bonded to the die pad portion 4 and the lead portion 3.

【0012】実施例4.実施例4による半導体装置用パ
ッケージを図4により説明する。実施例1ではダイスパ
ッド部4とリード部3が同一高さであったのを、ダイス
パッド部4を一段下方へ下げて金属細線2の配線をより
容易にさせるものである。このため、ダイスパッド部4
の下方への移動量に対応して、金属ベース11の上面に
くぼみ11aを設けた。
Embodiment 4. A semiconductor device package according to the fourth embodiment will be described with reference to FIG. In the first embodiment, the die pad portion 4 and the lead portion 3 have the same height, but the die pad portion 4 is lowered downward by one step to make the wiring of the metal thin wires 2 easier. Therefore, the die pad portion 4
A depression 11a is provided on the upper surface of the metal base 11 in correspondence with the amount of downward movement of the metal base 11.

【0013】実施例5.実施例5による半導体装置用パ
ッケージを図5により説明する。金属キャップ15を接
着剤12を介してリード部3と接合させ、中空状態で封
止したものである。
Embodiment 5. A semiconductor device package according to the fifth embodiment will be described with reference to FIG. The metal cap 15 is joined to the lead portion 3 via the adhesive 12 and sealed in a hollow state.

【0014】[0014]

【発明の効果】以上のようにこの発明によれば、半導体
素子下面部に金属ベースを設けた事により、放熱効果の
高いパッケージが得られる効果がある。
As described above, according to the present invention, by providing the metal base on the lower surface of the semiconductor element, a package having a high heat dissipation effect can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例1による半導体装置用パッケー
ジを示す断面図である。
FIG. 1 is a sectional view showing a semiconductor device package according to a first embodiment of the present invention.

【図2】本発明の実施例2による半導体装置用パッケー
ジを示す断面図である。
FIG. 2 is a sectional view showing a semiconductor device package according to a second embodiment of the present invention.

【図3】本発明の実施例3による半導体装置用パッケー
ジを示す断面図である。
FIG. 3 is a sectional view showing a semiconductor device package according to a third embodiment of the present invention.

【図4】本発明の実施例4による半導体装置用パッケー
ジを示す断面図である。
FIG. 4 is a sectional view showing a semiconductor device package according to a fourth embodiment of the present invention.

【図5】本発明の実施例5による半導体装置用パッケー
ジを示す断面図である。
FIG. 5 is a sectional view showing a semiconductor device package according to a fifth embodiment of the present invention.

【図6】従来の半導体装置用パッケージを示す断面図で
ある。
FIG. 6 is a cross-sectional view showing a conventional semiconductor device package.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 金属細線 3 リード部 4 ダイスパッド部 5 封止樹脂 11 金属ベース 12 接着剤 13 絶縁層 14 金属ベース表面に設けられた凹凸 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Metal thin wire 3 Lead part 4 Dice pad part 5 Sealing resin 11 Metal base 12 Adhesive 13 Insulating layer 14 Unevenness provided on the surface of metal base

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 ダイスパッド上に半導体素子が載置さ
れ、リード部と半導体素子が金属細線で接合されると共
に、上記装置全体を樹脂にて封止した半導体装置用パッ
ケージにおいて、上記ダイスパッド部及びリード部の下
部に接着剤を介して金属ベースを配置したことを特徴と
する半導体装置用パッケージ。
1. A semiconductor device package in which a semiconductor element is mounted on a die pad, the lead portion and the semiconductor element are joined by a fine metal wire, and the entire device is sealed with a resin. And a package for a semiconductor device in which a metal base is arranged below the lead portion via an adhesive.
【請求項2】 金属ベース上に直接半導体素子を取り付
けると共に、その外側に接着剤を介してリード部を載置
し、半導体素子とリード部を金属細線で接合し、装置全
体を樹脂にて封止したことを特徴とする半導体装置用パ
ッケージ。
2. A semiconductor element is directly mounted on a metal base, and a lead portion is placed on the outside thereof with an adhesive, the semiconductor element and the lead portion are joined with a metal thin wire, and the entire device is sealed with resin. A semiconductor device package characterized by being stopped.
【請求項3】 ダイスパッド部上に半導体素子が載置さ
れ、リード部と半導体素子が金属細線で接合されると共
に、装置全体を樹脂にて封止した半導体装置用パッケー
ジにおいて、上記ダイスパッド部およびリード部の下部
に、間隔を介して、上面に凹凸が設けられた金属ベース
が取り付けられたことを特徴とする半導体装置用パッケ
ージ。
3. A semiconductor device package in which a semiconductor element is mounted on a die pad portion, the lead portion and the semiconductor element are joined by a fine metal wire, and the entire device is sealed with a resin. A package for a semiconductor device, characterized in that a metal base having unevenness on the upper surface is attached to the lower part of the lead portion with a space therebetween.
【請求項4】 ダイスパッド部の配置をリード部より一
段下方へ下げると共に、これに対向する金属ベース部に
くぼみを設けたことを特徴とする請求項1記載の半導体
装置用パッケージ。
4. The package for a semiconductor device according to claim 1, wherein the disposition of the die pad portion is lowered by one step below the lead portion, and a recess is provided in the metal base portion facing the die pad portion.
【請求項5】 ダイスパッド部及びリードの下部に接着
剤を介して金属ベースを配置し、かつリード上方に接着
剤を介して金属キャップを設置し、中空状態で封止した
ことを特徴とする半導体装置用パッケージ。
5. A metal base is disposed below the die pad and the lead via an adhesive agent, and a metal cap is placed above the lead via the adhesive agent to seal in a hollow state. Package for semiconductor device.
【請求項6】 金属ベース下部に絶縁層を設けたことを
特徴とする請求項1〜5記載の半導体装置用パッケー
ジ。
6. The package for a semiconductor device according to claim 1, wherein an insulating layer is provided below the metal base.
JP3275592A 1992-01-22 1992-01-22 Package for semiconductor device Pending JPH05198701A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3275592A JPH05198701A (en) 1992-01-22 1992-01-22 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3275592A JPH05198701A (en) 1992-01-22 1992-01-22 Package for semiconductor device

Publications (1)

Publication Number Publication Date
JPH05198701A true JPH05198701A (en) 1993-08-06

Family

ID=12367662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3275592A Pending JPH05198701A (en) 1992-01-22 1992-01-22 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JPH05198701A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997031394A1 (en) * 1996-02-22 1997-08-28 Nitto Denko Corporation Semiconductor device and method for manufacturing the same
US5796159A (en) * 1995-11-30 1998-08-18 Analog Devices, Inc. Thermally efficient integrated circuit package
US5818105A (en) * 1994-07-22 1998-10-06 Nec Corporation Semiconductor device with plastic material covering a semiconductor chip mounted on a substrate of the device
EP0881677A1 (en) * 1996-02-15 1998-12-02 Nitto Denko Corporation Semiconductor device and multilayered lead frame used for the same
US6255742B1 (en) 1997-10-08 2001-07-03 Nec Corporation Semiconductor package incorporating heat dispersion plate inside resin molding
US6787389B1 (en) 1997-10-09 2004-09-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having pads for connecting a semiconducting element to a mother board
JP2017028060A (en) * 2015-07-21 2017-02-02 株式会社デンソー Electronic device
KR20180121581A (en) 2016-06-10 2018-11-07 히타치가세이가부시끼가이샤 Adhesive film and dicing die-bonding all-in-one film
KR20200026799A (en) 2017-07-20 2020-03-11 히타치가세이가부시끼가이샤 Heat-resistant die bonding film and dicing die bonding film
WO2021226799A1 (en) * 2020-05-11 2021-11-18 华为技术有限公司 Package structure, manufacturing method therefor, and communication apparatus
KR20230013169A (en) 2016-02-26 2023-01-26 쇼와덴코머티리얼즈가부시끼가이샤 Adhesive film and dicing/die bonding film

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818105A (en) * 1994-07-22 1998-10-06 Nec Corporation Semiconductor device with plastic material covering a semiconductor chip mounted on a substrate of the device
US5796159A (en) * 1995-11-30 1998-08-18 Analog Devices, Inc. Thermally efficient integrated circuit package
EP0881677A4 (en) * 1996-02-15 2001-01-31 Nitto Denko Corp Semiconductor device and multilayered lead frame used for the same
EP0881677A1 (en) * 1996-02-15 1998-12-02 Nitto Denko Corporation Semiconductor device and multilayered lead frame used for the same
EP0883170A4 (en) * 1996-02-22 2001-01-31 Nitto Denko Corp Semiconductor device and method for manufacturing the same
US6144108A (en) * 1996-02-22 2000-11-07 Nitto Denko Corporation Semiconductor device and method of fabricating the same
WO1997031394A1 (en) * 1996-02-22 1997-08-28 Nitto Denko Corporation Semiconductor device and method for manufacturing the same
EP0883170A1 (en) * 1996-02-22 1998-12-09 Nitto Denko Corporation Semiconductor device and method for manufacturing the same
US6255742B1 (en) 1997-10-08 2001-07-03 Nec Corporation Semiconductor package incorporating heat dispersion plate inside resin molding
US6787389B1 (en) 1997-10-09 2004-09-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having pads for connecting a semiconducting element to a mother board
JP2017028060A (en) * 2015-07-21 2017-02-02 株式会社デンソー Electronic device
KR20230013169A (en) 2016-02-26 2023-01-26 쇼와덴코머티리얼즈가부시끼가이샤 Adhesive film and dicing/die bonding film
KR20180121581A (en) 2016-06-10 2018-11-07 히타치가세이가부시끼가이샤 Adhesive film and dicing die-bonding all-in-one film
KR20200026799A (en) 2017-07-20 2020-03-11 히타치가세이가부시끼가이샤 Heat-resistant die bonding film and dicing die bonding film
WO2021226799A1 (en) * 2020-05-11 2021-11-18 华为技术有限公司 Package structure, manufacturing method therefor, and communication apparatus

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