JP2962575B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2962575B2 JP2962575B2 JP2340501A JP34050190A JP2962575B2 JP 2962575 B2 JP2962575 B2 JP 2962575B2 JP 2340501 A JP2340501 A JP 2340501A JP 34050190 A JP34050190 A JP 34050190A JP 2962575 B2 JP2962575 B2 JP 2962575B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- heat sink
- heat
- semiconductor chip
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は放熱性に優れる半導体装置に関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor device having excellent heat dissipation.
（従来の技術） 従来の半導体装置では第５図に例示するように半導体
チップ10をヒートシンク11上に固着し、半導体チップ10
からの熱をヒートシンク11を通じてリードあるいは封止
樹脂に拡散させ、放熱するようにしている。(Prior Art) In a conventional semiconductor device, a semiconductor chip 10 is fixed on a heat sink 11 as shown in FIG.
Is diffused into the lead or the sealing resin through the heat sink 11 to radiate the heat.
あるいは第６図に示すように、リードフレームを２層
に形成して、広い面積を有するダイパッド12からリード
フレームを通じて放熱を図るようにした半導体装置も知
られている。Alternatively, as shown in FIG. 6, there is also known a semiconductor device in which a lead frame is formed in two layers and heat is radiated from the die pad 12 having a large area through the lead frame.
（発明が解決しようとする課題） しかるに近年半導体チップは益々高集積化の一途を辿
り、発熱量も多いことから上記従来の半導体装置では放
熱性が十分でない。(Problems to be Solved by the Invention) However, in recent years, semiconductor chips have been increasingly integrated and generate a large amount of heat, so that the above-described conventional semiconductor device has insufficient heat dissipation.
そこで、本発明は放熱性に優れる半導体装置を提供す
ることを目的とする。Therefore, an object of the present invention is to provide a semiconductor device having excellent heat dissipation.
（課題を解決するための手段） 上記目的による本発明に係る半導体装置では、ヒート
シンクの周縁部にインナーリードの先端部が電気的に絶
縁されて接合されると共に、ヒートシンクのインナーリ
ード先端に囲まれる部位に突出部が形成され、該突出部
に半導体チップのジャンクションパターンが形成された
側の面が電気的に絶縁されて固着され、半導体チップと
インナーリードとがTABリードにより電気的に接続され
て樹脂封止されていることを特徴としている。(Means for Solving the Problems) In the semiconductor device according to the present invention having the above object, the tip of the inner lead is electrically insulated and joined to the peripheral edge of the heat sink, and is surrounded by the tip of the inner lead of the heat sink. A projecting portion is formed at the portion, and the surface of the semiconductor chip on which the junction pattern is formed is electrically insulated and fixed to the projecting portion, and the semiconductor chip and the inner lead are electrically connected by the TAB lead. It is characterized by being sealed with resin.
（作用） 本発明に係る半導体装置では、ジャンクションパター
ンがある発熱量の大きいチップ面からの熱が直接ヒート
シンクを介して外部に放熱されるので、放熱性に優れ、
より集積度の高い半導体チップを搭載できる。(Operation) In the semiconductor device according to the present invention, since heat from the chip surface having a large heat value with the junction pattern is directly radiated to the outside through the heat sink, the semiconductor device is excellent in heat dissipation.
A semiconductor chip with a higher degree of integration can be mounted.
（実施例） 以下、本発明の好適な実施例を添付図面に基づいて詳
細に説明する。Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
第１図はリードフレーム20の平面図、第２図はその断
面図である。FIG. 1 is a plan view of the lead frame 20, and FIG. 2 is a sectional view thereof.
図において、21はアウターリード、22はインナーリー
ド、23はダムバー、24はレール部、25はヒートシンクで
ある。In the figure, 21 is an outer lead, 22 is an inner lead, 23 is a dam bar, 24 is a rail, and 25 is a heat sink.
ヒートシンク25の上面周縁部にインナーリード22下面
が電気的絶縁性を有する接着剤26を介して接合されてい
る。またヒートシンク25上面の、インナーリード22先端
で囲まれる空間部内に上面がインナーリード22上面とほ
ぼ面一になる突出部27が形成されている。The lower surface of the inner lead 22 is joined to the peripheral portion of the upper surface of the heat sink 25 via an adhesive 26 having electrical insulation. Further, a protrusion 27 whose upper surface is substantially flush with the upper surface of the inner lead 22 is formed in a space surrounded by the tip of the inner lead 22 on the upper surface of the heat sink 25.
ヒートシンク25は放熱性に優れる金属やセラミックが
用いられるが、半導体チップと熱膨張係数の近い素材、
例えばMo材、AlN材、SiC材、Cu−Ｗ材などを用いると好
適である。The heat sink 25 is made of a metal or a ceramic having excellent heat dissipation properties.
For example, it is preferable to use a Mo material, an AlN material, a SiC material, a Cu-W material, or the like.
第３図は上記リードフレーム20を用いて形成した半導
体装置30の断面図を示す。FIG. 3 is a cross-sectional view of a semiconductor device 30 formed using the lead frame 20.
本実施例の半導体装置30は、ヒートシンク25の突出部
27上面に、半導体チップ31がそのジャンクションパター
ンのあるチップ面を突出部27上面に向けて絶縁性を有す
る接着剤32により固着され、さらに半導体チップ31はイ
ンナーリード22とTAB（Tape Automated Bonding）リー
ド33で電気的に接続されている。そして、ヒートシンク
25が封止樹脂34中に封止されて半導体装置30に完成され
ている。The semiconductor device 30 of the present embodiment
On the upper surface 27, a semiconductor chip 31 is fixed with an adhesive 32 having an insulating property so that the chip surface having the junction pattern faces the upper surface of the protruding portion 27. Further, the semiconductor chip 31 is connected to the inner leads 22 and TAB (Tape Automated Bonding) leads. 33 is electrically connected. And a heat sink
25 is sealed in a sealing resin 34 to complete the semiconductor device 30.
なお、TABテープとはTABテープを用いたものであり、
支持テープに銅箔からなるリードを多数本支持したTAB
テープを用いてリードを半導体チップとインナーリード
にボンディングし、支持テープを除去してリードのみを
用いたもの、あるいはそのまま支持テープを残したもの
をいう。In addition, the TAB tape uses TAB tape,
TAB with a large number of copper foil leads supported on a support tape
A tape is used to bond a lead to a semiconductor chip and an inner lead, and the support tape is removed to use only the lead or to leave the support tape as it is.
第４図は半導体チップ31の反対側の面にもヒートシン
ク35を接着剤36によって接合し、両ヒートシンク25、35
の外側面を封止樹脂34表面に露出させた実施例を示す。
両ヒートシンク25、35は封止樹脂34中に埋没させてもあ
るいは一部を露出させてもよい。FIG. 4 shows that a heat sink 35 is also bonded to the opposite surface of the semiconductor chip 31 by an adhesive 36, so that the two heat sinks 25, 35
This shows an embodiment in which the outer surface of is exposed on the surface of the sealing resin.
The heat sinks 25 and 35 may be buried in the sealing resin 34 or may be partially exposed.
以上のように構成されているから、ジャンクションパ
ターンがある発熱量の大きいチップ面からの熱が直接ヒ
ートシンク25を通じて外部の放熱されるので放熱性に優
れ、半導体チップ31の高集積化に対処しうる。また第４
図に示すように半導体チップ31の他面側にもヒートシン
ク35を設けることによりさらに放熱性を向上させること
ができる。With the configuration described above, since the heat from the chip surface having a large heat value with a junction pattern is directly radiated to the outside through the heat sink 25, the heat dissipation is excellent, and it is possible to cope with the high integration of the semiconductor chip 31. . The fourth
By providing the heat sink 35 on the other surface side of the semiconductor chip 31 as shown in the figure, the heat dissipation can be further improved.
また、リードフレーム20はヒートシンク25の上面側に
突出部27を設けているので、半導体チップ31の接合が容
易に行え、またTABリード33を用いることにより半導体
チップ31の端子部の存在する面を突出部27側に向けて固
定しても半導体チップ31とインナーリード22との接着を
容易に行える。In addition, since the lead frame 20 has the protrusion 27 on the upper surface side of the heat sink 25, the semiconductor chip 31 can be easily joined. Even if the semiconductor chip 31 and the inner lead 22 are fixed toward the protruding portion 27, the semiconductor chip 31 and the inner lead 22 can be easily bonded.
以上本発明につき好適な実施例を挙げて種々説明した
が、本発明はこの実施例に限定されるものではなく、発
明の精神を逸脱しない範囲内で多くの改変を施し得るの
はもちろんである。Although various preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and it goes without saying that many modifications can be made without departing from the spirit of the invention. .
（発明の効果） 本厚に係る半導体装置ではジャンクションパウダーが
ある発熱量の大きいチップ面からの熱が直接ヒートシン
クを介して外部に放熱されるので、放熱性に優れ、より
集積度の高い半導体チップを搭載できる。(Effect of the Invention) In the semiconductor device according to this thickness, since the heat from the chip surface where the junction powder has a large calorific value is directly radiated to the outside via the heat sink, the semiconductor chip having excellent heat dissipation and higher integration degree Can be installed.
第１図はリードフレームの一例を示す平面図、第２図は
その断面図、第３図は半導体装置の一例を示す断面図、
第４図は半導体装置の他の実施例を示す断面図である。
第５図、第６図はそれぞれ従来の半導体装置の例を示す
断面図である。 20……リードフレーム、22……インナーリード、25……
ヒートシンク、27……突出部、30……半導体装置、31…
…半導体チップ、32……接着剤、33……TABリード、34
……封止樹脂。FIG. 1 is a plan view showing an example of a lead frame, FIG. 2 is a sectional view thereof, FIG. 3 is a sectional view showing an example of a semiconductor device,
FIG. 4 is a sectional view showing another embodiment of the semiconductor device.
5 and 6 are cross-sectional views each showing an example of a conventional semiconductor device. 20 …… lead frame, 22 …… inner lead, 25 ……
Heat sink, 27 Projection, 30 Semiconductor device, 31
... Semiconductor chip, 32 ... Adhesive, 33 ... TAB lead, 34
.... Sealing resin.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/50 H01L 23/36 H01L 21/60 ──────────────────────────────────────────────────の Continued on the front page (58) Fields surveyed (Int.Cl. 6 , DB name) H01L 23/50 H01L 23/36 H01L 21/60
Claims (1)
先端部が電気的に絶縁されて接合されると共に、ヒート
シンクのインナーリード先端に囲まれる部位に突出部が
形成され、該突出部に半導体チップのジャンクションパ
ターンが形成された側の面が電気的に絶縁されて固着さ
れ、半導体チップとインナーリードとがTABリードによ
り電気的に接続されて樹脂封止されていることを特徴と
する半導体装置。A tip of an inner lead is electrically insulated and joined to a peripheral portion of a heat sink, and a protrusion is formed at a portion surrounded by a tip of the inner lead of the heat sink. A semiconductor device wherein a surface on a side where a junction pattern is formed is electrically insulated and fixed, and a semiconductor chip and inner leads are electrically connected by TAB leads and sealed with a resin.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2340501A JP2962575B2 (en) | 1990-11-30 | 1990-11-30 | Semiconductor device |
| KR1019910018795A KR920010862A (en) | 1990-11-30 | 1991-10-25 | Semiconductor devices and leadframes used therein |
| US07/798,736 US5293301A (en) | 1990-11-30 | 1991-11-27 | Semiconductor device and lead frame used therein |
| EP19910311114 EP0488783A3 (en) | 1990-11-30 | 1991-11-29 | Lead frame for semiconductor device comprising a heat sink |
| KR2019950026696U KR960000942Y1 (en) | 1990-11-30 | 1995-09-28 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2340501A JP2962575B2 (en) | 1990-11-30 | 1990-11-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04207062A JPH04207062A (en) | 1992-07-29 |
| JP2962575B2 true JP2962575B2 (en) | 1999-10-12 |
Family
ID=18337573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2340501A Expired - Lifetime JP2962575B2 (en) | 1990-11-30 | 1990-11-30 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2962575B2 (en) |
| KR (1) | KR920010862A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| MY133357A (en) * | 1999-06-30 | 2007-11-30 | Hitachi Ltd | A semiconductor device and a method of manufacturing the same |
| JP5402778B2 (en) * | 2010-03-30 | 2014-01-29 | 株式会社デンソー | Semiconductor device provided with semiconductor module |
-
1990
- 1990-11-30 JP JP2340501A patent/JP2962575B2/en not_active Expired - Lifetime
-
1991
- 1991-10-25 KR KR1019910018795A patent/KR920010862A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04207062A (en) | 1992-07-29 |
| KR920010862A (en) | 1992-06-27 |
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