JPH05189340A - Data delay control system - Google Patents

Abstract

PURPOSE:To avoid the next writing from being started before the completion of reading by switching a read memory by providing a phase comparing and judging equipment and a selector. CONSTITUTION:At least more than three sets of memories 5, 6, and 7 are arranged in parallel, and one received data column is simultaneously written in each memory. Then, memory writing address control parts 1, 2, and 3 controls operates the plural memories 5, 6, and 7 by writing addresses having arbitrary different time phases. This system is equipped with a phase comparing and judging part 10 which compares and judges the plural writing control signals and the reading control signals when the reading of data is operated by a memory reading address control part 8 after the lapse of a time delayed a little from the transmission path delay time fluctuation of the data column from the completion of the writing of data, and a selecting circuit 9 which recognizes the phase compared and judged result, judges the time phase margin of the writing and reading, selects the memory, and reads the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data delay control system, and in particular, in a data multiplex communication network by satellite communication, when the writing and reading of the data received in a memory are alternately performed, the data whose time sequence is improved. It relates to a delay control method.

[0002]

2. Description of the Related Art Conventionally, this type of data delay control system has been constructed by connecting in parallel one or a plurality of memories each of which is capable of inputting a continuous received data sequence and reading / writing at any time. Two or more different memory circuits that operate on these memories without the write and read operations matching each other, a memory write address control unit that operates by a clock associated with the received data string, and a memory read that operates by a clock that reads the memory. And an address control unit. In these write / read operations, when one received data string is alternately written in two memory circuits at different times, the memory write address control circuit performs write address control with the same time phase in each memory circuit. The memory reading is performed after a lapse of a little time after the completion of the writing and the fluctuation of the transmission line delay time of the data string. This memory read operation is performed by any one of the memory circuits according to the memory read address control based on the initially set time phase.
This is a data delay control method in which reading is alternately performed from one memory at any time.

[0003]

In this conventional data delay control method, since the clock frequencies for writing and reading are different, the integration time of the time difference caused by the difference between the different clock frequencies for controlling writing and reading. Is larger than the sum of the 1-bit time widths of the received data strings, that is, the product of the number of storable bits in the memory, the read operation is performed in the memory control that alternately performs the write operation and the read operation. It may happen that new data is written before the completion of the. This situation is a phenomenon that cannot be avoided in principle in a data network in which the data string input to the memory includes long-term time variations, and even if the write / read clock frequency difference approaches zero as much as possible. However, since there are variations in the transmission path length due to various differences in the transmission path length and variations in the orbit of the communication satellite, it cannot be avoided. On the other hand, the storage capacity of the memory is economically feasible, and especially as the communication data speed becomes faster, the number of bits accumulated in the memory required for delay absorption for a fixed time increases exponentially with the data speed. It has a drawback that it exceeds the speed limit and eventually becomes impossible.

[0004]

According to the data delay control method of the present invention, a plurality of serial / parallel connections in which a continuous received data string and a write clock associated with this received data string are input and can be read / written at any time. A memory read address control unit that performs write control on these memories with a clock associated with a received data string, and a memory read address control unit that operates on a clock read from the memory, At least three sets of memories are arranged in parallel, and one received data string is simultaneously written in each memory. The memory write address control unit performs write address control with a plurality of memories having different arbitrary time phases. Fluctuation of transmission line delay time of the data string from the completion of reading and writing In the case of performing after a lapse of a little later time, a phase comparison / determination unit for comparing and comparing the plurality of write control signals and the read control signal, and a time phase margin for writing / reading by recognizing the phase comparison determination result. And a selection circuit which makes a judgment, selects a memory, and reads it.

[0005]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a data delay control system according to an embodiment of the present invention. In FIG. 1, a continuous received data sequence Di and a write clock Ci associated with the received data sequence are input without being intermittent in time. One or a plurality of memories 5 to 7 capable of writing / reading at any time are used, and the memories are connected in parallel or in series parallel. This memory 5
In FIG. 7, three different memory circuits m in which write and read operations act on the same memory without matching
1 to m3. Further, the memory write address control units 1 to 3 that operate at the write clock Ci associated with the received data string, the memory read address control unit 8 that operates at the clock Co that reads the memory, and the read data from the memories 5 to 7 are selected. It has a selector 9 for outputting and a read clock phase comparison / decision unit 10 to be described later.

Next, the operation of this embodiment will be described. Memory 5
When 7 sets of 7 to 7 are arranged in parallel and one received data string Di is simultaneously written in the respective memories 5 to 7, the memory write address control units 1 to 3 use the three memories 5 to 7.
And write address control with arbitrary time phases different from each other. The memory read address control unit 8 performs a memory read after a lapse of a little time from the completion of writing after the transmission line delay time variation of the received data string, and the memory read address is based on the time phase initially set. Using the selector 9 that selects an arbitrary memory output from the memories 5 to 7 according to the control, one memory is read from time to time, and the delay-corrected output Do is output from the selector 9. Here, the timing control having an arbitrary time phase of the memory write address control units 1 to 3 is performed by the phase comparison / determination unit 10 with the memory write addresses 101 to 103 and the memory read address 1.
By comparing with 07, the time phase margin of reading and writing is judged using the phase comparison judging device 10. That is, when it is detected that the time phase margin of any memory currently being read has become small, control signals 104 to 106 for presetting an address having a safe phase margin to any one of the other two memories are transmitted. To do. The phase comparison / determination unit 10 also outputs the read memory switching signals of the memories 5 to 7 to the selector 9 at the same time, and in the actual switching operation, the control signals 104 to 10 for presetting the read address are used.
6 is output, and this time difference is performed after a lapse of a little delay from the fluctuation of the transmission line delay time.

[0007]

As described above, according to the present invention, a memory read circuit that operates at the same read address by storing one received data string in three different memories with write addresses having different arbitrary time phases. In the above, by providing the phase comparison / determination unit and the selector, it is possible to avoid the start of the next writing before the completion of reading by switching the reading memory.
Therefore, in a data network which has a property of including a long-term time variation of a received data string, it is possible to realize a memory with a relatively small storage capacity when performing delay control using the data storage / reading function. In addition, even if the delay variation exceeds the storage limit of the memory, the memory can be switched in advance so that the delay control can be performed without impairing the continuity of data.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 to 3 memory write address control unit 5 to 7 memory 8 memory read address control unit 9 selector 10 phase comparison judgment unit m1 to m3 memory circuit

Claims (2)

[Claims] 1. A plurality of memories connected in series and parallel, each of which is capable of inputting a continuous received data sequence and a write clock associated with the received data sequence and reading / writing at any time.
In a data delay control method having a memory write address control unit that controls writing to these memories with a clock associated with a received data string, and a memory read address control unit that operates with a clock read from the memory, the memories are arranged in parallel at the minimum. When three or more sets are arranged and one received data string is simultaneously written in each memory, the memory write address control unit performs write address control having a different arbitrary time phase in a plurality of memories, and when the memory read is completed, the write is completed. In the case of performing after a lapse of a little delay from the transmission line delay time fluctuation of the data string, the phase comparison determination unit for comparing and comparing the plurality of write control signals and the read control signal, and the phase comparison determination result. And the write / read time phase margin is determined. Data delay control method characterized by having a selection circuit which is selected and read memory with. 2. When the phase comparison / judgment unit recognizes that the time phase margin of the memory currently being read has decreased, one of the other two memories has a memory write address controller having a safe phase margin. The data delay control method according to claim 1, wherein an address is preset.