JPH05161016A - Quantized width adjusting circuit utilizing dct conversion ac coefficient - Google Patents

Abstract

PURPOSE: To improve the S/N ratio by classifying an image into numerous blocks, applying DCT(discrete cosine transformation) processing to each block, using an AC value so as to make a quantization width variable depending on a degree of complicatedness of an image. CONSTITUTION: A DCT 10 receiving data subject to block formatting provides outputs of DC and AC coefficients. The absolute AC coefficient is given to an accumulator 30 and the accumulated coefficient is given to a scaling factor decision section 40, in which complicatedness of an image of each block is decided. The scaling factor depending on the complicatedness of the image being an output of an encoder 44 is applied to a quantization width decision section 50, in which the quantization width is decided. Furthermore, data processed by the DCT 10 are given sequentially to a shift register 70 and a linear quantization section 80 receiving shifted data quantizes the data by the quantization width decided by the decision section 50. Thus, the S/N ratio is improved and the hardware is simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quantization width adjusting circuit in an image compression type digital video processing system recommended by JPEG (joint group of CCITT and ISO), and in particular, it divides an image into a large number of blocks. The present invention relates to a quantization width adjusting circuit capable of increasing the S / N ratio by performing DCT processing for each block and varying the individualization width according to the complexity of an image by using an AC value.

[0002]

2. Description of the Related Art Generally, the image compression method recommended by JPEG is DCT for data compression in a digital image recording / reproducing apparatus as shown in FIG.
Quantize after conversion. At this time, the quantization width was determined by a quantization matrix of 8 × 8 blocks and a constant scaling factor S considering human visual characteristics. As described above, when the quantization width is determined by the constant scaling factor S, a very complicated image cannot be reproduced accurately, and a simple image requires a large amount of memory in the process.

[0003]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to classify an image into a large number of blocks and to add D to each block.
After CT processing, a complex image is given a large scaling factor S value to reduce the quantization width to reduce the data compression rate, and a simple image is given a reduced scaling factor S value to give a large quantization width. Another object of the present invention is to provide a quantization width adjusting circuit that can improve the S / N ratio by increasing the data compression rate.

Another object of the present invention is to divide an image into a large number of blocks, perform DCT processing, and then use AC values to change the quantization width depending on the complexity of the image for each block to simplify the hardware structure. Another object of the present invention is to provide a quantization width adjusting circuit that can do this.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings. A DCT 10 for inputting block-formatted block-by-block 8 × 8 data and serially outputting one DC coefficient and 63 AC coefficients;
ABS20 that takes the output AC coefficient of 10 and takes the absolute value
And an accumulator 30 for sequentially inputting and accumulating 63 AC coefficients having the absolute value of the ABS 20, and an image of each block by inputting the accumulated coefficients of the accumulator 30. Scaling factor determining unit 40 that determines a scaling factor according to the complexity state, and a quantization width adjusting unit 5 that determines a quantization width based on the scaling factor value output from the scaling factor determining unit 40.
0, an operation control unit 60 that receives a clock signal and counts it to generate an operation control signal of the accumulator 30 and the scaling factor determination unit 40, and a DCT process of the DCT 10 by 64 registers. A shift register 70 that sequentially shifts the stored data and delays it until a scaling factor is determined.
And a linear quantizer 80 that receives the data delayed by the shift register 70 and performs quantization with the quantization width determined by the quantization width adjuster 50. The accumulator 30 in the above configuration is configured such that when a clock is input, an adder 31 that adds an AC coefficient that is an absolute value of the ABS 20 and an A that is added by the adder 31 are added.
The scaling factor determining unit 40 is configured by a latch 32 that latches and outputs a C coefficient value, and the scaling factor determining unit 40 determines a range of the first reference value and the first scaling factor after receiving the output signal of the latch 32. And the output signal of the latch 32 are input and compared with a second reference, and then an over signal in the range of the first scaling factor is received from the first scaling factor generating means and logically combined to determine the second scaling factor range. The second scaling factor generating means and the output signal of the latch 32 are input and compared with a third reference value, and then an over signal in the range of the second scaling factor is received from the second scaling factor generating means and logically combined. Third scaling factor Third scaling factor generating means for determining the range, and fourth scaling factor for logically combining and receiving an over signal of the range of the third scaling factor from the third scaling factor generating means to determine the range of the fourth scaling factor. The operation control unit 60 includes a generating unit and an encoder 44 that receives the determination signal of the scaling factor range from the first to fourth scaling factor generating units and outputs the encoded signal. A ring counter 61 that outputs a counting value to Q0-Q5 and a counting value that is output to the output terminals Q0-Q5 of the ring counter 61 are input to generate reset signals for the accumulator 30 and the scaling factor determining unit 40. You NOR gate 62
And an counting signal output from the output terminals Q0-Q5 of the ring counter 61 to generate an enable signal for the scaling factor determining unit 40.
And a D gate 63. An embodiment of the present invention will be described in detail based on the above configuration with reference to FIG.

The DCT 10 for inputting the block-formatted 8 × 8 data through the input terminal P1 outputs one DC coefficient and 63 AC coefficients serially by being clocked through the clock terminal P2.
The AC coefficient output by the DCT 10 has + and-values. Therefore, the ABS 20 which inputs the coefficient output from the DCT 10 takes an absolute value and outputs it. The ABS
The adder 31 for sequentially inputting the AC coefficients, which have the absolute values output at 20, outputs 63 ACs according to the clock signal.
The coefficient is added and output. AC added by the adder 31
The latch 32, which receives the coefficient, latches and outputs it according to the clock input through the clock terminal P2. Further, when the ring counter 61 for inputting a clock signal outputs 000000 to the clock terminals Q0-Q5, the NOR gate 62 outputs a "high" signal to output the latch 32 and the first-first signal.
The third comparators 41-43 and the encoder 44 are reset. The output of the ring counter 61 is 11
When it is 1111, the AND gate 63 outputs a "high" signal to enable the first to third comparators 41-43 and the encoder 44. The value output from the latch 32 is input to the input terminal A of the first comparator 41,
If it is smaller than the first reference value compared with the first reference value input to the input terminal B, it is determined as a first scaling factor and applied to the first input terminal 0 of the encoder 44.

However, if the value output by the latch 32 is the same as or larger than the first reference value, the output value of the latch 32 is input to the input terminal C of the second comparator 42. Second input through the input terminal D
When compared with the reference value and smaller than the second reference value, the output value of the first comparator 41 is determined as a second scaling factor through the OR gate OR1 and applied to the input terminal 1 of the encoder 44.

When the output value of the latch 32 is the same as or larger than the second reference value, the output value of the latch 32 is input to the input terminal E of the third comparator 43 and passed through the input terminal F. When compared with the input third reference value and smaller than the third reference value, the output value of the second comparator 42 is input to the output value of the second comparator 42 and the AND gate AN2 through the OR gate OR2. Is determined as a logical combination and applied to the input 2 of the encoder 44.
However, when the output value of the latch 32 is equal to or larger than the third reference, the output of the third comparator 43 is input to the OR gate OR3 and logically combined to determine the fourth scaling factor, which is determined by the encoder. Applied to the input terminal 3 of 44.

Accordingly, the encoder 64 encodes and outputs the scaling factor output according to the complexity of the image. The encoder 64
The scaling factor, which is the output of, is applied to the quantization width determining unit 50 to determine the quantization width. In addition, the DC
The shift register 70 for sequentially inputting the data subjected to the DCT processing at T10 is composed of 64 registers and shifts, but the DCT transform coefficient is delayed until the scaling factor required for quantization is determined. Let The linear quantizer 80, which receives the data shifted and output to the shift register 70, quantizes the data according to the quantization width determined by the quantization width determiner 50.

[0010]

As described above, after the block-formatted 8 × 8 data is subjected to the DCT processing, a block having a complex image of the image signal has a small quantization width to reduce the compression rate, and a block having a simple image is There is an advantage that the S / N ratio can be improved by widening the quantization width and increasing the compression rate, and the hardware configuration can be simplified and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an algorithm block recommended by JPEG.

FIG. 2 is a system configuration diagram according to the present invention.

[Explanation of symbols]

 10 DCT 20 ABS 30 Accumulator 40 Scaling Factor Determining Section 50 Quantization Width Determining Section 60 Operation Control Section 70 Shift Register 80 Linear Quantization Section

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 11/04 Z 9187-5C

Claims (4)

[Claims] 1. A block-formatted block receives 8 × 8 data, serially outputs one DC coefficient and 63 AC coefficients, and inputs a DCT (10) and a scaling factor to determine a quantization width. And a linear quantizer (50) for inputting the data subjected to the DCT processing by the DCT (10) and performing quantization according to the quantization width of the quantization width determiner (50). 8
0) in the quantization width adjusting circuit
The ABS (20) that takes the absolute value by inputting the output coefficient processed in (10) and the 63 AC coefficients that take the absolute value of the ABS (20) are sequentially input to set the cycle of the clock. An accumulator (30) for accumulating together and the accumulator (3
0) inputting the accumulated AC coefficient and determining a scaling factor according to the complexity of the image of each block, a scaling factor determining unit (40), receiving a clock signal and counting and counting the accumulator ( Three
0) and an operation control unit (60) for generating an operation control signal of the scaling factor determination unit (40), and the DCT.
A quantization width adjusting circuit, comprising: a shift register (70) which receives the data subjected to the DCT processing in (10), sequentially shifts the data, and delays the data until a scaling factor is determined. 2. An operation control unit (60), a ring counter (61) for inputting a clock signal, counting, and outputting a counting value to output terminals (Q0-Q5),
Output terminal (Q0-Q5) of the ring counter (61)
Means for generating the reset signal of the adder (31) and the scaling factor determining unit (40) by inputting the counting value output to the output terminal (Q0-Q5) of the ring counter (61). 2. The quantization width adjusting circuit according to claim 1, further comprising means for inputting a counting value to generate an enable signal of the scaling factor determining unit (40). 3. The scaling factor determination unit (4)
The quantization width adjusting circuit according to claim 1, wherein 0) is connected to the quantization width determining unit (50). 4. The quantization width adjusting circuit according to claim 1, wherein the shift register (70) is connected to the linear quantizer (80).