DE4134554A1 - Digital image quantisation width adjustment circuit - uses digital cosine transformation signals with coefficients generated in scaling process - Google Patents

Abstract

A discrete cosine transformation stage (10) for image data provides an output that is processed by a system having an absolute value converter (20), accumalator (30), sealing factor stage (40) and quantisation units (50,80). One quantisation unit (50) operates upon the sealing factor data, while the other provides a linear operation on the output of the discrete cosine transformation stage. The width of the quantisation process is controlled its improve the signal to noise rafts. ADVANTAGE - Improved signal to noise rafts, simplified image processing hardware.

Description

Technical background

The present invention relates to a circuit for Set the quantization width of a digital image at a digital image processing system using the image ver. suggested by JPEG (Joint Group of CCITT & ISO) poetry.

In general, the image compression method proposed by JPEG, as shown in FIG. 1, includes the steps of performing a discrete cosine transform (DCT) on data to compress and quantize the transformed data. In this case, the quantization width is determined by a block quantization matrix 8 × 8, which is taken into account in the human visual characteristics and by a constant scaling factor S. The disadvantage of this method is that a very complicated quantized image cannot be reproduced exactly and that a simple image for processing requires an undesirably increased memory.

Summary of the invention

The object of the invention is a circuit for the setting len the quantization width of a digital image in over in accordance with the DCT-processed image data that the signal-to-noise ratio is improved.

Another object of the present invention is in it, a circuit for setting the quantization width to deliver a digital image that is simple can be manufactured.

In accordance with the present invention, a  Circuit for setting the quantization width of a digital image, which includes:

• a) a discrete cosine transformation means for the transform image data formatted into blocks which each have the size of 8 × 8 pixels, in a GS coefficient th and sixty-three WS coefficients that are output serially will;
• b) a quantization determining means for determining the Quantization width by receiving a scaling factor;
• c) a linear quantization circuit for quantizing the DCT-processed data output from the DCT mean are, according to the quantization width of the quantization Be mood;
• d) an ABS (absolute value) means for converting the DCT- processed data in absolute values;
• e) an accumulator for accumulating the absolute three sixty WS coefficients that are sequentially in accordance with Timer pulses are entered;
• f) a scaling factor determining means for determining a scaling factor corresponding to the image density of each Blocks of data by receiving the accumulated WS coefficients the accumulator;
• g) a function control means for generating a signal for control of the scaling factor determination function by means of and the accumulator by counting the timer pulses; and
• h) a shift register for the sequential shifting of the DCT processed data to delay until the scale ration factor is determined.

Brief description of the accompanying drawings

For a better understanding of the invention and to show how it can be made effective, refer to the associated drawings using an example sen. These show in

Fig. 1 is a block diagram of the algorithm proposed by JPEG algorithm;

Fig. 2 is a schematic diagram of the Sy stems invention.

Embodiment

Referring to Fig. 2, a discrete cosine transforming means 10 for transforming image data formatted into blocks each having 8 x 8 pixels into a GS coefficient and sixty-three WS coefficients are output serially , shown.

A quantization determining means 50 is to determine the quantization width by receiving a scaling factor. A linear quantization circuit 80 is to quantize the DCT processed data output from the DCT means in accordance with the quantization width of the quantization determination means 50 .

An ABS means 20 is intended to convert the DCT-processed data into absolute values. An accumulator 30 is intended to accumulate the absolute sixty-three AC coefficients that are input sequentially in accordance with the timing pulses. A scaling factor determining means 40 is to determine a scaling factor in accordance with the image density of each data block by receiving the accumulated WS coefficients of the accumulator 30 . A function control means 60 is to control a signal for controlling the function of the scaling factor determination means 40 and the accumulator 30 by counting timer pulses. A shift register 70 is intended to shift the DCT-processed data sequentially by the DCT 10 in order to delay until the scaling factor is determined.

The accumulator 30 consists of an adder 31 for adding the absolute values of the WS coefficients from the ABS 20 in response to timer pulses and of a latch circuit 32 for blocking the output of the adder 31 .

The scaling factor determining means 40 includes four scaling factor generators. The first scaling factor generator is intended to compare the output signal of the latch circuit 32 with a first reference value in order in this way to determine the range of the first scaling factor. The second scaling factor generator compares the output signal of the latch circuit 32 with a second reference value and logically links the signal that exceeds the range of the first scaling factor that has been generated by the first scaling factor generator to thereby reduce the range to determine the second scaling factor. The third scaling factor generator compares the output signal of the latch circuit 32 with a third reference value and logically combines the signal that exceeds the range of the second scaling factor generator that has been generated by the second scaling factor generator, in this way to determine the range of the third scaling factor. The fourth scaling factor generator logically links the signal that exceeds the range of the third scaling factor generated by the third scaling factor generator, in order in this way to determine the range of the fourth scaling factor. A coding device 44 is intended to code the signals which determine the ranges of the scaling factors which have been generated by the scaling factor generators one to four.

The function control means 60 includes a ring counter 61 for counting the timer pulses, a NOR gate 62 for generating the reset signal of the accumulator 30 and the scaling factor determining means 40 by receiving the counted value by the output terminals Q 0- Q 5 of the Ring counter 61 is output and an AND gate 63 for the generation of a start-up signal of the scaling factor determining means 40 by receiving the counted value which has been output by the output terminals Q 0- Q 5 of the ring counter.

The 8 × 8 formatted block is fed through an input P 1 to DCT means 10 to serially output a GS coefficient and sixty three WS coefficients in response to the timer pulses input through a timer port P 2 . The WS coefficients output by the DCT 10 have positive (+) and negative (-) values, which are converted into absolute values by the ABS. The absolute values of the AC coefficients output from the ABS 20 are sequentially input to the adder 31 to add the sixty-three AC coefficients in response to the timer pulses. The added WS coefficients are locked by the latch circuit 32 in response to the timer pulses which are received via the timer connection P 2 .

If the signals output by the timer connections Q 0- Q 5 of the ring counter 61 have the value 000000, then the NOR gate 62 generates a high signal to the latch circuit, the comparators one to three 41-43 and to reset the coding device 44 . Alternatively, if the output signals of the ring counter 61 have the value 111111, the AND gate 62 generates a high signal in order to set the comparators one to three 41-44 and the coding device 44 in operation. The first comparator 41 compares the latched signal of the latch circuit 32 , which is input through an input terminal A, with the first reference value, which is input through another input terminal B. If the latched signal has a lower value than the first reference value, then it is determined as the first scaling factor that is applied to the first input terminal 0 of the encoder 44 .

However, if the latched signal of the latch circuit 32 has a value equal to or greater than the first reference value, then it is applied to an input terminal C of the second comparator 42 for comparison with the second reference value by another Input port D is entered ben. If the locked signal has a value smaller than the second reference value, then the output signal of the first comparator 41 by the OR gate OR 1 and the output signal of the second comparator 42 by the AND gate AN 1 are logically linked to one another To generate the second scaling factor, which is applied to the input terminal 1 of the encoder 41 .

Furthermore, when the latched signal of the latch circuit 32 has a value equal to or larger than the second reference value, it is supplied to an input terminal E of the third comparator 43 to compare it with the third reference value by another Input port F is entered ben. Then, when the locked signal has a value smaller than the third reference value, the output signal of the second comparator 42 through the OR gate OR 2 and the output signal of the third comparator 43 through the AND gate AN 2 are logically linked to one another produce third scaling factor, which is applied to the input terminal 2 of the coding device 44 . However, if the latched signal of the latch circuit 32 has a value which is equal to or greater than the third reference value, then the output signals of the third comparator 43 are logically combined by the OR gate OR 3 in order to add the fourth scaling factor generate, which is applied to the input terminal 3 of the encoder 44 .

The result is that the encoder 44 encodes the scaling factor that has been generated according to the density of the image. The scaling factor of the encoder 44 is fed to the quantization determining means 50 in order to determine the quantization width.

The shift register 70 , which is made up of sixty-four registers, shifts the DCT-processed data which are sequentially input from the DCT means so as to delay the DCT coefficients until the scaling factor is determined for quantization. The shifted data of the shift register 70 are quantized by the linear quantization circuit 80 in accordance with the quantization width determined by the quantization determination means 50 .

As stated above, the scarf according to the invention tion the compression ratio of the blocks to one block of 8 × 8 formatted data thereby reduced or enlarged, that the quantization width according to the image density of the Blocks is reduced or enlarged, thereby both  Signal-to-noise ratio improved and also the hardware for it is simplified.

The above description shows only one preferred embodiment tion form of the invention. There are various modifications for obvious to those who are familiar with the field of technology are without losing sight of the scope of the present invention dung deviates, which is only limited by the claims. Therefore, the embodiment shown and described is only illustrative, not restrictive.

Claims (4)

1. Circuit for setting the quantization width of a digital image, characterized by
discrete cosine transform means ( 10 ) for transforming image data formatted into blocks each having 8 x 8 pixels into a GS coefficient and sixty three WS coefficients which are output serially;
quantization determining means ( 50 ) for determining the quantization width by receiving a scaling factor;
a linear quantization circuit ( 80 ) for quantizing the DCT-processed data output from the DCT means ( 10 ) according to the quantization width of the quantization determining means ( 50 );
ABS (absolute) means ( 20 ) for converting the DCT processed data into absolute values;
an accumulator ( 30 ) for accumulating the absolute sixty three AC coefficients that are input sequentially in accordance with timer pulses;
scaling factor determining means ( 40 ) for determining a scaling factor in accordance with the image density of each of said data blocks by receiving the accumulated WS coefficients of the accumulator ( 30 );
function control means ( 60 ) for generating a signal to control the function of the scaling factor determining means ( 40 ) and the accumulator ( 30 ) by counting timer pulses; and
a shift register ( 70 ) for sequentially shifting the DCT processed data of said DCT ( 10 ) to delay until the scaling factor is determined. 2. Circuit according to claim 1, characterized in that the function control means ( 60 ) comprises
a ring counter ( 61 ) for counting the timer pulses;
a reset signal generator for generating the reset signal of the accumulator ( 30 ) and the scaling factor determining means ( 40 ) by receiving the counted value derived by the output terminals Q 0 -Q 5 of the ring counter ( 61 ); and
a start-up signal generating means for generating a start-up signal of the scaling factor determining means ( 40 ) by receiving the counted value output from the output terminals Q 0 -Q 5 of the ring counter ( 61 ). 3. A circuit according to claim 1, characterized in that the scaling factor determining means ( 40 ) is connected to the quantization determining means ( 50 ). 4. A circuit according to claim 1, characterized in that the shift register ( 70 ) is connected to the linear quantization circuit ( 80 ).