JPH0513425B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video signal processing circuit, and particularly relates to a video signal processing circuit.
This relates to a noise reduction device for video signals such as VTRs or televisions.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional video signal processing circuit disclosed in Japanese Patent Application Laid-Open No. 130835/1983.
In the figure, 1 is the input chroma signal, and 4 is 1H which delays this input chroma signal by one horizontal scanning period (1H).
Delay line, 5 is the output of this 1H delay line 4, 12 is an adder circuit that adds the delay line output 5 and the input chroma signal 1, 13 is the vertical high frequency component which is the output of the adder circuit 12, 14 is the vertical component 15 is a vertical noise signal; 16 is a level adjustment circuit that adjusts the level of the vertical noise signal 15; 17 is an inverter for inverting the phase of the output signal of the level adjustment circuit 16; 20 is an addition circuit that adds the output signal of the phase inversion circuit 17 and the input chroma signal 1, and 21 is an output chroma signal.

Next, the operation will be explained. Input chroma signal 1
becomes the delay line output 5 delayed by 1H by the 1H delay line 4, and is added to the input chroma signal 1 which has not been delayed by the addition circuit 12. That is, the 1H delay line 4 and the adder circuit 12 constitute a comb filter, and the vertical high frequency component 13 in the vertical spatial frequency band is obtained as an output. High-level signal components of this vertical high-frequency component 13 are cut off by an amplitude limiting circuit 14, resulting in a vertical noise signal 15 consisting only of low-level noise components. This noise signal 15 is sent to the next level adjustment circuit 1.
6, the signal is adjusted to approximately the same level as the noise level contained in the input chroma signal 1, and then the phase is inverted by the phase inverting circuit 17. The output signal of this phase inversion circuit 17 is added to the input chroma signal 1 by an adder circuit 20, thereby obtaining an output chroma signal 21 from which noise components have been removed from the input chroma signal 1.

In addition, the comb filter part shown in FIG. 3 can also be constructed with a circulating comb filter.
It is known to provide the same effects as above.

[Problem that the invention seeks to solve]

However, in such conventional video signal processing circuits, especially those using recursive comb filters, the phase characteristics of the filter are not linear, so a signal may appear in a part where there is no signal, or a signal may appear in a part where there is no signal. There are times when the signal is not in the right place. Therefore, when such a circuit device is placed in an automatic phase control (APC) loop, the APC
There was a problem that the loop responsiveness was disturbed and APC malfunctioned. Similarly, during high-speed picture search, noise may be generated due to the transient response of the circuit device, and in the circuit device, the amplitude is limited in the amplitude limiting circuit 14, but all signal components other than noise are removed. Therefore, the remaining signal components are added to the adder circuit 2.
By processing the signal at 0, not only noise but also high-frequency components in the input chroma signal are removed.
Depending on the mode (particularly the standard mode), there is a problem in that the negative effect of image quality deterioration due to vertical resolution deterioration is greater than the noise removal effect.

The present invention has been made in view of the above points, and an object of the present invention is to provide a video signal processing circuit that can eliminate the adverse effects caused by passing the video signal through the video signal processing circuit, and can reduce deterioration in image quality.

[Means for solving problems]

The video signal processing circuit according to the present invention processes a signal obtained through a comb filter and removes noise components from the input signal. Alternatively, in a device that emphasizes the high-frequency component, a calculation stopping means is provided to stop the function for a desired period and output the input signal as it is.

[Effect]

In this invention, the input of the high-frequency signal to the arithmetic circuit is stopped for a desired period, so that only the input signal that is the other input of the arithmetic circuit is output,
The input signal becomes the output signal as is.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In Figure 1, 1 is the input chroma signal, 2 is the adder circuit, 3 is the adder circuit output, 4 is the 1H delay line,
5 is the delay line output, 6 is the delay line output 5 multiplied by K (K<
1) a level adjustment circuit that adjusts the amount of feedback;
7 is a phase inversion circuit, 8 is a feedback signal, 9 is a level adjustment circuit that multiplies the delay line output 5 by (1-K) for level normalization, 10 is a phase inversion circuit, and 11 is the output of a cyclic comb filter. , 12 is an adding circuit that adds this output 11 and the input chroma signal 1.
Further, 13 is a vertical high frequency component, 14 is an amplitude limiting circuit, 15 is a vertical noise signal, 16 is a level adjustment circuit, 17 is a phase inversion circuit, 20 is an addition circuit,
21 is an output chroma signal, which is similar to the conventional one shown in FIG.

Further, 19 is a first calculation stop instruction signal,
The period indicated by this signal is, for example, a color burst period. 22 is a standard speed recording and reproduction mode signal (hereinafter referred to as standard mode instruction signal);
23 is an OR gate having two inputs, the first calculation stop instruction signal 19 and the standard mode instruction signal 22;
24 is a second arithmetic stop instruction signal which is the output of this OR gate 23; 18 is a switch that is controlled on and off by this second arithmetic stop instruction signal 24, the first terminal of which is connected to the phase inversion circuit described above; 17, and its second terminal is grounded.
This switch 18 may be an analog switch or a transistor switch circuit. Then, by the above OR gate 23 and switch 18,
The addition circuit 20 for the output of the phase inversion circuit 17
A computation stopping means is configured to stop the input to the input signal for a desired period of time, and output the input signal for the desired period as it is. Note that the above OR gate 23 can be constructed from a diode.

Next, the operation will be explained.

Input chroma signal 1 is input to adder circuit 2, and its output 3 is input to 1H delay line 4. The feedback amount K of the delay line output 5 is adjusted by a level adjustment circuit 6, and the phase of the delay line output 5 is inverted by a phase inversion circuit 7, and then input as a feedback signal 8 to an addition circuit 2. That is, these circuits constitute a cyclic comb filter. This output, the delay line output 5, is
The signal is multiplied by (1-K) by the level adjustment circuit 9 and normalized to the level of the input signal, and then phase inverted by the phase inversion circuit 10 to become the cyclic comb filter output 11. This output 11 is added to the input chroma signal 1 in an adder circuit 12, resulting in a vertical high frequency component 13. The high level signal of the vertical high frequency component 13 is cut off by the amplitude limiting circuit 14. Here, since the high level signal is considered to be a signal component and the low level signal is considered to be noise, the output of the amplitude limiting circuit 14 becomes the vertical noise signal 15. The vertical noise signal 15 obtained in this way is adjusted to almost the same level as the noise component in the input chroma signal 1 by the level adjustment circuit 16, and is output after being phase-inverted by the phase inversion circuit 17. Ru.

Here, when the switch 18 is turned off by the second calculation stop instruction signal 24, that is, when the recording/reproducing time mode is the long mode and the signal is not in the burst period, the standard mode instruction signal 22 and the first When the arithmetic stop instruction signal 19 is in an inactive state, the phase-inverted noise signal is input to the adder circuit 20 and is arithmetic-processed with the input chroma signal 1, which is one input of the adder circuit 20. Therefore, an output chroma signal 21 from which noise has been removed is obtained as the output of the adder circuit 20.

On the other hand, the switch 18 outputs the second calculation stop signal 24.
When the standard mode indication signal 2 is in the on state, i.e. in the standard mode or the signal is in a burst period, the standard mode indication signal 2
When the second or first calculation stop instruction signal 19 is in the active state, the output of the phase inversion circuit 17 is grounded via this switch 18, and the input of the noise signal to the addition circuit 20 is stopped. As a result, the input chroma signal 1, which is one input signal of the adder circuit 20, becomes the output chroma signal 21 as it is.

In the device of this embodiment, the OR gate 23
and a switch 18 are provided so that no signal processing is performed during standard speed recording and reproduction and during the burst period, that is, the input chroma signal 1 is used as the output chroma signal 21 as it is, so that the burst signal is not disturbed. Therefore, the APC operation is performed normally, and the influence of image quality disturbance caused by the processing circuit can be reduced.

FIG. 2 shows another embodiment of the present invention, which differs only in the construction of the switch 18 from the embodiment described above. That is, in the above embodiment, the switch 18
is provided between the phase inversion circuit 17 and the ground, but in the embodiment shown in FIG. 2, it is provided between the phase inversion circuit 17 and the addition circuit 20.

The operation is almost the same as the above embodiment, but in this embodiment, when the switch 18 is on, an output signal with reduced noise is obtained, and when the switch 18 is off, an output signal that is the same as the input signal is obtained.

In the above embodiment, the calculation stop period due to the first calculation stop instruction signal is set as the burst period, but the calculation may be stopped not only during the burst period but also during the horizontal blanking period. In addition to the same effects as the above example,
You can get a TV signal that complies with the NTSC standard. Further, logical operations may be performed using a plurality of VTR mode instruction signals, such as a high-speed picture search mode and a standard speed mode.

Furthermore, in the above embodiments, the case where the input signal is a chroma signal has been described, but the input signal may also be a luminance signal.

Furthermore, in the above embodiment, the switch was located after the phase inversion circuit, but this position may be anywhere between the adder circuit 12 and the adder circuit 20, and the same effect as in the above embodiment can be obtained. play.

Furthermore, in the above embodiment, the phase inversion circuit 17
However, in the present invention, the phase inversion circuit 17 is removed and addition processing is performed on the input signal, that is, high-frequency components are emphasized. It can also be applied to objects, and the same effects as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a means including a cyclic comb filter for extracting high-frequency components in a vertical spatial frequency band from an input video signal, and an amplitude-limiting means for limiting the amplitude of the high-frequency components. , in a video signal processing circuit comprising arithmetic processing means for arithmetic processing the amplitude limiting signal from the amplitude limiting means and the input video signal, when the recording and reproducing time mode is the standard time mode, the recording and reproducing period; When the recording and playback time mode is long mode, calculation processing is stopped for a predetermined period corresponding to the synchronization signal, and the input video signal is output during this stop period, so the above signal processing is performed as necessary. This has the effect of preventing harmful effects and reducing image quality deterioration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a video signal processing circuit according to one embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the invention, and FIG. 3 is a block diagram showing a conventional video signal processing circuit. be. 1... Input chroma signal, 2, 12, 20... Addition circuit, 4... 1H delay line, 6... Level adjustment circuit, 7, 10, 17... Phase inversion circuit, 9... Level adjustment circuit, 14 ...Amplitude limiting circuit, 18...
Switch, 19...First calculation stop instruction signal, 2
1...Output chroma signal, 22...Standard speed recording and playback mode signal, 23...OR gate, 24...
...Second calculation stop instruction signal. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. Means including a cyclic comb filter for extracting high frequency components in a vertical spatial frequency band from an input video signal, amplitude limiting means for limiting the amplitude of the high frequency components, and In a video signal processing circuit comprising an arithmetic processing means for arithmetic processing the amplitude limiting signal from the limiting means and the input video signal, when the recording and reproducing time mode is the standard time mode, the recording and reproducing period, and the recording and reproducing period. A video signal processing circuit characterized in that when the time mode is a long time mode, the arithmetic processing is stopped for a predetermined period corresponding to a synchronization signal, and the input video signal is outputted during this stop period. 2. The video signal processing circuit according to claim 1, wherein the video signal is a luminance signal. 3. The video signal processing circuit according to claim 1, wherein the video signal is a color signal.