JPH05101023A - Debugging method for processor - Google Patents

Abstract

PURPOSE:To generate an unmatch error falsely and to easily realize evaluation environment by performing different processing by two processors by informing interruption to one of duplex processors. CONSTITUTION:A microprocessor 11 being operated in a monitoring mode fetches the output signal of a microprocessor 10 being operated in a normal mode at every bus cycle, and compared it with a signal generated by its own processor, and informs unmatch to the outside by a fault detection signal 12 when detecting it. FFs 20-22 are connected to a bus 6, and software can be freely set/reset on them, and the interruption is informed to a corresponding microprocessor when '1' is set. As a result, since the microprocessor accepting the interruption performs interruption processing by interrupting the processing under execution at that time, difference in inertial operations between the microprocessor on the other side occurs, which generated the unmatch. Thereby, a false unmatched error can be generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a debug method for a processor, and more particularly to a debug method for a dual processor used in an information processing apparatus that requires high reliability.

[0002]

2. Description of the Related Art Generally, although a mismatch error of a dual processor does not occur frequently, if it occurs, it has a great influence on the entire system, and in order to guarantee the operation such as switching to a standby system, software / hardware is included. It is necessary to fully evaluate on an overall scale.

In the conventional debugging method of this type of processor, in order to generate a pseudo mismatch, the address, data, control signal indicating the access type, etc. output from the executing microprocessor are inverted and monitored. A dummy circuit for inputting to the microprocessor on the side is provided outside.

By the way, in the case of a duplex processor, it is normal to stop immediately when a mismatch error is detected. This is because even if a mismatch error is detected, it is not possible to specify the failed processor by duplication alone, and therefore it is not possible to allow a possibly failed processor to continue processing. However, in order to recover the stopped processor, it has to be reset by some external method (such as a reset switch or a reset instruction from another device).

As a method for resynchronizing pseudo asynchronism and causing the same operation, a reset switch for resetting only a microprocessor is conventionally prepared,
It is operated manually,

The above-described conventional debug method for a processor is not preferable because it causes an increase in the gate amount of the external circuit and an increase in the delay time due to the external circuit. In particular, an increase in the delay time may cause a mismatch to be detected in the normal operation due to the delay of the comparison target signal.

Further, re-synchronization of the duplex processor not only makes debugging inefficient due to manual intervention, but also deteriorates maintenance operability. For example, if the test program that is always executed before the start of operation includes a pseudo-failure test of the redundant processor, the reset button must be pressed halfway each time this program is executed. There is a problem that such an operation form lacks consistency.

[0007]

The method of the first invention is as follows.
A microprocessor that operates in the execution mode and a microprocessor that operates in the monitoring mode are duplicated, and the microprocessor that operates in the execution mode and the microprocessor that operates in the monitoring mode have the same phase clock. The microprocessor that is supplied and operates in exactly the same manner and that operates in the execution mode outputs an output signal to the outside, and the microprocessor that operates in the monitoring mode captures the output signal internally every bus cycle and In the debugging method of the processor having a function of immediately outputting a mismatch notification signal to the outside when a mismatch is detected by comparing with the signal of (1), an interrupt generating means for notifying an interrupt to either one of the duplicated microprocessors is provided. By the above 2
Causes a difference in behavior between the two microprocessors,
The non-coincidence signal is output.

A second aspect of the present invention is a processor configured by duplicating a microprocessor operating in an execution mode and a microprocessor operating in a monitoring mode, the microprocessor operating in the execution mode.
The same phase clock is supplied to the microprocessor operating in the monitoring mode, the microprocessor operates in exactly the same manner, the microprocessor operating in the execution mode outputs an output signal to the outside, and the microprocessor operating in the monitoring mode is In the debug method of the processor having the function of outputting the output signal internally for each bus cycle and comparing it with its own signal, and immediately detecting a mismatch, the mismatch notification signal is output to the outside. An interrupt generation means for notifying an interrupt to either one, a processing continuation control means for continuing the operation of the microprocessor operating in the execution mode even when the non-match signal is output, and a duplication of the duplicated micro processor according to software instructions. Set up reset generation means to initialize the processor. Characterized in that was.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the first invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a first embodiment of the present invention. The redundant processor unit 1 has two microprocessors 10 and 11, and the microprocessor 10
Is in the execution mode, and the microprocessor 11 is in the monitoring mode.

The microprocessor 11 operating in the monitor mode fetches the output signal of the microprocessor 10 every bus cycle, compares it with the signal generated by itself, and detects a mismatch if it detects a mismatch. Signal 1
Notify the outside in 2.

Dual microprocessor 10, 1
1 is connected to the bus 6 via the buffer 5. Further, the microprocessors 10 and 11 have a function of disconnecting the microprocessor itself from an external circuit by setting all output signals in a high impedance state according to an instruction from the outside.

In this example, the failure detection signal 12 is directly input to the execution-side microprocessor 10. When the monitoring-side microprocessor 11 detects a mismatch and activates the failure detection signal 12, the execution-side microprocessor 10 is activated. The processor 10 is immediately disconnected from the bus 6 and stopped.

During normal operation, the microprocessors 10 and 11 operate in synchronization with each other and perform exactly the same processing. Therefore, unless either one of the microprocessors malfunctions, the signals of both processors match and the failure detection signal 12 remains inactive.

If a signal inconsistency is detected between the two microprocessors due to an internal failure of the microprocessor or a soft error in a special environment, the failure detection signal 12 becomes active, and at this time, the operation is performed in the execution mode. The operating microprocessor 10 is stopped.

Generally, in a system adopting a dual structure of a microprocessor, a plurality of sets of the dual structure are prepared, all the sets other than the operating one are in a standby state, and when one operating set fails, the system is in a standby state immediately. A redundant configuration is adopted in which the group takes over the processing. Therefore, for a dual-structured microprocessor, when a mismatch is detected, the operating microprocessor may be immediately stopped and the rest may be left to the standby system.

In the evaluation of the redundant system as described above, it is very important to evaluate the operation of the standby system after the detection of the mismatch error and the software for managing the entire system. It is necessary to prepare a means capable of generating.

As a means for this, the present invention provides hardware that enables software to intentionally notify an interrupt to each of the duplicated microprocessors. An interrupt generation circuit 2 is prepared in FIG. 1, and the interrupt generation circuit 2 is composed of three flip-flops 20, 21 and 22.

The flip-flop 20 is for setting the debug mode. When set to "1", the flip-flop 20 enters the debug mode and the flip-flops 21 and 22 are enabled.
The flip-flop 21 is connected to the interrupt input terminal of the microprocessor 10 via the signal line 210, and the flip-flop 22 is connected to the microprocessor 11 via the signal line 220.
An interrupt is generated when the interrupt input terminals are connected and "1" is set in these flip-flops.

The flip-flops 20 to 22 are connected to the bus 6 and can be freely set / reset by software. When "1" is set in the flip-flop 20 and "1" is set in either one of the flip-flops 21 or 22, an interrupt is notified to the corresponding microprocessor.

As a result, the microprocessor which has accepted the interrupt temporarily interrupts the processing being executed at that time to perform the interrupt processing, and therefore, the microprocessor which is trying to continue the processing being executed at that time is called the other microprocessor. A difference in internal operation occurs between them, resulting in inconsistency.

In many cases of duplex processors, it is common to stop as soon as a mismatch error occurs. However, in the present invention, the means for continuing the processing even if a mismatch error is detected, and the instruction of the software,
Means are provided for initializing and resynchronizing the duplexing processor. FIG. 2 is a diagram showing an embodiment of the second present invention showing such a concrete example, and additionally has a reset generation circuit 3 and a process continuation control circuit 4.

The reset generation circuit 130 includes a flip-flop 30 and can be freely set / reset by software. When the flip-flop 30 is set to "1" in the debug mode (the flip-flop 120 is "1"), the reset generation circuit 130 outputs the reset signal 300 to the duplex processor for a certain period of time.

The processing continuation control circuit 4 uses the failure detection signal 11
2 and the signal line 200 are input, and the stop signal 40 is output to the microprocessor 110 in the execution mode. When the stop signal 40 becomes active, the microprocessor 110 is logically disconnected from the bus 106 because all output signals such as address lines are not driven.

The processing continuation control circuit 4 activates the stop signal 40 as it is to stop the microprocessor 110 when the microprocessor 111 outputs a failure detection signal 112 in which a mismatch error is detected during normal operation. In the mode, even if the failure detection signal 112 is output, the stop signal 40 is not activated, and the microprocessor 110 is allowed to continue the processing.

As a result, the microprocessor 110 can continue the processing even after the pseudo mismatch error is generated. Therefore, by setting the flip-flop 30 to "1", the microprocessors 110 and 111 are reset and reset. It is possible to synchronize.

[0027]

As described above, according to the present invention, by notifying one of the duplicated processors of an interrupt and causing the two processors to perform different processing, a pseudo mismatch error is generated and the evaluation environment is facilitated. Will be realized. Also,
In the debug mode, even if a mismatch error occurs, the microprocessor in the execution mode does not stop and the process continues as it is, and the redundant processor can be reset by software. It has the effect of improving the quality and realizing a consistent evaluation environment.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the first present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

[Explanation of symbols]

1,100 Duplex processor unit 2,120 Interrupt generation circuit 4 Processing continuation control circuit 5,105 Buffer 6,106 Bus 10,11,110,111 Monitoring mode microprocessor 12,112 Failure detection signal 20,21,22,20 , 120, 120, 122
Flip-flop 130 Reset generation circuit

Claims (2)

[Claims] 1. A processor configured by duplicating a microprocessor operating in an execution mode and a microprocessor operating in a monitoring mode, wherein the microprocessor operating in the execution mode and the microprocessor operating in the monitoring mode are provided. Is supplied with the in-phase clock,
The microprocessor operating in exactly the same manner and operating in the execution mode outputs an output signal to the outside, and the microprocessor operating in the monitoring mode captures the output signal internally every bus cycle and outputs it as its own signal. In comparison, in the debug method of the processor having a function of outputting a mismatch notification signal to the outside immediately when a mismatch is detected, by providing an interrupt generation unit that notifies an interrupt to one of the duplicated microprocessors, A processor debugging method characterized in that a difference in operation is generated between two microprocessors, and the mismatch signal is output. 2. A processor configured by duplicating a microprocessor operating in an execution mode and a microprocessor operating in a monitoring mode, wherein the microprocessor operating in the execution mode and the microprocessor operating in the monitoring mode are: The microprocessor operating in the execution mode outputs the output signal to the outside while being supplied with the in-phase clock and operating in exactly the same manner, and the microprocessor operating in the monitoring mode outputs the external output signal to the inside every bus cycle. Capture and compare with your own signal,
In a debugging method of a processor having a function of outputting a mismatch notification signal to the outside immediately when a mismatch is detected, by providing an interrupt generation means for notifying an interrupt to either one of the duplicated microprocessors, the two microprocessors are provided. Processing continuation control means for causing the difference in operation between the processors to output the non-coincidence signal, and continuing the operation of the microprocessor operating in the execution mode even when the non-coincidence signal is output, and a software instruction. And a reset generation means for initializing the duplicated microprocessor, thereby enabling resynchronization of the duplicated microprocessor.