JP3055249B2 - Processor debugging method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for debugging a processor, and more particularly to a system for debugging a dual-structured processor employed in an information processing apparatus requiring high reliability.

[0002]

2. Description of the Related Art In general, although a mismatch error of a duplicated processor does not frequently occur, if it occurs, it greatly affects the entire system. To guarantee operation such as switching to a standby system, software and hardware are required. It is necessary to fully evaluate the overall scale.

In a conventional debugging method of this type of processor, in order to generate a pseudo-mismatch, an address, data, a control signal indicating an access type, etc. output from an executing microprocessor are inverted and monitored. A false fault circuit for input to the microprocessor on the side is provided outside.

Incidentally, in the case of a duplicated processor, it is common to stop immediately upon detecting a mismatch error. This is because a failed processor cannot be identified even if a mismatch error is detected by duplexing alone, so that a processor that may have failed cannot continue processing as it is. However, in order to recover the stopped processor, it must be reset by some external method (such as a reset switch or a reset instruction from another device).

[0005] As a method of synchronizing pseudo-generated asynchronous signals again and operating them in the same manner, conventionally, a reset switch for resetting only the microprocessor has been prepared.
Operated by hand,

However, the conventional processor debugging method described above is not preferable because the gate amount of the external circuit increases and the delay time increases due to the external circuit. In particular, when the delay time increases, a mismatch may be detected even in the normal operation due to the delay of the signal to be compared.

Further, resynchronization of the duplicated processor due to manual intervention not only makes debugging inefficient, but also greatly deteriorates operability in maintenance. For example, if a test program always executed before the start of operation includes a false test for a duplicated processor, the reset button must be pressed halfway each time this program is executed. Such an operation form has a problem of lack of consistency.

[0007]

A first method according to the present invention is as follows.
A microprocessor configured to duplicate a microprocessor operating in the execution mode and a microprocessor operating in the monitoring mode, wherein the microprocessor operating in the execution mode and the microprocessor operating in the monitoring mode have the same phase clock. The microprocessor that is supplied and operates in exactly the same manner and operates in the execution mode outputs an output signal to the outside, and the microprocessor that operates in the monitoring mode captures the output signal internally every bus cycle and In a debug method of a processor having a function of outputting a mismatch notification signal to the outside immediately when a mismatch is detected by comparing with a signal of the same type, an interrupt generating means for notifying an interrupt to one of the duplicated microprocessors is provided. According to the above 2
Causes a difference in operation between the two microprocessors,
Outputting the mismatch signal.

According to a second aspect of the present invention, there is provided a processor in which a microprocessor operating in an execution mode and a microprocessor operating in a monitoring mode are duplicated, and a microprocessor operating in the execution mode,
The microprocessor operating in the monitoring mode is supplied with the same phase clock, operates in exactly the same way, the microprocessor operating in the execution mode outputs an output signal to the outside, and the microprocessor operating in the monitoring mode is The output signal is internally taken in every bus cycle, compared with its own signal, and when a mismatch is detected, in a processor debugging method having a function of immediately outputting a mismatch notification signal to the outside, in the debug method of the dual microprocessor, Interrupt generating means for notifying one of the interrupts, processing continuation control means for continuing the operation of the microprocessor operating in the execution mode even when the mismatch signal is output, and the duplicated microcontroller according to software instructions. Reset generation means for initializing the processor Characterized in that was.

[0009]

Next, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. The duplicated processor unit 1 has two microprocessors 10 and 11, and the microprocessor 10
Is operating in the execution mode, and the microprocessor 11 is operating in the monitoring mode.

The microprocessor 11 operating in the monitoring mode takes in the output signal of the microprocessor 10 internally every bus cycle, compares it with a signal generated by itself, and if a mismatch is detected, detects a failure. Signal 1
Notify outside at 2.

The duplicated microprocessors 10, 1
1 is connected to a bus 6 via a buffer 5. Further, the microprocessors 10 and 11 have a function of setting all output signals to a high impedance state and disconnecting the microprocessor itself from an external circuit in response to an instruction from the outside.

In this embodiment, the failure detection signal 12 is directly input to the microprocessor 10 on the execution side, and when the microprocessor 11 on the monitoring side detects a mismatch and activates the failure detection signal 12, the microprocessor 11 on the execution side is activated. The processor 10 is immediately disconnected from the bus 6 and stops.

In a normal operation, the microprocessors 10 and 11 are operating synchronously and perform exactly the same processing. Therefore, as long as one of the microprocessors does not malfunction, the signals of the two processors match, and the failure detection signal 12 remains inactive.

If a signal mismatch between the two microprocessors is detected due to an internal failure of the microprocessor or a soft error in a special environment, the failure detection signal 12 becomes active, and at this point, the microprocessor operates in the execution mode. Microprocessor 10 is stopped.

In general, in a system adopting a redundant configuration of a microprocessor, a plurality of pairs of the redundant configuration are prepared, and a set other than the active pair is in a standby state. A redundant configuration is adopted, in which a group takes over the processing. Therefore, for a microprocessor having a dual configuration, upon detecting a mismatch, the operating microprocessor may be stopped immediately and then left to the standby system.

In the evaluation of a system having a redundant configuration as described above, it is very important to evaluate the operation of a standby system after detecting a mismatch error and the evaluation of software for managing the entire system. It is necessary to provide a means capable of generating the following.

The present invention, as a means, provides hardware that enables each of the duplicated microprocessors to be notified of an interrupt intentionally by software. In FIG. 1, an interrupt generation circuit 2 is prepared, and the interrupt generation circuit 2 includes three flip-flops 20, 21, and 22.

The flip-flop 20 is for setting the debug mode. When the flip-flop 20 is set to "1", the mode is set to the debug mode, and the flip-flops 21 and 22 are enabled.
The flip-flop 21 is connected to an interrupt input terminal of the microprocessor 10 via a signal line 210, and the flip-flop 22 is connected to the microprocessor 11 via a signal line 220.
Are set to "1", an interrupt is generated.

The flip-flops 20 to 22 are connected to the bus 6 and can be freely set / reset by software. When "1" is set in the flip-flop 20, and "1" is set in either one of the flip-flops 21 and 22, an interrupt is notified to the corresponding microprocessor.

As a result, the microprocessor that has accepted the interrupt temporarily interrupts the processing being executed at that time and performs the interrupt processing. , A difference in internal operation occurs, and a mismatch occurs.

[0022] In many cases, a duplicated processor will stop immediately when a mismatch error occurs. However, in the present invention, by means of means for continuing processing even when a mismatch error is detected and instructions of software,
A means is provided for initializing and resynchronizing the duplicated processor. FIG. 2 is a diagram showing one embodiment of the second present invention showing such a specific example, and has a reset generation circuit 3 and a processing continuation control circuit 4 newly.

The reset generation circuit 130 includes a flip-flop 30 and can be freely set / reset by software. The reset generation circuit 130 outputs a reset signal 300 to the duplicated processor for a certain period when "1" is set in the flip-flop 30 in the debug mode (the flip-flop 120 is "1").

The processing continuation control circuit 4 outputs the failure detection signal 11
2 and the signal line 200, and outputs a stop signal 40 to the microprocessor 110 in the execution mode. When the stop signal 40 becomes active, the microprocessor 110 stops driving all output signals such as address lines and is logically disconnected from the bus 106.

The processing continuation control circuit 4 activates the stop signal 40 and stops the microprocessor 110 when the failure detection signal 112 in which the mismatch error is detected by the microprocessor 111 is output during normal operation. In the mode, the stop signal 40 is not activated even if the failure detection signal 112 is output, and the microprocessor 110 continues the processing as it is.

As a result, the microprocessor 110 can continue processing even after a pseudo mismatch error is generated. Therefore, by setting "1" to the flip-flop 30, the microprocessors 110 and 111 are reset and reset. It is possible to synchronize.

[0027]

According to the present invention, a pseudo mismatch error is generated by notifying an interrupt to one of the duplicated processors and performing different processing between the two processors, thereby facilitating the evaluation environment. To be realized. Also,
In the debug mode, even if a mismatch error occurs, processing can be continued without stopping the microprocessor in the execution mode, and the redundant processor can be reset by software. This has the effect of improving the performance and realizing a consistent evaluation environment.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the first invention.

FIG. 2 is a block diagram of one embodiment of the second invention.

[Explanation of symbols]

1,100 Redundant processor unit 2,120 Interrupt generation circuit 4 Processing continuation control circuit 5,105 Buffer 6,106 Bus 10,11,110,111 Monitoring mode microprocessor 12,112 Failure detection signal 20,21,22,20 , 120, 120, 122
Flip-flop 130 reset generation circuit

Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G06F 15/177 678 G06F 11/28 JICST file (JOIS) WPI (DIALOG)

Claims (2)

(57) [Claims] A microprocessor configured to duplicate a microprocessor operating in an execution mode and a microprocessor operating in a monitoring mode, wherein the microprocessor operating in the execution mode and the microprocessor operating in the monitoring mode are provided. Is supplied with an in-phase clock,
Operating in exactly the same way, the microprocessor operating in the execution mode outputs an output signal to the outside, and the microprocessor operating in the monitoring mode takes in the output signal internally every bus cycle and In a debug method of a processor having a function of immediately outputting a mismatch notification signal to the outside when a mismatch is detected, the interrupt generation means for notifying an interrupt to one of the duplexed microprocessors is provided. A debug method for a processor, which causes a difference in operation between two microprocessors and outputs the mismatch signal. 2. A microprocessor in which a microprocessor that operates in an execution mode and a microprocessor that operates in a monitoring mode are duplicated, and a microprocessor that operates in the execution mode and a microprocessor that operates in the monitoring mode include: The same-phase clock is supplied, the microprocessor operates in exactly the same manner, the microprocessor operating in the execution mode outputs an output signal to the outside, and the microprocessor operating in the monitoring mode outputs the external output signal internally at every bus cycle. Capture it, compare it to your own signal,
In a debug method of a processor having a function of immediately outputting a mismatch notification signal to the outside when a mismatch is detected, an interrupt generating means for notifying one of the duplexed microprocessors of an interrupt is provided. Processing continuation control means for causing the difference between the processors to output the mismatch signal, and for continuing the operation of the microprocessor operating in the execution mode even when the mismatch signal is output; And a reset generating means for initializing the duplicated microprocessor, thereby enabling resynchronization of the duplicated microprocessor.