JPH0488514A - Light emitting element array - Google Patents

Abstract

PURPOSE:To erase information by incident light from the outside by connecting a control electrode. CONSTITUTION:When a light emitting thyristor T(3) is turned on, an anode current IA is set higher than the minimum current Ih to maintain the on-state of the light emitting thyristor T(3). In such a state, when the base of a phototransistor P(3) is irradiated with light from the outside, a photoelectric current generated in the inside of the phototransistor P(3) is amplified, and a current IPT can be pulled in from the collector. When the current IPT is sufficiently high and no sufficient anode current IA flows on the anode of the light emitting thyristor T(3), the light emitting thyristor T(3) is turned off.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a light emitting element array having a self-scanning function capable of erasing information written on the light emitting elements by inputting light, and particularly relates to The present invention relates to a light emitting element array suitable for application to optical information processing such as optical computing.

[Prior Art] FIG. 6 is an equivalent circuit diagram showing a conventional light emitting element array. In FIG. 6, T. ,~T19. are light emitting thyristors (light emitting elements) whose cathodes are grounded. Each light emitting thyristor T,. , ~T31. gate (
(first control electrodes) are connected by coupling diodes D0 to D5. Also, a light emitting thyristor T. ,~
The gates of TI%) are connected to a DC power supply of power supply voltage VGK (in this conventional example, it is assumed to be 5 [■]) through a gate load resistor R4.

On the other hand, the light emitting thyristor T,. , is connected via an anode load resistor RA to a supply line to which a start pulse φ is supplied. Furthermore, the anodes of the light-emitting thyristors T (+), T (31, T (S)) are each connected to a supply line (clock line) to which the transfer lock φ1 is supplied via an anode load resistor RA. and a light emitting thyristor T, 2.
, T , , , are each connected to a supply line (clock line) to which transfer lock φ2 is supplied via an anode load resistor R8.

Next, the operation of the light emitting element array shown in FIG. 6 will be explained.

Note that the turn-on voltage of the light-emitting thyristor is the gate voltage■
. It is known that the diffusion potential is higher by Va=t (approximately 1 (V)).

First, the power supply voltage Vcx (5(v)) is lowered by 1
It is assumed that a start pulse φ having a value higher than [■] is applied to the light emitting thyristor T(.). This causes the light-emitting thyristor T,. , becomes on state (light emitting state). At this time, a gate load resistance R is attached to the gate of the light emitting thyristor T3゜.
Current flows through L.

For this reason, the light emitting thyristor T,. , the gate voltage ■G becomes almost zero volts. At the same time, current also flows into the coupling diode D0 from the right side of FIG. 6, and a potential difference of the diode forward voltage V'dif (approximately 1 (V)) is generated across the coupling diode D0.

Therefore, the gate voltage of the light emitting thyristor T(1) is approximately t
(becomes Vl. At this time, similarly, the coupling diode D1
The gate voltage of the light emitting thyristor T,2) becomes approximately 2 [V] due to the voltage difference between both ends of the light emitting thyristor T,2). Furthermore, the light emitting thyristor T, 3. The gate voltage of the light-emitting thyristors T(1), T(21, T13+) becomes approximately 3(Vl), and the turn-on voltage becomes 2(V) and 3(vL4(V)) respectively. There is.

In this state, transfer lock φ1 is 2 (V: 1 or more 3
When a voltage pulse (high level voltage) of less than [V] is applied to the supply line, only the light emitting thyristor T (1°) is turned on.After that, when the supply of the start pulse φS is stopped, the light emitting thyristor T, . . . is turned off. state, and the on state has moved to the right light emitting thyristor T(1).Hereafter, by applying the transfer locks φ2 and φ1 alternately to the light emitting element in the same way, the on state will move to the right side. To go.

That is, this light emitting element array has a self-scanning function.

Note that the point to be noted here is that the high level voltages of the transfer locks φ1 and φ2 must not overlap.

If both high level voltages overlap, for example, from light emitting thyristor T(1) to light emitting thyristor T, 2. As soon as the on state moves to the light emitting thyristor T4. The gate voltage will also drop.

As a result, the light emitting thyristor T(3) is also turned on. In other words, the on state is suddenly transferred to the right side in FIG. Therefore, the light emitting element array cannot operate normally.

Therefore, delicate adjustment is required to set the width of the high level voltage of the transfer locks φ4 and φ2.

If this delicate adjustment poses a manufacturing problem, it can be solved by increasing the number of transfer locks to three and supplying them to the light emitting elements in sequence. This prevents the sudden transfer of the light emission state as described above.

In addition, light emitting thyristor T(2, to light emitting thyristor T(
, ), the coupling diode D
, becomes reverse biased, the gate voltage of the light emitting thyristor T,1) becomes the power supply voltage VcK (5 (Vl).In other words, the turn-on voltage of the light emitting thyristor T(1) is 6 [v
〕become. Therefore, the light emitting thyristor T(1) does not turn on.

Writing the light emitting element array into an on state is possible by using the start pulse φ, but it is also possible by light. This method utilizes the phenomenon that the turn-on voltage of a light emitting thyristor decreases due to incident light, and was reported by Kuroda et al. at the 1990 Spring Conference on Applied Physics, 30PF-11.

The only way to do this was to set the transfer locks to low level voltage all at once. In this case, all information is erased, which poses a major constraint when optical information processing is performed.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art described above and to provide a light emitting element array in which specific light emitting elements in an information recording state can be brought into an erased state by means of light.

[Problem to be solved by the invention]

In the application of light emitting element arrays to optical information processing such as optical computing, the function of writing information with light and the function of erasing information with light are important.

However, in the conventional light emitting element array described above, information (light emitting state) could not be erased by light. Namely, there is a problem that, first, a specific light emitting element that is in an on state cannot be changed to an off state by light.

Therefore, in order to erase the information written twice [Means for Solving the Problem] In order to achieve the above object, the light emitting element array of the present invention has a A plurality of light emitting elements each having a first control electrode are arranged, and each of the first control electrodes is connected to each other via an electrical means or an optical means, and a light emitting state is caused to each of the light emitting elements. A light emitting element array is provided with second control electrodes for control, and a supply line for supplying voltage or current from the outside is connected to each of the second control electrodes, The light sensing element has a plurality of light sensing elements whose resistance value decreases when detecting light, and the light sensing element is connected to the second light sensing element so that each of the light sensing elements and each of the light emitting elements are connected in parallel. The control electrode is configured to be connected to the control electrode.

Preferably, the light emitting element array of the present invention is configured such that the electrical means is a resistor or an electrical element having electrical unidirectionality.

More preferably, the light emitting element is configured such that a threshold voltage for light emitting operation changes depending on the intensity of light incident on the first control electrode, and the optical means is separate from the light emitting element in the light emitting state. of the first light emitting element of
is configured to guide light to the control electrode of the

[Function] Since the electrical means or optical means connects the first control electrodes of each of the plurality of light emitting elements arranged, it causes an interaction in the threshold voltage for the light emitting operation of the light emitting elements. and provides a self-scanning function to each light emitting element. In addition, the plurality of supply lines supply voltage or current to the second control electrode for controlling the light emitting state of the light emitting element, so that each light emitting element is turned on as appropriate.
Enables writing of information to light emitting elements.

Furthermore, since the photodetecting element connected in parallel with the light emitting element is connected to the second control t-pole, when it is irradiated with light from the outside to turn the light emitting element in the on state into the off state, The resistance decreases to change the voltage or current supplied to the second control electrode.

Therefore, the light emitting element corresponding to the photodetecting element irradiated with light is turned off, so that the information written in the specific light emitting element is erased.

Therefore, since only desired information is selectively erased by light, this light emitting element array is suitable for a wide range of applications as a device for optical computing.

[Example] <Example 1> FIG. 1 is an equivalent circuit diagram showing a first example of a light emitting element array of the present invention. In FIG. 1, the same parts as in FIG. 6 are given the same reference numerals. The configuration of FIG. 1 is almost the same as the light emitting element (light emitting thyristor) array shown in FIG. 6, and the difference is that phototransistors P, 1. ~P(
, ) are connected.

Note that the emitters of each of the phototransistors P(1) to P(,) are grounded. That is, each phototransistor P (+) to P13. is a light emitting thyristor T. ,~T(
, ) are connected in parallel.

Next, the operation of the light emitting element array shown in FIG. 1 will be explained.

However, descriptions of operations common to those in FIG. 6 will be omitted.

It is now assumed that the light emitting thyristor T (3, It is approximately 0 (V).

In this case, the anode current ■ flowing between the anode and cathode of the light-emitting thyristor T, 3°, is the high level voltage of the applied transfer lock φ1, V, g, and the resistance value of the anode load resistor R4 is RAM. Then, it is expressed as IA=(VpshVh)/RAv.

Here, the anode current 1. is the minimum current (hold current) l for maintaining the on state of the light emitting thyristor T(3)
, is set larger than . In this embodiment, the hold current of the light emitting thyristor T(3) is 1t.

is approximately 1 mA.

Now, in this state, when the base of phototransistor P (3) (specifically, the base-emitter junction) is irradiated with light from the outside, the photocurrent generated inside phototransistor P (3) is amplified. and the current IP from the collector
? is drawn in. This current I□ is sufficiently large, and the anode current ■ is sufficient for the anode of the light emitting thyristor T(3).
When the current can no longer flow, the light emitting thyristor T(3) turns off.

The condition for erasing information (on state) in this light-emitting thyrisk is expressed as (V, g, -V,)/RAvTPT<Ih.

Note that the current IPT depends on the light intensity L in incident on the phototransistor P and the current amplification factor of the phototransistor P. In order to increase the sensitivity of erasing information by light, the current amplification factor of the phototransistor P must be increased. There is a need to.

As explained above, according to the light emitting element array shown in FIG. 1, by irradiating the phototransistor P with light, a written on state (light emitting state) can be turned into an off state. That is, it becomes possible to erase information using light. In the first embodiment shown in FIG. 1, a case is shown in which the phototransistor P is connected to all the light emitting thyristors T, but the phototransistor P may be connected only to the necessary light emitting thyristors T. .

Next, FIG. 2 is a longitudinal sectional view for explaining a case where the equivalent circuit of the light emitting element array shown in FIG. 1 is integrated and formed on the same semiconductor substrate. Note that this figure 2 shows the light emitting cyrisk T, 1. of figure 1. , T(2) and phototransistors P n+ , P (21) are shown formed on a semiconductor substrate.

In FIG. 2, the light emitting thyristors T +n, T (Z
l, phototransistor P (11, PC21) and coupling diodes D1, D2 are formed on a substrate l made of n-type GaAs semiconductor.The light-emitting thyristors T, , T, z, are p-type. It is formed of a GaAs semiconductor layer 21, an n-type GaAs semiconductor layer 22, a p-type GaAs semiconductor N23, and an n1 GaAs semiconductor layer 24.

In addition, phototransistors P (11, P (21 are n-type GaAs semiconductor layer 22, p-type GaAs semiconductor layer 23, n
It is formed from a GaAs semiconductor N24. here,
Phototransistor P (+1, P tz+ is npn
Become a transistor. Furthermore, a coupling diode D0,
D2 is formed from a p-type GaAs semiconductor layer 21 and an n-type GaAs semiconductor layer 22.

Next, an example of the manufacturing process for the structure shown in FIG. 2 will be explained.

First, an n-type GaAs semiconductor device 4, a p-type GaAs semiconductor layer 23, an n-type GaAS/semiconductor layer 22,
A p-type GaAs semiconductor layer 21 is formed. Thereafter, only a desired portion of the p-type GaAs semiconductor layer 21 is removed by photoetching using a first photomask. Then, by photoetching using a second photomask, desired portions of the n-type GaAs semiconductor layer 22, P
The GaAs semiconductor layer 23 and the n-type GaAs semiconductor layer 24 are removed.

Next, an insulating film (not shown) called polyimide is formed on this surface. Then, a hole (not shown) called a contact hole for electrical connection is made by a method using a third photomask. At this time, a technique called RIE (reactive ion etching) is used.

After this, a material for forming a resistor and a metal material for wiring are deposited by a vacuum deposition method or the like. This deposited film (shown as an equivalent circuit in FIG. 2) is processed by photoetching using fourth and fifth photomasks. As a result, the equivalent circuit shown in FIG. 1 is realized.

Note that in GaAs semiconductors, the metal materials that allow ohmic contact may be different between p-type and n-type. For example, P-type GaAs semiconductors include AuZn alloys, n-type GaAs
Semiconductors include AuGe alloys and the like. In this case, it is necessary to use two types of wiring metal materials in the above manufacturing process.

In this embodiment, a case has been described in which a coupling diode is used, but a coupling resistor can also be used, and in this case, it is necessary to use three transfer locks.

<Example 2> FIG. 3 is an equivalent circuit diagram showing a second example of the light emitting element array of the present invention. In FIG. 3, the same parts as in FIG. 1 are given the same reference numerals. Note that FIG. 3 shows only the light emitting thyristor T(1) and its peripheral circuits.

The configuration shown in FIG. 3 is almost the same as the configuration of the light emitting element array shown in FIG. 1, and the difference is that the cathodes of photodiodes PD (phototransistors PC1, ~P The anode of each photodiode PD is connected to the ground (instead of the collector of S+).The anode of each photodiode PD is grounded as represented by photodiode PD(1) in the figure. Photodiode PD is light emitting thyristor T
are connected in parallel.

Next, the operation of the light emitting element array shown in FIG. 3 will be explained.

However, descriptions of operations common to those in FIG. 1 will be omitted.

When the erasing light for erasing information is not irradiated, the photodiode P D (1) is reverse biased, so no current flows between the cathode and the anode. Therefore, the original transfer operation in the light emitting element array of this embodiment is not affected by the photodiodes P D , . on the other hand,
When the photodiode PD(1) is irradiated with the erasing light, a current corresponding to the amount of the erasing light flows inside the photodiode PD(1).

Therefore, at least a part of the anode current ■1 flowing through the light emitting thyristor T(1) is transferred to the photodiode PD(1).
). If this current is sufficiently large, the light emitting thyristor T(1) changes from the on state to the off state. Therefore, the light emitting element array of this embodiment operates in exactly the same way as the first embodiment shown in FIG.

<Embodiment 3> FIG. 4 is an equivalent circuit diagram showing a third embodiment of the light emitting element array of the present invention. In FIG. 4, the same parts as in FIG. 1 are given the same reference numerals. Note that FIG. 4 shows only the light emitting thyristor T(1) and its peripheral circuits.

The configuration shown in FIG. 4 is almost the same as the configuration of the light emitting element array shown in FIG.
dS is connected to one end of the photoconductive resistor PR (instead of the collectors of the phototransistors P Tl to P (S)).

Note that the other end of each photoconductive resistor PR is grounded as shown. That is, each photoconductive resistor PR is connected to the light emitting thyristor T in parallel.

Next, the operation of the light emitting element array shown in FIG. 4 will be explained.

However, descriptions of operations common to those in FIG. 1 will be omitted.

When erasing light for erasing information is not irradiated, the resistance value of the photoconductive resistor PR(11) is sufficiently high. Therefore, the current flowing through the photoconductive resistor PR(1) is sufficiently small. Therefore, the original transfer operation in the light emitting element array of this embodiment is not affected by the photoconductive resistor PR+11.On the other hand, when the photoconductive resistor PR(1) is irradiated with erase light,
The resistance value of the photoconductive resistor P Rl,) decreases depending on the amount of erasing light.

Therefore, at least a portion of the anode current IA flowing through the light emitting thyristor T(1) is transferred to the photoconductive resistor PR(
It flows towards 1). If this current is sufficiently large, the light emitting thyristor T(1) changes from the on state to the off state. Therefore, the light emitting element array of this example is the first one shown in FIG.
The operation is exactly the same as in the embodiment (and thus the second embodiment shown in FIG. 3).

<Embodiment 4> FIG. 5 is an equivalent circuit diagram showing a fourth embodiment of the light emitting element array of the present invention. In FIG. 5, the same parts as in FIG. 1 are given the same reference numerals. The configuration shown in FIG. 5 is almost the same as the configuration of the light emitting element array shown in FIG. The method has been changed to one that uses optical coupling between the two.

For this purpose, in FIG. 5, the coupling diodes D, ~D4, gate load resistance R4, and power supply voltage (2) in FIG. 1 are used. A DC power supply is not provided, and a supply line (clock line) to which the transfer lock φ3 is supplied is newly provided. Then, each light emitting thyristor T (11~
The anodes of T(5,
connected to each supply line.

In this method using optical coupling, for example, a light emitting thyristor T
(When 31 is in the on state (light emitting state), the emitted light is configured to enter the adjacent light emitting thyristors T, 2., T, 4. Then, this incident light causes the light emitting thyristors to The structure is such that the turn-on voltages of T(2), T, and 4 are reduced.

Therefore, when a high-level voltage is sequentially applied to the transfer locks φ0, φ2, and φ3, the on state is transferred by optical coupling of the light emitting thyristor T.

Next, the operation of the light emitting element array shown in FIG. 5 will be explained.

However, descriptions of operations common to those in FIG. 1 will be omitted.

When the light-emitting thyristor T(3) is in the on state, when the base (base-emitter junction) of the phototransistor P(,) is irradiated with light from the outside, a current I, from the collector of the phototransistor P(,), □ is drawn in. If this current IPT is large enough, the light emitting thyristor T (3,
is turned off.

In this embodiment, the case where the phototransistor P is connected in parallel to the light emitting thyristor (light emitting element) T has been described, but the case where the photodiode PD is connected as shown in FIG. As shown, the photoconductive resistor PR
A similar operation is performed when the two are connected.

- [Effects of the Invention] Since the present invention is configured as described above, it is possible to change a specific light emitting element that is in an on state to an off state by, for example, incident light from the outside. That is, information can be erased by external incident light.

Therefore, according to the present invention, there is provided a light emitting element array that has the three functions of writing information, moving (transferring) information, and erasing information using light, which are important in optical information processing such as optical computing. be able to.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram showing a first embodiment of the light emitting element array of the present invention, and FIG. 2 is for explaining the case where the equivalent circuit shown in FIG. 1 is integrated and formed on the same semiconductor substrate. 3 is an equivalent circuit diagram showing a second embodiment of the light emitting element array of the present invention, and FIG. 4 is an equivalent circuit diagram showing a third embodiment of the light emitting element array of the present invention.
FIG. 5 is an equivalent circuit diagram showing a fourth embodiment of the light emitting element array of the present invention, and FIG. 6 is an equivalent circuit diagram showing a conventional light emitting element array. In addition, in the symbols used in the drawings, 1----------111--substrate 21---111------------P type Ga
As semiconductor layer 22 ------- N-type GaAs semiconductor layer 23 ---m --- P-type GaAs semiconductor layer 24 ------- N-type GaAs semiconductor layer T(., ~T (S)-------・--・--Light-emitting thyristor D0-Ds "'-'--・----1--
--Coupling diode (electrical means) φ, ~φ, -------------1・-------111 transfer lock P(,〉~P (S) """'−”−−
'-It is a phototransistor. PDLl. PRt. (Photodetection element) Photodiode (Photodetection element) ・--111 Photoconductive resistor (Photodetection element)

Claims (1)

[Claims] 1. First for controlling the threshold voltage for light emission operation
A plurality of light emitting elements each having a control electrode are arranged, and each of the first control electrodes is connected to each other via electrical means or optical means to control the light emitting state of each of the light emitting elements. A light emitting element array is provided with second control electrodes for supplying light from the outside, and a supply line for supplying voltage or current from the outside is connected to each of the second control electrodes, the light emitting element array comprising: The photodetecting element has a plurality of photodetecting elements whose resistance value decreases when detected, and the photodetecting element is connected to the second control electrode so that each of the photodetecting elements and each of the light emitting elements are connected in parallel. A light emitting element array, characterized in that the light emitting element array is connected to. 2. The light emitting element array according to claim 1, wherein the electrical means is a resistor or an electrical element having electrical unidirectionality. 3. In the light emitting element array according to claim 1, the light emitting elements are configured such that a threshold voltage for light emitting operation changes depending on the intensity of light incident on the first control electrode, and the optical means comprises: A light emitting element array, characterized in that the light emitting element array is configured to guide light from the light emitting element in a light emitting state to the first control electrode of another light emitting element.