JP3523644B2 - Light emitting element array - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a light emitting element array having a self-scanning function capable of erasing information written in a light emitting element by incident light, and in particular, to a light emitting element array. The present invention relates to a light emitting element array suitable for application to optical information processing such as optical computing.

[Conventional technology]

FIG. 6 is an equivalent circuit diagram showing a conventional light emitting element array. In FIG. 6, T _{(0) to} T ₍₅₎ are light emitting thyristors (light emitting elements) whose cathodes are grounded. Gate of each light emitting thyristor T _{(0) to} T ₍₅₎ (first control electrode)
The coupling diodes D _{0 to} D ₅ are connected to each other.
Further, the light-emitting thyristor T ₍₀₎ at the supply voltage V _GK (this prior art by the respective gates gate load resistor R _L of the through T ₍₅₎ 5
[V] is assumed. ) Is connected to the DC power supply.

On the other hand, the anode of the light emitting thyristor T ₍₀₎ is connected to the supply line to which the start pulse φ _S is supplied via the anode load resistor _RA . Also a light emitting thyristor
The transfer clock φ ₁ is connected to the supply line (clock line) through the anode load resistor _RA for each of the anodes of T ₍₁₎ , T ₍₃₎ , and T ₍₅₎ . The respective anodes of the light emitting thyristors T ₍₂₎ and T ₍₄ ) are connected to the supply line (clock line) to which the transfer clock φ ₂ is supplied via the anode load resistance _RA .

Next, the operation of the light emitting element array shown in FIG. 6 will be described. It is known that the turn-on voltage of the light emitting thyristor is higher than the gate voltage V _G by the diffusion potential V _dif (about 1 [V]).

First of all, it is 1 more than the power supply voltage V _GK (5 [V])
It is assumed that the start pulse φ _S having a higher value than [V] is applied to the light emitting thyristor T ₍₀₎ . As a result, the light emitting thyristor T ₍₀₎ is turned on (light emitting state). At this time, a current flows into the gate of the light emitting thyristor T ₍₀₎ via the gate load resistor R _L. Therefore, the gate voltage V _G of the light emitting thyristor T ₍₀₎ becomes almost zero volt. At the same time, the coupling diode
A current also flows into D ₀ from the right side of FIG. 6, and a potential difference of the diode forward voltage V ^D _dif (about 1 [V]) is generated across the coupling diode D ₀ .

Therefore, the gate voltage of the light emitting thyristor T ₍₁₎ is about 1
It becomes [V]. At this time, similarly, the gate voltage of the light emitting thyristor T ₍₂₎ becomes about 2 [V] due to the voltage difference across the coupling diode D ₁ . Further, the gate voltage of the light emitting thyristor T ₍₃₎ becomes about 3 [V] by the coupling diode D ₂ . That is, the turn-on voltage is the light emitting thyristor T ₍₁₎ , T
₍₂₎ and T ₍₃₎ are 2 [V], 3 [V] and 4 [V], respectively.
It is [V].

In this state, the transfer clock φ ₁ is 2 [V] or more 3
When a voltage pulse (high level voltage) of less than [V] is applied to the supply line, only the light emitting thyristor T ₍₁₎ is turned on. After that, when the supply of the start pulse φ _S is stopped, the light emitting thyristor T ₍₀₎ is turned off, and the on state is moved to the right light emitting thyristor T ₍₁₎ . Thereafter, similarly, the transfer clocks φ ₂ and φ ₁ are alternately applied to the light emitting element to shift the ON state to the right. That is, this light emitting element array has a self-scanning function.

The points to be noted here are the transfer clocks φ ₁ and φ ₂
It means that the high level voltage of must not be overlapped. If the high-level voltages of the two overlap, the gate voltage of the light-emitting thyristor T ₍₃₎ will drop as soon as the ON state moves from the light-emitting thyristor T ₍₁₎ to the light-emitting thyristor T ₍₂₎ . Therefore, the light emitting thyristor T ₍₃₎ is also turned on. That is, the ON state is suddenly transferred to the right side in FIG. Therefore, the light emitting element array cannot operate normally.

Therefore, delicate adjustment is required to set the width of the high-level voltage of the transfer clocks φ ₁ and φ ₂ . If this delicate adjustment causes a problem in manufacturing, it can be solved by increasing the number of transfer clocks to three and supplying them to the light emitting elements in order. This prevents the abrupt transfer of the light emitting state as described above.

Further, when the ON state moves from the light emitting thyristor T ₍₂₎ to the light emitting thyristor T ₍₃₎ , the coupling diode D ₁ is reverse biased, so that the gate voltage of the light emitting thyristor T ₍₁₎ is the power supply voltage V It becomes _GK (5 [V]). That is, the turn-on voltage of the light emitting thyristor T ₍₁₎ becomes 6 [V]. Therefore,
The light emitting thyristor T ₍₁₎ does not turn on.

On-state writing to this light emitting element array is
It is possible to use the start pulse φ _S , but it is also possible to use light. This method utilizes the phenomenon that the turn-on voltage of the light-emitting thyristor is lowered by the incident light, and was reported by Kuroda et al. In the 30th Spring Applied Physics Association Joint Lecture, 30P-F-11.

[Problems to be solved by the invention]

In the application of the light emitting element array to optical information processing such as optical computing, the function of writing information by light and the function of erasing information by light are important. However, in the above-mentioned conventional light emitting element array, information (light emitting state) cannot be erased by light. That is, there is a problem that a specific light emitting element in the on state cannot be changed to the off state by light.

Therefore, in order to erase the information once written,
There was no choice but to set the transfer clocks to a low level voltage all at once. In this case, all the information is erased, which is a great limitation when performing optical information processing.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a light emitting element array capable of erasing a specific light emitting element in an information recording state by light.

[Means for Solving the Problems]

In order to achieve the above object, the light emitting device array of the present invention includes a first light emitting device for controlling a threshold voltage for a light emitting operation.
A plurality of light emitting elements each having a control electrode are arranged, and each of the first control electrodes is connected to each other through an electric means or an optical means to control a light emitting state of each of the light emitting elements. A light-emitting element array in which a second control electrode is provided, and a supply line for supplying a voltage or a current from the outside is connected to each of the second control electrodes. A plurality of photodetecting elements whose resistance values are reduced by detection, and the photodetecting elements are connected in parallel to each of the photodetecting elements and each of the light emitting elements. Configured to be connected to.

Further preferably, the light emitting element array of the present invention is configured such that the electric means is an electric element having resistance or electrical unidirectionality.

More preferably, the light emitting element is configured such that a threshold voltage for a light emitting operation is changed according to the intensity of light incident on the first control electrode, and the optical means is separated from the light emitting element in a light emitting state. Is configured to direct light to the first control electrode of the light emitting device.

[Action]

The electrical means or the optical means connects the respective first control electrodes of the plurality of light emitting elements which are arranged, so that the threshold voltage for the light emitting operation of the light emitting elements interacts with each other, and The self-scanning function is given to the light emitting element. Further, since the plurality of supply lines supply voltage or current to the second control electrode for controlling the light emitting state of the light emitting element, each light emitting element is appropriately turned on to write information to the light emitting element. To enable.

Further, since the light detecting element connected in parallel with the light emitting element is connected to the second control electrode, when the light for turning the light emitting element in the on state to the off state is externally irradiated, the resistance is reduced. Decrease to change the voltage or current supplied to the second control electrode. Therefore, the light emitting element corresponding to the light detecting element irradiated with light is turned off, and the information written in the specific light emitting element is erased.

Therefore, since only desired information is selectively erased by light, this light emitting element array is suitable for a wide range of applications as a device for optical computing.

〔Example〕

<Embodiment 1> FIG. 1 is an equivalent circuit diagram showing a first embodiment of the light emitting element array of the present invention. In FIG. 1, the same parts as those in FIG. 6 are designated by the same reference numerals. The configuration of FIG. 1 is almost the same as that of the light emitting element (light emitting thyristor) array shown in FIG. 6, except that the phototransistor P _{(1 )} is provided to each of the anodes of the light emitting thyristors T _{(1) to} T _{(5). )} ~ P ₍₅₎ collectors are connected.

The emitters of the phototransistors P _{(1) to} P ₍₅₎ are grounded. That is, each phototransistor P ₍₁₎
~ P ₍₅₎ are connected in parallel to the light emitting thyristors T _{(1) to} T ₍₅₎ .

Next, the operation of the light emitting element array shown in FIG. 1 will be described. However, the description of the operation common to FIG. 6 is omitted.

Now, it is assumed that the light emitting thyristor T ₍₃₎ is in the ON state. At this time, the anode of the light emitting thyristor T ₍₃₎ is about 1 [V] (anode on-state voltage V _h ) and the gate is about 0 [V]. In this case, the anode current I _A flowing between the anode and the cathode of the light emitting thyristor T ₍₃₎ is V _φh which is the high level voltage of the applied transfer clock φ ₁ , and the resistance value of the anode load resistor R _A is R _AV. Then, I _A = (V _φh −V _h ) / R _AV

Here, the anode current I _A is set to be larger than the minimum current (hold current) I _h for maintaining the ON state of the light emitting thyristor T ₍₃₎ . In this embodiment, the light emitting thyristor T ₍₃₎
The hold current I _h is about 1 mA.

In this state, when the base of the phototransistor P ₍₃₎ (specifically, the base-emitter junction) is irradiated with light from the outside, the photocurrent generated inside the phototransistor P ₍₃₎ changes. It is amplified and the current I _PT is drawn from the collector. The current I _PT is sufficiently large, a sufficient anode current I _A to the anode of the light-emitting thyristor T ₍₃₎ is not flowed, the light-emitting thyristor T ₍₃₎ is turned off. Conditions of erasing of information (on-state) in the light-emitting thyristor is represented by _{(V φh -V h) / R} AV -I PT <I h.

The current I _PT depends on the light intensity L _in incident on the phototransistor P and the current amplification factor of the phototransistor P. To increase the sensitivity of erasing information by light, the current amplification factor of the phototransistor P is set to Need to be bigger.

As described above, according to the light emitting element array shown in FIG. 1, the written on state (light emitting state) can be turned off by irradiating the phototransistor P with light. That is, information can be erased by light. In the first embodiment shown in FIG. 1, the phototransistors P are connected to all the light emitting thyristors T, but the phototransistors P may be connected only to the necessary light emitting thyristors T. .

Next, FIG. 2 is a vertical cross-sectional view for explaining a case where equivalent circuits of the light-emitting element array shown in FIG. 1 are integrated and formed on the same semiconductor substrate. This FIG. 2 shows the light emitting thyristors T ₍₁₎ , T ₍₂₎ and the phototransistor of FIG.
It shows a case where P ₍₁₎ and P ₍₂₎ are formed on a semiconductor substrate.

In FIG. 2, light emitting thyristors T ₍₁₎ and T ₍₂₎ , phototransistors P ₍₁₎ and P ₍₂₎ , and coupling diodes D ₁ and D ₂ are formed on a substrate 1 made of an n-type GaAs semiconductor. Has been done. The light emitting thyristors T ₍₁₎ and T ₍₂₎ are p-type GaAs semiconductor layers 2
1, n-type GaAs semiconductor layer 22, p-type GaAs semiconductor layer 23, n-type GaA
s It is formed from the semiconductor layer 24.

The phototransistors P ₍₁₎ and P ₍₂₎ are composed of an n-type GaAs semiconductor layer 22, a p-type GaAs semiconductor layer 23, and an n-type GaAs semiconductor layer 24. Where the phototransistors P ₍₁₎ and P ₍₂₎ are
Become an npn transistor. Furthermore, coupling diodes
D ₁ and D ₂ are formed of a p-type GaAs semiconductor layer 21 and an n-type GaAs semiconductor layer 22.

Next, an example of a manufacturing process for the structure shown in FIG. 2 will be described.

First, MOVPE (Metal Organic Chemical Vapor Deposition) on the substrate 1
As a result, the n-type GaAs semiconductor layer 24, the p-type GaAs semiconductor layer 23, the n-type GaAs semiconductor layer 22, and the p-type GaAs semiconductor layer 21 are sequentially formed. After that, only a desired portion of the p-type GaAs semiconductor layer 21 is removed by a photoetching technique using the first photomask. Then, the n-type GaAs semiconductor layer 22, the p-type GaAs semiconductor layer 23, and the n-type GaAs semiconductor layer 24 in desired portions are removed by photoetching using the second photomask.

Next, an insulating film (not shown) called polyimide is formed on this surface. Then, a hole called a contact hole (not shown) for electrical connection is formed by a method using a third photomask. At this time, a method called RIE (reactive ion etching) is used.

After that, a material for forming a resistor and a metal material for wiring are deposited by a vacuum deposition method or the like. This vapor-deposited film (shown by the equivalent circuit in FIG. 2) is processed by photoetching with the fourth and fifth photomasks. As a result, the equivalent circuit shown in FIG. 1 is realized.

In the case of a GaAs semiconductor, the p-type and n-type may differ in the metal material capable of making ohmic contact. For example,
AuZn alloy for p-type GaAs semiconductor, AuGe for n-type GaAs semiconductor
Alloys and the like. In this case, it is necessary to form two kinds of metal materials for wiring in the above manufacturing process.

Although the case where the coupling diode is used has been described in the present embodiment, the coupling resistor may be used, and in this case, it is necessary to use three transfer clocks.

<Embodiment 2> FIG. 3 is an equivalent circuit diagram showing a second embodiment of the light emitting element array of the present invention. 3, the same parts as those in FIG. 1 are designated by the same reference numerals. In FIG. 3, only the light emitting thyristor T ₍₁₎ and its peripheral circuits are shown.

The structure shown in FIG. 3 is almost the same as the structure of the light emitting element array shown in FIG. 1, except that the cathodes of the photodiodes PD (phototransistors P ₍₁₎ to Be connected ₍ instead of the collector of P ₍₅₎₎ . The anode of each photodiode PD is grounded as represented by the photodiode PD ₍₁₎ in the figure. That is, each photodiode PD is connected in parallel to the light emitting thyristor T.

Next, the operation of the light emitting element array shown in FIG. 3 will be described. However, the description of the operation common to FIG. 1 is omitted.

When not erasing light for erasing information,
Since the photodiode PD ₍₁₎ is reverse-biased, no current flows between the cathode and anode. Therefore, the original transfer operation in the light emitting element array of this embodiment is not affected by the photodiode PD ₍₁₎ . On the other hand, when the erasing light is applied to the photodiode PD ₍₁₎ , a current according to the light amount of the erasing light flows inside the photodiode PD ₍₁₎ .

Therefore, at least a part of the anode current I _A flowing through the light emitting thyristor T ₍₁₎ flows toward the photodiode PD ₍₁₎ . If this current is large enough, the light emitting thyristor
T ₍₁₎ goes from on to off. Therefore, the light emitting element array of this embodiment operates exactly as in the case of the first embodiment shown in FIG.

<Embodiment 3> FIG. 4 is an equivalent circuit diagram showing a third embodiment of the light emitting element array of the present invention. 4, the same components as those in FIG. 1 are designated by the same reference numerals. In FIG. 4, only the light emitting thyristor T ₍₁₎ and its peripheral circuits are shown.

The structure shown in FIG. 4 is almost the same as the structure of the light emitting element array shown in FIG. 1, and the difference is that the resistivity of each anode of the light emitting thyristor T is changed by light.
One end of the photoconductive resistance PR such as CdS is (phototransistor P
_{(1) to} P ₍₅₎ instead of collectors ₎ .

The other end of each photoconductive resistor PR is grounded as shown. That is, each photoconductive resistor PR is connected in parallel to the light emitting thyristor T.

Next, the operation of the light emitting element array shown in FIG. 4 will be described. However, the description of the operation common to FIG. 1 is omitted.

When not erasing light for erasing information,
The resistance value of the photoconductive resistance PR ₍₁₎ is sufficiently high. For this reason,
The current flowing through the photoconductive resistor PR ₍₁₎ is sufficiently small. Therefore, the original transfer operation in the light emitting element array of this embodiment is not affected by the photoconductive resistance PR ₍₁₎ . On the other hand, if the erasing light is irradiated on the optical conductivity type resistor PR _(1), the resistance value of the optical conductivity type resistor PR ₍₁₎ is reduced according to the amount of erasing light.

Therefore, at least part of the anode current I _A flowing through the light emitting thyristor T ₍₁₎ flows toward the photoconductive resistance PR ₍₁₎ . If this current is large enough, the light emitting thyristor T
₍₁₎ changes from the on state to the off state. Therefore, the light-emitting element array of this embodiment operates exactly as in the case of the first embodiment shown in FIG. 1 (and thus the second embodiment shown in FIG. 3).

<Embodiment 4> FIG. 5 is an equivalent circuit diagram showing a fourth embodiment of the light emitting element array of the present invention. 5, the same parts as those in FIG. 1 are designated by the same reference numerals. The configuration shown in FIG. 5 is almost the same as the configuration of the light emitting element array shown in FIG. 1, except that the configuration using the coupling diodes D _{1 to} D ₄ is different from that of the light emitting thyristors T _{(1) to} T ₍₅ That is, the method has been changed to a method using optical coupling between the two ₎ .

For this reason, in FIG. 5, the coupling diodes D _{1 to} D ₄ , the gate load resistance R _L and the DC power supply of the power supply voltage V _GK in FIG. ₁ are not provided, and the transfer clock φ ₃ is supplied. A line (clock line) is newly provided. Then, the anodes of the respective light emitting thyristors T _{(1) to} T ₍₅₎ are sequentially connected to the supply lines of the transfer clocks φ ₁ , φ ₂ , and φ ₃ via the anode load resistor _RA from the left side of FIG. It is connected.

In the method using this optical coupling, for example, a light emitting thyristor is used.
When T ₍₃₎ is in the ON state (light emitting state), the emitted light is configured to enter the adjacent light emitting thyristors T ₍₂₎ and T ₍₄₎ . Then, the incident light reduces the turn-on voltage of the light emitting thyristors T ₍₂₎ and T ₍₄₎ .

Therefore, when the high level voltage is sequentially applied to the transfer clocks φ ₁ , φ ₂ , and φ ₃ , the ON state is transferred by the optical coupling of the light emitting thyristor T.

Next, the operation of the light emitting element array shown in FIG. 5 will be described. However, the description of the operation common to FIG. 1 is omitted.

When the light-emitting thyristor T ₍₃₎ is in the ON state and the base (base-emitter junction ₎ of the phototransistor P ₍₃₎ is irradiated with light from the outside, a current I from the collector of the phototransistor P ₍₃₎ is generated. _PT is pulled in. When this current I _PT is sufficiently large, the light emitting thyristor T ₍₃₎ is turned off.

In this embodiment, the case where the phototransistor P is connected in parallel to the light emitting thyristor (light emitting element) T has been described, but the case where the photodiode PD is connected as shown in FIG. 3 and the case shown in FIG. Similar operation is performed when the photoconductive resistor PR is connected as shown.

〔The invention's effect〕

Since the present invention is configured as described above,
For example, a specific light emitting element in the on state can be changed to the off state by incident light from the outside. That is,
Information can be erased by incident light from the outside.

Therefore, according to the present invention, it is possible to provide a light emitting element array having three functions which are important in optical information processing such as optical computing: writing information, moving (transferring) information, and erasing information by light. You can

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram showing a first embodiment of a light emitting device array of the present invention, and FIG. 2 is a diagram for explaining a case where the equivalent circuit shown in FIG. 1 is integrated and formed on the same semiconductor substrate. FIG. 3 is an equivalent circuit diagram showing a second embodiment of the light emitting element array of the present invention, and FIG. 4 is an equivalent circuit diagram showing a third embodiment of the light emitting element array of the present invention.
FIG. 5 is an equivalent circuit diagram showing a fourth embodiment of the light emitting device array of the present invention, and FIG. 6 is an equivalent circuit diagram showing a conventional light emitting device array. In the reference numerals used in the drawings, 1 ... Substrate 21 ... P-type GaAs semiconductor layer 22 ... N-type GaAs semiconductor layer 23 ... P-type GaAs semiconductor layer 24 ... N-type GaAs semiconductor layer T ₍₀₎ . T ₍₅₎ ...... Light emitting thyristor D _{0 to} D ₅ …… Coupling diode (electrical means) φ _{1 to} φ ₃ …… Transfer clock P _{(1) to} P ₍₅₎ …… Phototransistor (light detection element) PD ₍₁₎ …… Photodiode ₍ photodetector) PR ₍₁₎ …… Photoconductive resistance (photodetector).

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-2-14584 (JP, A) JP-A-52-31648 (JP, A) JP-A-63-238717 (JP, A) JP-A-2- 13010 (JP, A) JP 60-115263 (JP, A) JP 58-21867 (JP, A) JP 1-143365 (JP, A) JP 4-1996 (JP, A) JP-A-48-83742 (JP, A) Actually-developed Sho-56-108378 (JP, U) Teruo Imura et al., Thyristor electronics 2 thyristor circuit, Japan, Maruzen Co., Ltd., January 30, 1974, p. 38-53 (58) Fields investigated (Int.Cl. ⁷ , DB name) G06E 3/00 G11C 11/42 G11C 13/08 G11C 19/30 H01L 27/10 H01L 33/00 H03K 17/725

Claims (3)

(57) [Claims] 1. A plurality of light emitting elements each having a first control electrode for controlling a threshold voltage for a light emitting operation are arranged, each of the first control electrodes being an electric means or an optical means. Second control electrodes for controlling the light emitting state are provided to each of the light emitting elements, and a voltage or current is externally supplied to each of the second control electrodes. A light emitting element array to which a supply line is connected, the light emitting element array having a plurality of light detecting elements for detecting light from the outside and having a resistance value reduced, and each of the light detecting elements and each of the light emitting elements. The light emitting element array, wherein the light detecting element is connected to the second control electrode so that and are connected in parallel. 2. The light emitting element array according to claim 1, wherein the electrical means is a resistance or an electrical element having electrical unidirectionality. 3. The light emitting element array according to claim 1, wherein the light emitting element is configured such that a threshold voltage for a light emitting operation is changed according to an intensity of light incident on the first control electrode. The light emitting element array, wherein the target means is configured to guide light from the light emitting element in a light emitting state to the first control electrode of another light emitting element.