JPH0474393A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To correctly execute the read-out of an EPROM after the oscillation is started by providing a boosting waiting circuit for controlling a clock of a timing generator for outputting a read-out signal of the EPROM until a boosting voltage of a boosting circuit is charged up. CONSTITUTION:An output signal 3 of an oscillator 2 whose oscillation can be stopped by an oscillation stop signal 1 is inputted to a boosting circuit 6 for generating a boosting voltage 5 required for an operation of an EPROM 4, and a boosting waiting circuit 10 for controlling a clock 9 for operating a timing generator 8 for outputting a read-out signal 7 of the EPROM 4. Accordingly, the read-out signal 7 outputted form the timing generator 8 is outputted at a third shot of the clock 9, that is at a seventh shot of the output signal 3 of the oscillator 2, and thereafter, every fifth shot. In such a way, the boosting voltage 5 reaches a voltage for operating correctly the EPROM 4 and from the EPROM 4, correct data is outputted to a CPU 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit incorporating an EPROM operated by a booster circuit.

[Conventional technology]

FIG. 4 is a block diagram of a conventional semiconductor integrated circuit incorporating an EPROM operated by a booster circuit. An oscillator 2 whose oscillation can be stopped by the oscillation stop signal 1, a booster circuit 6 which boosts the voltage by the output signal 3 of the oscillator 2, an EPROM 4 which operates by the boosted voltage 5 of the booster circuit 6, and a readout of the EPROM 4 by the output signal 3 of the oscillator 2. It has a timing generator 8 that outputs a signal 7, and the read signal 7 causes the EPROM 4 to output data to the CPU II.

FIG. 5 is a waveform diagram explaining the operation of each block. T
Until timing 51, all blocks are stopped or reset due to the oscillation stop signal l being at the "H" level, and the booster circuit is also stopped in order to reduce current consumption.

After timing T51, the oscillation stop signal 1 becomes "L" level and each block starts operating. Timing generator 8 receives output signal 3 from oscillator 2 and first
At the start, read signal 7 of EPROM4 is sent every 4 times thereafter.
Output. The booster electrician 5 of the booster circuit 6 gradually increases in response to the output signal 3 of the oscillator 2, and at the 306th output signal, the voltage increases to a voltage that can be read from the EPROM 4.

[Problem to be solved by the invention]

After the conventional oscillation starts as described above, EP starts at timing T52.
Even if the ROM 4 is read, the boosted voltage 5 is insufficient, causing the problem that the EPROM 4 does not operate properly and cannot output correct data to the CPU II.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention has an E
It includes a boost wait circuit that controls the clock of a timing generator that inputs and outputs PROM read signals.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The output signal 3 of the oscillator 2, which can stop oscillation by the oscillation stop signal l, controls the clock 9 that operates the booster circuit 6 that generates the boosted voltage 5 necessary for the operation of the EPROM 4 and the timing generator 8 that outputs the read signal 7 for the EPROM 4. It serves as an input to the boost waiting circuit 10. FIG. 2 is an example of the boost waiting circuit IO of FIG. 1. FIG. 3 is a waveform diagram for explaining the operation of each block and each point when the circuit of FIG. 2 is used in the boost waiting circuit 10 of FIG. 1. Up to T31, the booster circuit 6 of the oscillator 2 is stopped due to the oscillation stop signal being at the "H" level, and the timing generator 8 is reset and the binary flip-flops 12, 1 forming the frequency divider circuit of the booster wait circuit IC+ are activated.
3. '14 are each reset, and the RS latch 15 is also reset, so that the clock 9 that operates the timing generator 8 is at the "L" level. T
After 31, the oscillation stop signal 1 becomes "L" level and the oscillator 2
outputs an output signal 3, a booster circuit 6 outputs a boosted voltage 5, and the sixth output of the output signal 3 reaches a voltage at which the read operation of the EPROM 4 can be performed accurately. Furthermore, the frequency divider circuit composed of flip-flops 12, 13, and 14 of the boost waiting circuit 10 is activated by the output signal 3 of the oscillator 2, and outputs 8 outputs 21, 22°23, and when the timing of Ta2 comes, the boost waiting circuit 10 is activated. The RS latch 15 of the circuit 10 is set, and the timing generator 8 is supplied with a clock 9 having the same phase as the output signal 3 of the oscillator 2. After T32, the reading ratio signal 7 output from the timing generator 8 is the clock 9.
The third shot, that is, the 307th shot K1 of the output signal of oscillator 2
After that, it will be output every 4 shots. - Therefore, at the timing of Ta2, the boosted voltage 5 has reached a voltage sufficient to properly operate the EPROM 4, and the correct data is outputted from the EPROM 4 to CFULL.

〔Effect of the invention〕

As explained above, the present invention provides a boost wait circuit that controls the clock of the timing generator that outputs the EPROM read signal until the boosted voltage of the booster circuit is charged up.
This has the effect of being able to read out data.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the semiconductor integrated circuit of the present invention, FIG. 2 is an example of the boost waiting circuit used in FIG. 1, FIG. 3 is a waveform diagram of one embodiment, and FIG. 4 is a block diagram of a conventional semiconductor integrated circuit, and FIG. 5 is a waveform diagram thereof. 1... Oscillation stop signal, 2... Oscillator,
3...Oscillator output signal, 4...EPR
OM, 5... Boost voltage, 6... Boost circuit, 7... Read signal, 8... Timing generator, 9... Clock , 10・
...boost waiting circuit, 11 ... CPU, 12
, 13° 14... Binary flip-flop, 15... RS latch, 16.17, 18.
20...Inverter circuit, 19...N
AND circuit, 21, 22° 23...output signal. Agent patent attorney Shindai Uchihara! Koumekuni j2 Kaya review

Claims (1)

[Claims] An oscillator that can stop oscillation, a booster circuit that boosts the voltage using the output of the oscillator, an EPROM that operates using the boosted voltage of the booster circuit, and an EPROM that operates using the boosted voltage of the booster circuit.
A semiconductor integrated circuit having a timing generator that outputs a ROM read signal, characterized in that the timing generator is provided with a boost waiting circuit that controls clock supply until the boosted voltage of the booster circuit is almost charged up. integrated circuit.